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[refactor] reposition implementations of unit test hw helper

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- remove double implementation between similar hw generation.
- group the same implementations into dedicated inl files.

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
This commit is contained in:
Zbigniew Zdanowicz
2023-04-12 21:33:35 +00:00
committed by Compute-Runtime-Automation
parent 63eb88b819
commit d48f5b01f6
12 changed files with 208 additions and 195 deletions
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17
shared/test/common/gen11/unit_test_helper_gen11.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -20,20 +20,5 @@ uint32_t UnitTestHelper<Family>::getDebugModeRegisterOffset() {
return 0x20d8;
}
template <>
uint32_t UnitTestHelper<Family>::getDebugModeRegisterValue() {
return (1u << 5) | (1u << 21);
}
template <>
uint32_t UnitTestHelper<Family>::getTdCtlRegisterOffset() {
return 0xe400;
}
template <>
uint32_t UnitTestHelper<Family>::getTdCtlRegisterValue() {
return (1u << 7) | (1u << 4);
}
template struct UnitTestHelper<Gen11Family>;
} // namespace NEO

17
shared/test/common/gen12lp/unit_test_helper_gen12lp.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -36,21 +36,6 @@ uint32_t UnitTestHelper<Family>::getDebugModeRegisterOffset() {
return 0x20d8;
}
template <>
uint32_t UnitTestHelper<Family>::getDebugModeRegisterValue() {
return (1u << 5) | (1u << 21);
}
template <>
uint32_t UnitTestHelper<Family>::getTdCtlRegisterOffset() {
return 0xe400;
}
template <>
uint32_t UnitTestHelper<Family>::getTdCtlRegisterValue() {
return (1u << 7) | (1u << 4);
}
template <>
bool UnitTestHelper<Family>::getDisableFusionStateFromFrontEndCommand(const typename Family::VFE_STATE_TYPE &feCmd) {
return feCmd.getDisableSlice0Subslice2();

12
shared/test/common/gen8/unit_test_helper_gen8.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -25,15 +25,5 @@ uint32_t UnitTestHelper<Family>::getDebugModeRegisterValue() {
return (1u << 6) | (1u << 22);
}
template <>
uint32_t UnitTestHelper<Family>::getTdCtlRegisterOffset() {
return 0xe400;
}
template <>
uint32_t UnitTestHelper<Family>::getTdCtlRegisterValue() {
return (1u << 7) | (1u << 4);
}
template struct UnitTestHelper<Gen8Family>;
} // namespace NEO

12
shared/test/common/gen9/unit_test_helper_gen9.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -29,15 +29,5 @@ uint32_t UnitTestHelper<Family>::getDebugModeRegisterValue() {
return (1u << 6) | (1u << 22);
}
template <>
uint32_t UnitTestHelper<Family>::getTdCtlRegisterOffset() {
return 0xe400;
}
template <>
uint32_t UnitTestHelper<Family>::getTdCtlRegisterValue() {
return (1u << 7) | (1u << 4);
}
template struct UnitTestHelper<Family>;
} // namespace NEO

44
shared/test/common/helpers/unit_test_helper.inl
View File

@@ -16,13 +16,13 @@
namespace NEO {
template <typename GfxFamily>
bool UnitTestHelper<GfxFamily>::isPageTableManagerSupported(const HardwareInfo &hwInfo) {
return false;
uint32_t UnitTestHelper<GfxFamily>::getTdCtlRegisterOffset() {
return 0xe400;
}
template <typename GfxFamily>
inline uint32_t UnitTestHelper<GfxFamily>::getAppropriateThreadArbitrationPolicy(int32_t policy) {
return static_cast<uint32_t>(policy);
bool UnitTestHelper<GfxFamily>::isPageTableManagerSupported(const HardwareInfo &hwInfo) {
return false;
}
template <typename GfxFamily>
@@ -30,37 +30,6 @@ bool UnitTestHelper<GfxFamily>::isPipeControlWArequired(const HardwareInfo &hwIn
return false;
}
template <typename GfxFamily>
bool UnitTestHelper<GfxFamily>::isAdditionalSynchronizationRequired() {
return false;
}
template <typename GfxFamily>
bool UnitTestHelper<GfxFamily>::isAdditionalMiSemaphoreWaitRequired(const RootDeviceEnvironment &rootDeviceEnvironment) {
return false;
}
template <typename GfxFamily>
inline uint64_t UnitTestHelper<GfxFamily>::getAtomicMemoryAddress(const typename GfxFamily::MI_ATOMIC &atomic) {
return atomic.getMemoryAddress() | ((static_cast<uint64_t>(atomic.getMemoryAddressHigh())) << 32);
}
template <typename GfxFamily>
inline bool UnitTestHelper<GfxFamily>::requiresTimestampPacketsInSystemMemory(HardwareInfo &hwInfo) {
return true;
}
template <typename GfxFamily>
void UnitTestHelper<GfxFamily>::setExtraMidThreadPreemptionFlag(HardwareInfo &hwInfo, bool value) {
hwInfo.featureTable.flags.ftrGpGpuMidThreadLevelPreempt = value;
}
template <typename GfxFamily>
const uint32_t UnitTestHelper<GfxFamily>::smallestTestableSimdSize = 8;
template <typename GfxFamily>
const AuxTranslationMode UnitTestHelper<GfxFamily>::requiredAuxTranslationMode = AuxTranslationMode::Builtin;
template <typename GfxFamily>
const bool UnitTestHelper<GfxFamily>::useFullRowForLocalIdsGeneration = false;
@@ -75,11 +44,6 @@ inline uint64_t UnitTestHelper<GfxFamily>::getPipeControlPostSyncAddress(const t
return (gpuAddressHigh << 32) | gpuAddress;
}
template <typename GfxFamily>
bool UnitTestHelper<GfxFamily>::timestampRegisterHighAddress() {
return false;
}
template <typename GfxFamily>
void UnitTestHelper<GfxFamily>::validateSbaMocs(uint32_t expectedMocs, CommandStreamReceiver &csr) {
using STATE_BASE_ADDRESS = typename GfxFamily::STATE_BASE_ADDRESS;

53
shared/test/common/helpers/unit_test_helper_bdw_and_later.inl
View File

@@ -5,16 +5,69 @@
*
*/
#include "shared/source/helpers/hw_info.h"
#include "shared/source/kernel/kernel_descriptor.h"
#include "shared/test/common/cmd_parse/gen_cmd_parse.h"
#include "shared/test/common/helpers/unit_test_helper.h"
namespace NEO {
template <typename GfxFamily>
uint64_t UnitTestHelper<GfxFamily>::getAtomicMemoryAddress(const typename GfxFamily::MI_ATOMIC &atomic) {
return atomic.getMemoryAddress() | ((static_cast<uint64_t>(atomic.getMemoryAddressHigh())) << 32);
}
template <typename GfxFamily>
const uint32_t UnitTestHelper<GfxFamily>::smallestTestableSimdSize = 8;
template <typename GfxFamily>
uint32_t UnitTestHelper<GfxFamily>::getAppropriateThreadArbitrationPolicy(int32_t policy) {
return static_cast<uint32_t>(policy);
}
template <typename GfxFamily>
void UnitTestHelper<GfxFamily>::setExtraMidThreadPreemptionFlag(HardwareInfo &hwInfo, bool value) {
hwInfo.featureTable.flags.ftrGpGpuMidThreadLevelPreempt = value;
}
template <typename GfxFamily>
bool UnitTestHelper<GfxFamily>::isAdditionalMiSemaphoreWaitRequired(const RootDeviceEnvironment &rootDeviceEnvironment) {
return false;
}
template <typename GfxFamily>
uint32_t UnitTestHelper<GfxFamily>::getDebugModeRegisterValue() {
return (1u << 5) | (1u << 21);
}
template <typename GfxFamily>
bool UnitTestHelper<GfxFamily>::isAdditionalSynchronizationRequired() {
return false;
}
template <typename GfxFamily>
bool UnitTestHelper<GfxFamily>::requiresTimestampPacketsInSystemMemory(HardwareInfo &hwInfo) {
return true;
}
template <typename GfxFamily>
const AuxTranslationMode UnitTestHelper<GfxFamily>::requiredAuxTranslationMode = AuxTranslationMode::Builtin;
template <typename GfxFamily>
uint32_t UnitTestHelper<GfxFamily>::getTdCtlRegisterValue() {
return (1u << 7) | (1u << 4);
}
template <typename GfxFamily>
bool UnitTestHelper<GfxFamily>::isL3ConfigProgrammable() {
return true;
};
template <typename GfxFamily>
bool UnitTestHelper<GfxFamily>::timestampRegisterHighAddress() {
return false;
}
template <typename GfxFamily>
bool UnitTestHelper<GfxFamily>::evaluateDshUsage(size_t sizeBeforeEnqueue, size_t sizeAfterEnqueue, const KernelDescriptor *kernelDescriptor, uint32_t rootDeviceIndex) {
if (sizeBeforeEnqueue != sizeAfterEnqueue) {

37
shared/test/common/helpers/unit_test_helper_xe_hpc_and_later.inl Normal file
View File

@@ -0,0 +1,37 @@
/*
* Copyright (C) 2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/test/common/helpers/unit_test_helper.h"
namespace NEO {
template <typename GfxFamily>
uint64_t UnitTestHelper<GfxFamily>::getAtomicMemoryAddress(const typename GfxFamily::MI_ATOMIC &atomic) {
return atomic.getMemoryAddress();
}
template <typename GfxFamily>
uint32_t UnitTestHelper<GfxFamily>::getAppropriateThreadArbitrationPolicy(int32_t policy) {
using STATE_COMPUTE_MODE = typename GfxFamily::STATE_COMPUTE_MODE;
switch (policy) {
case ThreadArbitrationPolicy::RoundRobin:
return STATE_COMPUTE_MODE::EU_THREAD_SCHEDULING_MODE_OVERRIDE::EU_THREAD_SCHEDULING_MODE_OVERRIDE_ROUND_ROBIN;
case ThreadArbitrationPolicy::AgeBased:
return STATE_COMPUTE_MODE::EU_THREAD_SCHEDULING_MODE_OVERRIDE::EU_THREAD_SCHEDULING_MODE_OVERRIDE_OLDEST_FIRST;
case ThreadArbitrationPolicy::RoundRobinAfterDependency:
return STATE_COMPUTE_MODE::EU_THREAD_SCHEDULING_MODE_OVERRIDE::EU_THREAD_SCHEDULING_MODE_OVERRIDE_STALL_BASED_ROUND_ROBIN;
default:
return STATE_COMPUTE_MODE::EU_THREAD_SCHEDULING_MODE_OVERRIDE::EU_THREAD_SCHEDULING_MODE_OVERRIDE_HW_DEFAULT;
}
}
template <typename GfxFamily>
bool UnitTestHelper<GfxFamily>::isAdditionalSynchronizationRequired() {
return true;
}
} // namespace NEO

51
shared/test/common/helpers/unit_test_helper_xe_hpg_and_xe_hpc.inl Normal file
View File

@@ -0,0 +1,51 @@
/*
* Copyright (C) 2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/test/common/helpers/unit_test_helper.h"
namespace NEO {
template <typename GfxFamily>
const AuxTranslationMode UnitTestHelper<GfxFamily>::requiredAuxTranslationMode = AuxTranslationMode::Blit;
template <typename GfxFamily>
GenCmdList::iterator UnitTestHelper<GfxFamily>::findMidThreadPreemptionAllocationCommand(GenCmdList::iterator begin, GenCmdList::iterator end) {
return end;
}
template <typename GfxFamily>
std::vector<GenCmdList::iterator> UnitTestHelper<GfxFamily>::findAllMidThreadPreemptionAllocationCommand(GenCmdList::iterator begin, GenCmdList::iterator end) {
std::vector<GenCmdList::iterator> emptyList;
return emptyList;
}
template <typename GfxFamily>
bool UnitTestHelper<GfxFamily>::timestampRegisterHighAddress() {
return false;
}
template <typename GfxFamily>
void UnitTestHelper<GfxFamily>::setExtraMidThreadPreemptionFlag(HardwareInfo &hwInfo, bool value) {
hwInfo.featureTable.flags.ftrGpGpuMidThreadLevelPreempt = value;
}
template <typename GfxFamily>
inline void UnitTestHelper<GfxFamily>::setPipeControlHdcPipelineFlush(typename GfxFamily::PIPE_CONTROL &pipeControl, bool hdcPipelineFlush) {
pipeControl.setHdcPipelineFlush(hdcPipelineFlush);
}
template <typename GfxFamily>
inline bool UnitTestHelper<GfxFamily>::getPipeControlHdcPipelineFlush(const typename GfxFamily::PIPE_CONTROL &pipeControl) {
return pipeControl.getHdcPipelineFlush();
}
template <typename GfxFamily>
bool UnitTestHelper<GfxFamily>::getSystolicFlagValueFromPipelineSelectCommand(const typename GfxFamily::PIPELINE_SELECT &pipelineSelectCmd) {
return pipelineSelectCmd.getSystolicModeEnable();
}
} // namespace NEO

43
shared/test/common/helpers/unit_test_helper_xehp_and_later.inl
View File

@@ -14,6 +14,24 @@
namespace NEO {
template <typename GfxFamily>
const uint32_t UnitTestHelper<GfxFamily>::smallestTestableSimdSize = 16;
template <typename GfxFamily>
uint32_t UnitTestHelper<GfxFamily>::getDebugModeRegisterOffset() {
return 0x20d8;
}
template <typename GfxFamily>
uint32_t UnitTestHelper<GfxFamily>::getDebugModeRegisterValue() {
return (1u << 5) | (1u << 21);
}
template <typename GfxFamily>
uint32_t UnitTestHelper<GfxFamily>::getTdCtlRegisterValue() {
return (1u << 7) | (1u << 4) | (1u << 2) | (1u << 0);
}
template <typename GfxFamily>
bool UnitTestHelper<GfxFamily>::isL3ConfigProgrammable() {
return false;
@@ -72,15 +90,6 @@ auto UnitTestHelper<GfxFamily>::getCoherencyTypeSupported(COHERENCY_TYPE coheren
return GfxFamily::RENDER_SURFACE_STATE::COHERENCY_TYPE_GPU_COHERENT;
}
template <typename GfxFamily>
inline bool UnitTestHelper<GfxFamily>::getPipeControlHdcPipelineFlush(const typename GfxFamily::PIPE_CONTROL &pipeControl) {
return pipeControl.getHdcPipelineFlush();
}
template <typename GfxFamily>
inline void UnitTestHelper<GfxFamily>::setPipeControlHdcPipelineFlush(typename GfxFamily::PIPE_CONTROL &pipeControl, bool hdcPipelineFlush) {
pipeControl.setHdcPipelineFlush(hdcPipelineFlush);
}
template <typename GfxFamily>
inline void UnitTestHelper<GfxFamily>::adjustKernelDescriptorForImplicitArgs(KernelDescriptor &kernelDescriptor) {
kernelDescriptor.kernelAttributes.flags.requiresImplicitArgs = true;
@@ -105,22 +114,6 @@ inline bool UnitTestHelper<GfxFamily>::getWorkloadPartitionForStoreRegisterMemCm
return storeRegisterMem.getWorkloadPartitionIdOffsetEnable();
}
template <typename GfxFamily>
GenCmdList::iterator UnitTestHelper<GfxFamily>::findMidThreadPreemptionAllocationCommand(GenCmdList::iterator begin, GenCmdList::iterator end) {
return end;
}
template <typename GfxFamily>
std::vector<GenCmdList::iterator> UnitTestHelper<GfxFamily>::findAllMidThreadPreemptionAllocationCommand(GenCmdList::iterator begin, GenCmdList::iterator end) {
std::vector<GenCmdList::iterator> emptyList;
return emptyList;
}
template <typename GfxFamily>
bool UnitTestHelper<GfxFamily>::getSystolicFlagValueFromPipelineSelectCommand(const typename GfxFamily::PIPELINE_SELECT &pipelineSelectCmd) {
return pipelineSelectCmd.getSystolicModeEnable();
}
template <typename GfxFamily>
size_t UnitTestHelper<GfxFamily>::getAdditionalDshSize(uint32_t iddCount) {
return 0;

12
shared/test/common/libult/CMakeLists.txt
View File

@@ -137,6 +137,18 @@ if(TESTS_XEHP_AND_LATER)
)
endif()
if(TESTS_XE_HPG_CORE OR TESTS_XE_HPC_CORE)
list(APPEND neo_libult_common_SRCS_LIB_ULT
${NEO_SHARED_TEST_DIRECTORY}/common/helpers/unit_test_helper_xe_hpg_and_xe_hpc.inl
)
endif()
if(TESTS_PVC_AND_LATER)
list(APPEND neo_libult_common_SRCS_LIB_ULT
${NEO_SHARED_TEST_DIRECTORY}/common/helpers/unit_test_helper_xe_hpc_and_later.inl
)
endif()
set_property(GLOBAL PROPERTY neo_libult_common_SRCS_LIB_ULT ${neo_libult_common_SRCS_LIB_ULT})
set_property(GLOBAL PROPERTY neo_libult_common_SRCS_ENABLE_TESTED_HW ${neo_libult_common_SRCS_ENABLE_TESTED_HW})

56
shared/test/common/xe_hpc_core/unit_test_helper_xe_hpc_core.cpp
View File

@@ -11,6 +11,8 @@
#include "shared/source/xe_hpc_core/hw_info.h"
#include "shared/test/common/helpers/unit_test_helper.h"
#include "shared/test/common/helpers/unit_test_helper.inl"
#include "shared/test/common/helpers/unit_test_helper_xe_hpc_and_later.inl"
#include "shared/test/common/helpers/unit_test_helper_xe_hpg_and_xe_hpc.inl"
#include "shared/test/common/helpers/unit_test_helper_xehp_and_later.inl"
using Family = NEO::XeHpcCoreFamily;
@@ -19,42 +21,11 @@ using Family = NEO::XeHpcCoreFamily;
namespace NEO {
template <>
const AuxTranslationMode UnitTestHelper<Family>::requiredAuxTranslationMode = AuxTranslationMode::Blit;
template <>
uint64_t UnitTestHelper<Family>::getAtomicMemoryAddress(const Family::MI_ATOMIC &atomic) {
return atomic.getMemoryAddress();
}
template <>
const uint32_t UnitTestHelper<Family>::smallestTestableSimdSize = 16;
template <>
uint32_t UnitTestHelper<Family>::getAppropriateThreadArbitrationPolicy(int32_t policy) {
using STATE_COMPUTE_MODE = typename Family::STATE_COMPUTE_MODE;
switch (policy) {
case ThreadArbitrationPolicy::RoundRobin:
return STATE_COMPUTE_MODE::EU_THREAD_SCHEDULING_MODE_OVERRIDE::EU_THREAD_SCHEDULING_MODE_OVERRIDE_ROUND_ROBIN;
case ThreadArbitrationPolicy::AgeBased:
return STATE_COMPUTE_MODE::EU_THREAD_SCHEDULING_MODE_OVERRIDE::EU_THREAD_SCHEDULING_MODE_OVERRIDE_OLDEST_FIRST;
case ThreadArbitrationPolicy::RoundRobinAfterDependency:
return STATE_COMPUTE_MODE::EU_THREAD_SCHEDULING_MODE_OVERRIDE::EU_THREAD_SCHEDULING_MODE_OVERRIDE_STALL_BASED_ROUND_ROBIN;
default:
return STATE_COMPUTE_MODE::EU_THREAD_SCHEDULING_MODE_OVERRIDE::EU_THREAD_SCHEDULING_MODE_OVERRIDE_HW_DEFAULT;
}
}
template <>
bool UnitTestHelper<Family>::requiresTimestampPacketsInSystemMemory(HardwareInfo &hwInfo) {
return false;
}
template <>
bool UnitTestHelper<Family>::isAdditionalSynchronizationRequired() {
return true;
}
template <>
bool UnitTestHelper<Family>::isAdditionalMiSemaphoreWaitRequired(const RootDeviceEnvironment &rootDeviceEnvironment) {
const auto &productHelper = rootDeviceEnvironment.getHelper<ProductHelper>();
@@ -66,29 +37,6 @@ bool UnitTestHelper<Family>::isAdditionalMiSemaphoreWaitRequired(const RootDevic
return !programGlobalFenceAsMiMemFenceCommandInCommandStream;
}
template <>
const bool UnitTestHelper<Family>::additionalMiFlushDwRequired = false;
template <>
uint32_t UnitTestHelper<Family>::getDebugModeRegisterOffset() {
return 0x20d8;
}
template <>
uint32_t UnitTestHelper<Family>::getDebugModeRegisterValue() {
return (1u << 5) | (1u << 21);
}
template <>
uint32_t UnitTestHelper<Family>::getTdCtlRegisterOffset() {
return 0xe400;
}
template <>
uint32_t UnitTestHelper<Family>::getTdCtlRegisterValue() {
return (1u << 7) | (1u << 4) | (1u << 2) | (1u << 0);
}
template <>
bool UnitTestHelper<Family>::getComputeDispatchAllWalkerFromFrontEndCommand(const typename Family::VFE_STATE_TYPE &feCmd) {
return feCmd.getComputeDispatchAllWalkerEnable();

49
shared/test/common/xe_hpg_core/unit_test_helper_xe_hpg_core.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2022 Intel Corporation
* Copyright (C) 2021-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -9,40 +9,45 @@
#include "shared/source/xe_hpg_core/hw_info.h"
#include "shared/test/common/helpers/unit_test_helper.h"
#include "shared/test/common/helpers/unit_test_helper.inl"
#include "shared/test/common/helpers/unit_test_helper_xe_hpg_and_xe_hpc.inl"
#include "shared/test/common/helpers/unit_test_helper_xehp_and_later.inl"
using Family = NEO::XeHpgCoreFamily;
namespace NEO {
template <>
const AuxTranslationMode UnitTestHelper<Family>::requiredAuxTranslationMode = AuxTranslationMode::Blit;
uint64_t UnitTestHelper<Family>::getAtomicMemoryAddress(const typename Family::MI_ATOMIC &atomic) {
return atomic.getMemoryAddress() | ((static_cast<uint64_t>(atomic.getMemoryAddressHigh())) << 32);
}
template <>
uint32_t UnitTestHelper<Family>::getAppropriateThreadArbitrationPolicy(int32_t policy) {
return static_cast<uint32_t>(policy);
}
template <>
const bool UnitTestHelper<Family>::additionalMiFlushDwRequired = true;
template <>
uint32_t UnitTestHelper<Family>::getDebugModeRegisterOffset() {
return 0x20d8;
}
template <>
uint32_t UnitTestHelper<Family>::getDebugModeRegisterValue() {
return (1u << 5) | (1u << 21);
}
template <>
uint32_t UnitTestHelper<Family>::getTdCtlRegisterOffset() {
return 0xe400;
}
template <>
uint32_t UnitTestHelper<Family>::getTdCtlRegisterValue() {
return (1u << 7) | (1u << 4) | (1u << 2) | (1u << 0);
}
template <>
bool UnitTestHelper<Family>::getDisableFusionStateFromFrontEndCommand(const typename Family::VFE_STATE_TYPE &feCmd) {
return feCmd.getFusedEuDispatch();
}
template <>
bool UnitTestHelper<Family>::isAdditionalMiSemaphoreWaitRequired(const RootDeviceEnvironment &rootDeviceEnvironment) {
return false;
}
template <>
bool UnitTestHelper<Family>::isAdditionalSynchronizationRequired() {
return false;
}
template <>
bool UnitTestHelper<Family>::requiresTimestampPacketsInSystemMemory(HardwareInfo &hwInfo) {
return true;
}
template struct UnitTestHelper<Family>;
} // namespace NEO