diff --git a/level_zero/core/source/gen11/CMakeLists.txt b/level_zero/core/source/gen11/CMakeLists.txt
index e64511fc78..66412510b1 100644
--- a/level_zero/core/source/gen11/CMakeLists.txt
+++ b/level_zero/core/source/gen11/CMakeLists.txt
@@ -1,5 +1,5 @@
 #
-# Copyright (C) 2020-2021 Intel Corporation
+# Copyright (C) 2020-2022 Intel Corporation
 #
 # SPDX-License-Identifier: MIT
 #
@@ -7,6 +7,8 @@
 if(SUPPORT_GEN11)
   set(HW_SOURCES_GEN11
       ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
+      ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_gen11.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_gen11.h
       ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_gen11.inl
       ${CMAKE_CURRENT_SOURCE_DIR}/debugger_gen11.cpp
       ${CMAKE_CURRENT_SOURCE_DIR}/enable_family_full_l0_gen11.cpp
diff --git a/level_zero/core/source/gen11/cmdlist_gen11.cpp b/level_zero/core/source/gen11/cmdlist_gen11.cpp
new file mode 100644
index 0000000000..1c7a7ea1ca
--- /dev/null
+++ b/level_zero/core/source/gen11/cmdlist_gen11.cpp
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2022 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "level_zero/core/source/gen11/cmdlist_gen11.inl"
+
+#include "level_zero/core/source/cmdlist/cmdlist_hw.h"
+#include "level_zero/core/source/cmdlist/cmdlist_hw.inl"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_base.inl"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.h"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.inl"
+
+#include "cmdlist_extended.inl"
+
+namespace L0 {
+
+template struct CommandListCoreFamily<IGFX_GEN11_CORE>;
+template struct CommandListCoreFamilyImmediate<IGFX_GEN11_CORE>;
+
+} // namespace L0
diff --git a/level_zero/core/source/gen11/cmdlist_gen11.h b/level_zero/core/source/gen11/cmdlist_gen11.h
new file mode 100644
index 0000000000..76cb1bedcf
--- /dev/null
+++ b/level_zero/core/source/gen11/cmdlist_gen11.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2022 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#pragma once
+#include "level_zero/core/source/cmdlist/cmdlist_hw.h"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.h"
+
+namespace L0 {
+template <PRODUCT_FAMILY productFamily>
+struct CommandListProductFamily : public CommandListCoreFamily<IGFX_GEN11_CORE> {
+    using CommandListCoreFamily::CommandListCoreFamily;
+};
+
+template <PRODUCT_FAMILY gfxProductFamily>
+struct CommandListImmediateProductFamily : public CommandListCoreFamilyImmediate<IGFX_GEN11_CORE> {
+    using CommandListCoreFamilyImmediate::CommandListCoreFamilyImmediate;
+};
+} // namespace L0
diff --git a/level_zero/core/source/gen11/cmdlist_gen11.inl b/level_zero/core/source/gen11/cmdlist_gen11.inl
index 9eebf79fd2..7b53b95caf 100644
--- a/level_zero/core/source/gen11/cmdlist_gen11.inl
+++ b/level_zero/core/source/gen11/cmdlist_gen11.inl
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2020-2021 Intel Corporation
+ * Copyright (C) 2020-2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -7,6 +7,8 @@
 
 #include "shared/source/helpers/pipe_control_args.h"
 
+#include "level_zero/core/source/cmdlist/cmdlist_hw.h"
+
 namespace L0 {
 
 template <GFXCORE_FAMILY gfxCoreFamily>
diff --git a/level_zero/core/source/gen11/icllp/cmdlist_icllp.cpp b/level_zero/core/source/gen11/icllp/cmdlist_icllp.cpp
index 00c9d80c08..5198076e9c 100644
--- a/level_zero/core/source/gen11/icllp/cmdlist_icllp.cpp
+++ b/level_zero/core/source/gen11/icllp/cmdlist_icllp.cpp
@@ -1,39 +1,16 @@
 /*
- * Copyright (C) 2020-2021 Intel Corporation
+ * Copyright (C) 2020-2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
  */
 
-#include "shared/source/gen11/hw_cmds.h"
-#include "shared/source/gen11/hw_info.h"
-
-#include "level_zero/core/source/cmdlist/cmdlist_hw.inl"
-#include "level_zero/core/source/cmdlist/cmdlist_hw_base.inl"
-#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.inl"
-#include "level_zero/core/source/gen11/cmdlist_gen11.inl"
-
-#include "cmdlist_extended.inl"
-#include "igfxfmid.h"
+#include "level_zero/core/source/gen11/cmdlist_gen11.h"
 
 namespace L0 {
-
-template struct CommandListCoreFamily<IGFX_GEN11_CORE>;
-template struct CommandListCoreFamilyImmediate<IGFX_GEN11_CORE>;
-
-template <>
-struct CommandListProductFamily<IGFX_ICELAKE_LP> : public CommandListCoreFamily<IGFX_GEN11_CORE> {
-    using CommandListCoreFamily::CommandListCoreFamily;
-};
-
 static CommandListPopulateFactory<IGFX_ICELAKE_LP, CommandListProductFamily<IGFX_ICELAKE_LP>>
     populateICLLP;
 
-template <>
-struct CommandListImmediateProductFamily<IGFX_ICELAKE_LP> : public CommandListCoreFamilyImmediate<IGFX_GEN11_CORE> {
-    using CommandListCoreFamilyImmediate::CommandListCoreFamilyImmediate;
-};
-
 static CommandListImmediatePopulateFactory<IGFX_ICELAKE_LP, CommandListImmediateProductFamily<IGFX_ICELAKE_LP>>
     populateICLLPImmediate;
 
diff --git a/level_zero/core/source/gen9/CMakeLists.txt b/level_zero/core/source/gen9/CMakeLists.txt
index 3b0ef380f0..86cf686024 100644
--- a/level_zero/core/source/gen9/CMakeLists.txt
+++ b/level_zero/core/source/gen9/CMakeLists.txt
@@ -1,5 +1,5 @@
 #
-# Copyright (C) 2020-2021 Intel Corporation
+# Copyright (C) 2020-2022 Intel Corporation
 #
 # SPDX-License-Identifier: MIT
 #
@@ -7,6 +7,8 @@
 if(SUPPORT_GEN9)
   set(HW_SOURCES_GEN9
       ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
+      ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_gen9.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_gen9.h
       ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_gen9.inl
       ${CMAKE_CURRENT_SOURCE_DIR}/debugger_gen9.cpp
       ${CMAKE_CURRENT_SOURCE_DIR}/enable_family_full_l0_gen9.cpp
diff --git a/level_zero/core/source/gen9/cfl/cmdlist_cfl.cpp b/level_zero/core/source/gen9/cfl/cmdlist_cfl.cpp
index aeca2add3c..8ff935f44e 100644
--- a/level_zero/core/source/gen9/cfl/cmdlist_cfl.cpp
+++ b/level_zero/core/source/gen9/cfl/cmdlist_cfl.cpp
@@ -1,21 +1,11 @@
 /*
- * Copyright (C) 2020-2021 Intel Corporation
+ * Copyright (C) 2020-2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
  */
 
-#include "shared/source/gen9/hw_cmds.h"
-#include "shared/source/gen9/hw_info.h"
-
-#include "level_zero/core/source/cmdlist/cmdlist_hw.inl"
-#include "level_zero/core/source/cmdlist/cmdlist_hw_base.inl"
-#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.inl"
 #include "level_zero/core/source/gen9/cmdlist_gen9.h"
-#include "level_zero/core/source/gen9/cmdlist_gen9.inl"
-
-#include "cmdlist_extended.inl"
-#include "igfxfmid.h"
 
 namespace L0 {
 
diff --git a/level_zero/core/source/gen9/cmdlist_gen9.cpp b/level_zero/core/source/gen9/cmdlist_gen9.cpp
new file mode 100644
index 0000000000..6dc90db941
--- /dev/null
+++ b/level_zero/core/source/gen9/cmdlist_gen9.cpp
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2022 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "level_zero/core/source/gen9/cmdlist_gen9.inl"
+
+#include "level_zero/core/source/cmdlist/cmdlist_hw.h"
+#include "level_zero/core/source/cmdlist/cmdlist_hw.inl"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_base.inl"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.h"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.inl"
+
+#include "cmdlist_extended.inl"
+
+namespace L0 {
+template struct CommandListCoreFamily<IGFX_GEN9_CORE>;
+template struct CommandListCoreFamilyImmediate<IGFX_GEN9_CORE>;
+} // namespace L0
diff --git a/level_zero/core/source/gen9/cmdlist_gen9.inl b/level_zero/core/source/gen9/cmdlist_gen9.inl
index e5064d14c5..4ad1c07b48 100644
--- a/level_zero/core/source/gen9/cmdlist_gen9.inl
+++ b/level_zero/core/source/gen9/cmdlist_gen9.inl
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2020-2021 Intel Corporation
+ * Copyright (C) 2020-2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -14,10 +14,6 @@
 #include "level_zero/core/source/cmdlist/cmdlist_hw.h"
 
 namespace L0 {
-
-template struct CommandListCoreFamily<IGFX_GEN9_CORE>;
-template struct CommandListCoreFamilyImmediate<IGFX_GEN9_CORE>;
-
 template <GFXCORE_FAMILY gfxCoreFamily>
 void CommandListCoreFamily<gfxCoreFamily>::applyMemoryRangesBarrier(uint32_t numRanges,
                                                                     const size_t *pRangeSizes,
diff --git a/level_zero/core/source/gen9/kbl/cmdlist_kbl.cpp b/level_zero/core/source/gen9/kbl/cmdlist_kbl.cpp
index 3dc1443aa0..ca176febcf 100644
--- a/level_zero/core/source/gen9/kbl/cmdlist_kbl.cpp
+++ b/level_zero/core/source/gen9/kbl/cmdlist_kbl.cpp
@@ -1,21 +1,11 @@
 /*
- * Copyright (C) 2020-2021 Intel Corporation
+ * Copyright (C) 2020-2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
  */
 
-#include "shared/source/gen9/hw_cmds.h"
-#include "shared/source/gen9/hw_info.h"
-
-#include "level_zero/core/source/cmdlist/cmdlist_hw.inl"
-#include "level_zero/core/source/cmdlist/cmdlist_hw_base.inl"
-#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.inl"
 #include "level_zero/core/source/gen9/cmdlist_gen9.h"
-#include "level_zero/core/source/gen9/cmdlist_gen9.inl"
-
-#include "cmdlist_extended.inl"
-#include "igfxfmid.h"
 
 namespace L0 {
 static CommandListPopulateFactory<IGFX_KABYLAKE, CommandListProductFamily<IGFX_KABYLAKE>>
diff --git a/level_zero/core/source/gen9/skl/cmdlist_skl.cpp b/level_zero/core/source/gen9/skl/cmdlist_skl.cpp
index 660478ea73..98dee04a95 100644
--- a/level_zero/core/source/gen9/skl/cmdlist_skl.cpp
+++ b/level_zero/core/source/gen9/skl/cmdlist_skl.cpp
@@ -1,25 +1,16 @@
 /*
- * Copyright (C) 2020-2021 Intel Corporation
+ * Copyright (C) 2020-2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
  */
 
-#include "shared/source/gen9/hw_cmds.h"
-#include "shared/source/gen9/hw_info.h"
-
-#include "level_zero/core/source/cmdlist/cmdlist_hw.inl"
-#include "level_zero/core/source/cmdlist/cmdlist_hw_base.inl"
-#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.inl"
 #include "level_zero/core/source/gen9/cmdlist_gen9.h"
-#include "level_zero/core/source/gen9/cmdlist_gen9.inl"
-
-#include "cmdlist_extended.inl"
-#include "igfxfmid.h"
 
 namespace L0 {
 
-static CommandListPopulateFactory<IGFX_SKYLAKE, CommandListProductFamily<IGFX_SKYLAKE>> populateSKL;
+static CommandListPopulateFactory<IGFX_SKYLAKE, CommandListProductFamily<IGFX_SKYLAKE>>
+    populateSKL;
 
 static CommandListImmediatePopulateFactory<IGFX_SKYLAKE, CommandListImmediateProductFamily<IGFX_SKYLAKE>>
     populateSKLImmediate;
diff --git a/level_zero/core/source/xe_hp_core/CMakeLists.txt b/level_zero/core/source/xe_hp_core/CMakeLists.txt
index 372f47eb4e..dcbc395536 100644
--- a/level_zero/core/source/xe_hp_core/CMakeLists.txt
+++ b/level_zero/core/source/xe_hp_core/CMakeLists.txt
@@ -1,5 +1,5 @@
 #
-# Copyright (C) 2021 Intel Corporation
+# Copyright (C) 2021-2022 Intel Corporation
 #
 # SPDX-License-Identifier: MIT
 #
@@ -7,6 +7,8 @@
 if(SUPPORT_XE_HP_CORE)
   set(HW_SOURCES_XE_HP_CORE
       ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
+      ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_xe_hp_core.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_xe_hp_core.h
       ${CMAKE_CURRENT_SOURCE_DIR}/debugger_xe_hp_core.cpp
       ${CMAKE_CURRENT_SOURCE_DIR}/image_xe_hp_core.inl
       ${CMAKE_CURRENT_SOURCE_DIR}/sampler_xe_hp_core.inl
diff --git a/level_zero/core/source/xe_hp_core/cmdlist_xe_hp_core.cpp b/level_zero/core/source/xe_hp_core/cmdlist_xe_hp_core.cpp
new file mode 100644
index 0000000000..70edf54544
--- /dev/null
+++ b/level_zero/core/source/xe_hp_core/cmdlist_xe_hp_core.cpp
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2022 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "level_zero/core/source/cmdlist/cmdlist_hw.h"
+#include "level_zero/core/source/cmdlist/cmdlist_hw.inl"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.h"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.inl"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_xehp_and_later.inl"
+
+#include "cmdlist_extended.inl"
+
+namespace L0 {
+template <>
+void CommandListCoreFamily<IGFX_XE_HP_CORE>::clearComputeModePropertiesIfNeeded(bool requiresCoherency, uint32_t numGrfRequired, uint32_t threadArbitrationPolicy) {
+    finalStreamState.stateComputeMode = {};
+    finalStreamState.stateComputeMode.setProperties(requiresCoherency, numGrfRequired, threadArbitrationPolicy);
+}
+
+template struct CommandListCoreFamily<IGFX_XE_HP_CORE>;
+template struct CommandListCoreFamilyImmediate<IGFX_XE_HP_CORE>;
+
+} // namespace L0
diff --git a/level_zero/core/source/xe_hp_core/cmdlist_xe_hp_core.h b/level_zero/core/source/xe_hp_core/cmdlist_xe_hp_core.h
new file mode 100644
index 0000000000..077321a8ed
--- /dev/null
+++ b/level_zero/core/source/xe_hp_core/cmdlist_xe_hp_core.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2022 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#pragma once
+#include "level_zero/core/source/cmdlist/cmdlist_hw.h"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.h"
+
+namespace L0 {
+template <PRODUCT_FAMILY productFamily>
+struct CommandListProductFamily : public CommandListCoreFamily<IGFX_XE_HP_CORE> {
+    using CommandListCoreFamily::CommandListCoreFamily;
+};
+
+template <PRODUCT_FAMILY gfxProductFamily>
+struct CommandListImmediateProductFamily : public CommandListCoreFamilyImmediate<IGFX_XE_HP_CORE> {
+    using CommandListCoreFamilyImmediate::CommandListCoreFamilyImmediate;
+};
+} // namespace L0
diff --git a/level_zero/core/source/xe_hp_core/xehp/cmdlist_xehp.cpp b/level_zero/core/source/xe_hp_core/xehp/cmdlist_xehp.cpp
index 0717c2eedf..167dfc6de8 100644
--- a/level_zero/core/source/xe_hp_core/xehp/cmdlist_xehp.cpp
+++ b/level_zero/core/source/xe_hp_core/xehp/cmdlist_xehp.cpp
@@ -1,39 +1,16 @@
 /*
- * Copyright (C) 2021 Intel Corporation
+ * Copyright (C) 2021-2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
  */
 
-#include "level_zero/core/source/cmdlist/cmdlist_hw.inl"
-#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.inl"
-#include "level_zero/core/source/cmdlist/cmdlist_hw_xehp_and_later.inl"
-
-#include "cmdlist_extended.inl"
+#include "level_zero/core/source/xe_hp_core/cmdlist_xe_hp_core.h"
 
 namespace L0 {
-
-template <>
-void CommandListCoreFamily<IGFX_XE_HP_CORE>::clearComputeModePropertiesIfNeeded(bool requiresCoherency, uint32_t numGrfRequired, uint32_t threadArbitrationPolicy) {
-    finalStreamState.stateComputeMode = {};
-    finalStreamState.stateComputeMode.setProperties(requiresCoherency, numGrfRequired, threadArbitrationPolicy);
-}
-
-template struct CommandListCoreFamily<IGFX_XE_HP_CORE>;
-
-template <>
-struct CommandListProductFamily<IGFX_XE_HP_SDV> : public CommandListCoreFamily<IGFX_XE_HP_CORE> {
-    using CommandListCoreFamily::CommandListCoreFamily;
-};
-
 static CommandListPopulateFactory<IGFX_XE_HP_SDV, CommandListProductFamily<IGFX_XE_HP_SDV>>
     populateXEHP;
 
-template <>
-struct CommandListImmediateProductFamily<IGFX_XE_HP_SDV> : public CommandListCoreFamilyImmediate<IGFX_XE_HP_CORE> {
-    using CommandListCoreFamilyImmediate::CommandListCoreFamilyImmediate;
-};
-
 static CommandListImmediatePopulateFactory<IGFX_XE_HP_SDV, CommandListImmediateProductFamily<IGFX_XE_HP_SDV>>
     populateXEHPImmediate;
 
diff --git a/level_zero/core/source/xe_hpc_core/CMakeLists.txt b/level_zero/core/source/xe_hpc_core/CMakeLists.txt
index cfe7cd5c9e..b1aab4868c 100644
--- a/level_zero/core/source/xe_hpc_core/CMakeLists.txt
+++ b/level_zero/core/source/xe_hpc_core/CMakeLists.txt
@@ -1,5 +1,5 @@
 #
-# Copyright (C) 2021 Intel Corporation
+# Copyright (C) 2021-2022 Intel Corporation
 #
 # SPDX-License-Identifier: MIT
 #
@@ -7,7 +7,8 @@
 if(SUPPORT_XE_HPC_CORE)
   set(HW_SOURCES_XE_HPC_CORE
       ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
-      ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_xe_hpc_core.inl
+      ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_xe_hpc_core.cpp
+      ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_xe_hpc_core.h
       ${CMAKE_CURRENT_SOURCE_DIR}/debugger_xe_hpc_core.cpp
       ${CMAKE_CURRENT_SOURCE_DIR}/enable_family_full_l0_xe_hpc_core.cpp
       ${CMAKE_CURRENT_SOURCE_DIR}/l0_hw_helper_xe_hpc_core.cpp
diff --git a/level_zero/core/source/xe_hpc_core/cmdlist_xe_hpc_core.inl b/level_zero/core/source/xe_hpc_core/cmdlist_xe_hpc_core.cpp
similarity index 57%
rename from level_zero/core/source/xe_hpc_core/cmdlist_xe_hpc_core.inl
rename to level_zero/core/source/xe_hpc_core/cmdlist_xe_hpc_core.cpp
index 39dd585c50..695c5479e2 100644
--- a/level_zero/core/source/xe_hpc_core/cmdlist_xe_hpc_core.inl
+++ b/level_zero/core/source/xe_hpc_core/cmdlist_xe_hpc_core.cpp
@@ -1,14 +1,19 @@
 /*
- * Copyright (C) 2021 Intel Corporation
+ * Copyright (C) 2021-2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
  */
 
 #include "level_zero/core/source/cmdlist/cmdlist_hw.h"
+#include "level_zero/core/source/cmdlist/cmdlist_hw.inl"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.h"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.inl"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_xehp_and_later.inl"
+
+#include "cmdlist_extended.inl"
 
 namespace L0 {
-
 template <>
 NEO::PipeControlArgs CommandListCoreFamily<IGFX_XE_HPC_CORE>::createBarrierFlags() {
     NEO::PipeControlArgs args;
@@ -46,4 +51,21 @@ ze_result_t CommandListCoreFamily<IGFX_XE_HPC_CORE>::appendMemoryPrefetch(const
 
     return ZE_RESULT_SUCCESS;
 }
+
+template <>
+void CommandListCoreFamily<IGFX_XE_HPC_CORE>::applyMemoryRangesBarrier(uint32_t numRanges,
+                                                                       const size_t *pRangeSizes,
+                                                                       const void **pRanges) {
+
+    increaseCommandStreamSpace(NEO::MemorySynchronizationCommands<GfxFamily>::getSizeForSinglePipeControl());
+
+    NEO::PipeControlArgs args;
+    args.hdcPipelineFlush = true;
+    args.unTypedDataPortCacheFlush = true;
+    NEO::MemorySynchronizationCommands<GfxFamily>::addPipeControl(*commandContainer.getCommandStream(), args);
+}
+
+template struct CommandListCoreFamily<IGFX_XE_HPC_CORE>;
+template struct CommandListCoreFamilyImmediate<IGFX_XE_HPC_CORE>;
+
 } // namespace L0
diff --git a/level_zero/core/source/xe_hpc_core/cmdlist_xe_hpc_core.h b/level_zero/core/source/xe_hpc_core/cmdlist_xe_hpc_core.h
new file mode 100644
index 0000000000..3f72e9696c
--- /dev/null
+++ b/level_zero/core/source/xe_hpc_core/cmdlist_xe_hpc_core.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2022 Intel Corporation
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#pragma once
+#include "level_zero/core/source/cmdlist/cmdlist_hw.h"
+#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.h"
+
+namespace L0 {
+template <PRODUCT_FAMILY productFamily>
+struct CommandListProductFamily : public CommandListCoreFamily<IGFX_XE_HPC_CORE> {
+    using CommandListCoreFamily::CommandListCoreFamily;
+};
+
+template <PRODUCT_FAMILY gfxProductFamily>
+struct CommandListImmediateProductFamily : public CommandListCoreFamilyImmediate<IGFX_XE_HPC_CORE> {
+    using CommandListCoreFamilyImmediate::CommandListCoreFamilyImmediate;
+};
+} // namespace L0
diff --git a/level_zero/core/source/xe_hpc_core/pvc/cmdlist_pvc.cpp b/level_zero/core/source/xe_hpc_core/pvc/cmdlist_pvc.cpp
index f48179922e..adfb2ae0f7 100644
--- a/level_zero/core/source/xe_hpc_core/pvc/cmdlist_pvc.cpp
+++ b/level_zero/core/source/xe_hpc_core/pvc/cmdlist_pvc.cpp
@@ -1,46 +1,16 @@
 /*
- * Copyright (C) 2021 Intel Corporation
+ * Copyright (C) 2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
  */
 
-#include "level_zero/core/source/cmdlist/cmdlist_hw.inl"
-#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.inl"
-#include "level_zero/core/source/cmdlist/cmdlist_hw_xehp_and_later.inl"
-#include "level_zero/core/source/xe_hpc_core/cmdlist_xe_hpc_core.inl"
-
-#include "cmdlist_extended.inl"
+#include "level_zero/core/source/xe_hpc_core/cmdlist_xe_hpc_core.h"
 
 namespace L0 {
-template <>
-void CommandListCoreFamily<IGFX_XE_HPC_CORE>::applyMemoryRangesBarrier(uint32_t numRanges,
-                                                                       const size_t *pRangeSizes,
-                                                                       const void **pRanges) {
-
-    increaseCommandStreamSpace(NEO::MemorySynchronizationCommands<GfxFamily>::getSizeForSinglePipeControl());
-
-    NEO::PipeControlArgs args;
-    args.hdcPipelineFlush = true;
-    args.unTypedDataPortCacheFlush = true;
-    NEO::MemorySynchronizationCommands<GfxFamily>::addPipeControl(*commandContainer.getCommandStream(), args);
-}
-
-template struct CommandListCoreFamily<IGFX_XE_HPC_CORE>;
-
-template <>
-struct CommandListProductFamily<IGFX_PVC> : public CommandListCoreFamily<IGFX_XE_HPC_CORE> {
-    using CommandListCoreFamily::CommandListCoreFamily;
-};
-
 static CommandListPopulateFactory<IGFX_PVC, CommandListProductFamily<IGFX_PVC>>
     populatePVC;
 
-template <>
-struct CommandListImmediateProductFamily<IGFX_PVC> : public CommandListCoreFamilyImmediate<IGFX_XE_HPC_CORE> {
-    using CommandListCoreFamilyImmediate::CommandListCoreFamilyImmediate;
-};
-
 static CommandListImmediatePopulateFactory<IGFX_PVC, CommandListImmediateProductFamily<IGFX_PVC>>
     populatePVCImmediate;
 } // namespace L0