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Extract functions to device_queue_hw_base.inl
Change-Id: I91216453effadf7290b6364bfd442704add97566 Related-To: NEO-3016 Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
This commit is contained in:
Maciej Dziuban
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sys_ocldev
sys_ocldev
parent
2e6e791a1c
commit
e67879ffca
239
runtime/device_queue/device_queue_hw_base.inl
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239
runtime/device_queue/device_queue_hw_base.inl
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/*
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* Copyright (C) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include "runtime/command_queue/gpgpu_walker.h"
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#include "runtime/device_queue/device_queue_hw.h"
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#include "runtime/helpers/hw_helper.h"
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#include "runtime/helpers/kernel_commands.h"
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#include "runtime/helpers/preamble.h"
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#include "runtime/helpers/string.h"
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#include "runtime/memory_manager/memory_manager.h"
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#include "runtime/utilities/tag_allocator.h"
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namespace NEO {
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template <typename GfxFamily>
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void DeviceQueueHw<GfxFamily>::allocateSlbBuffer() {
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auto slbSize = getMinimumSlbSize() + getWaCommandsSize();
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slbSize *= 128; //num of enqueues
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slbSize += sizeof(MI_BATCH_BUFFER_START);
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slbSize = alignUp(slbSize, MemoryConstants::pageSize);
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slbSize += DeviceQueueHw<GfxFamily>::getExecutionModelCleanupSectionSize();
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slbSize += (4 * MemoryConstants::pageSize); // +4 pages spec restriction
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slbSize = alignUp(slbSize, MemoryConstants::pageSize);
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slbBuffer = device->getMemoryManager()->allocateGraphicsMemoryWithProperties({slbSize, GraphicsAllocation::AllocationType::DEVICE_QUEUE_BUFFER});
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}
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template <typename GfxFamily>
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void DeviceQueueHw<GfxFamily>::resetDeviceQueue() {
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auto &caps = device->getDeviceInfo();
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auto igilEventPool = reinterpret_cast<IGIL_EventPool *>(eventPoolBuffer->getUnderlyingBuffer());
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memset(eventPoolBuffer->getUnderlyingBuffer(), 0x0, eventPoolBuffer->getUnderlyingBufferSize());
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igilEventPool->m_size = caps.maxOnDeviceEvents;
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auto igilCmdQueue = reinterpret_cast<IGIL_CommandQueue *>(queueBuffer->getUnderlyingBuffer());
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igilQueue = igilCmdQueue;
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igilCmdQueue->m_controls.m_StackSize =
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static_cast<uint32_t>((stackBuffer->getUnderlyingBufferSize() / sizeof(cl_uint)) - 1);
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igilCmdQueue->m_controls.m_StackTop =
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static_cast<uint32_t>((stackBuffer->getUnderlyingBufferSize() / sizeof(cl_uint)) - 1);
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igilCmdQueue->m_controls.m_PreviousHead = IGIL_DEVICE_QUEUE_HEAD_INIT;
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igilCmdQueue->m_controls.m_IDTAfterFirstPhase = 1;
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igilCmdQueue->m_controls.m_CurrentIDToffset = 1;
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igilCmdQueue->m_controls.m_PreviousStorageTop = static_cast<uint32_t>(queueStorageBuffer->getUnderlyingBufferSize());
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igilCmdQueue->m_controls.m_PreviousStackTop =
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static_cast<uint32_t>((stackBuffer->getUnderlyingBufferSize() / sizeof(cl_uint)) - 1);
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igilCmdQueue->m_controls.m_DebugNextBlockID = 0xFFFFFFFF;
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igilCmdQueue->m_controls.m_QstorageSize = static_cast<uint32_t>(queueStorageBuffer->getUnderlyingBufferSize());
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igilCmdQueue->m_controls.m_QstorageTop = static_cast<uint32_t>(queueStorageBuffer->getUnderlyingBufferSize());
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igilCmdQueue->m_controls.m_IsProfilingEnabled = static_cast<uint32_t>(isProfilingEnabled());
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igilCmdQueue->m_controls.m_IsSimulation = static_cast<uint32_t>(device->isSimulation());
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igilCmdQueue->m_controls.m_LastScheduleEventNumber = 0;
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igilCmdQueue->m_controls.m_PreviousNumberOfQueues = 0;
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igilCmdQueue->m_controls.m_EnqueueMarkerScheduled = 0;
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igilCmdQueue->m_controls.m_SecondLevelBatchOffset = 0;
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igilCmdQueue->m_controls.m_TotalNumberOfQueues = 0;
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igilCmdQueue->m_controls.m_EventTimestampAddress = 0;
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igilCmdQueue->m_controls.m_ErrorCode = 0;
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igilCmdQueue->m_controls.m_CurrentScheduleEventNumber = 0;
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igilCmdQueue->m_controls.m_DummyAtomicOperationPlaceholder = 0x00;
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igilCmdQueue->m_controls.m_DebugNextBlockGWS = 0;
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// set first stack element in surface at value "1", it protects Scheduler in corner case when StackTop is empty after Child execution
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auto stack = static_cast<uint32_t *>(stackBuffer->getUnderlyingBuffer());
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stack += ((stackBuffer->getUnderlyingBufferSize() / sizeof(cl_uint)) - 1);
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*stack = 1;
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igilCmdQueue->m_head = IGIL_DEVICE_QUEUE_HEAD_INIT;
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igilCmdQueue->m_size = static_cast<uint32_t>(queueBuffer->getUnderlyingBufferSize() - sizeof(IGIL_CommandQueue));
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igilCmdQueue->m_magic = IGIL_MAGIC_NUMBER;
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igilCmdQueue->m_controls.m_SchedulerEarlyReturn = DebugManager.flags.SchedulerSimulationReturnInstance.get();
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igilCmdQueue->m_controls.m_SchedulerEarlyReturnCounter = 0;
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buildSlbDummyCommands();
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igilCmdQueue->m_controls.m_SLBENDoffsetInBytes = -1;
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igilCmdQueue->m_controls.m_CriticalSection = ExecutionModelCriticalSection::Free;
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resetDSH();
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}
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template <typename GfxFamily>
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void DeviceQueueHw<GfxFamily>::initPipeControl(PIPE_CONTROL *pc) {
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*pc = GfxFamily::cmdInitPipeControl;
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pc->setStateCacheInvalidationEnable(0x1);
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pc->setDcFlushEnable(true);
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pc->setPipeControlFlushEnable(true);
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pc->setTextureCacheInvalidationEnable(true);
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pc->setCommandStreamerStallEnable(true);
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}
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template <typename GfxFamily>
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void DeviceQueueHw<GfxFamily>::addExecutionModelCleanUpSection(Kernel *parentKernel, TagNode<HwTimeStamps> *hwTimeStamp, uint32_t taskCount) {
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// CleanUp Section
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auto offset = slbCS.getUsed();
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auto alignmentSize = alignUp(offset, MemoryConstants::pageSize) - offset;
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slbCS.getSpace(alignmentSize);
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offset = slbCS.getUsed();
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igilQueue->m_controls.m_CleanupSectionAddress = ptrOffset(slbBuffer->getGpuAddress(), slbCS.getUsed());
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GpgpuWalkerHelper<GfxFamily>::applyWADisableLSQCROPERFforOCL(&slbCS, *parentKernel, true);
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using PIPE_CONTROL = typename GfxFamily::PIPE_CONTROL;
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if (hwTimeStamp != nullptr) {
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uint64_t timeStampAddress = hwTimeStamp->getGpuAddress() + offsetof(HwTimeStamps, ContextCompleteTS);
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igilQueue->m_controls.m_EventTimestampAddress = timeStampAddress;
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addProfilingEndCmds(timeStampAddress);
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//enable preemption
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addLriCmd(false);
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}
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uint64_t criticalSectionAddress = (uint64_t)&igilQueue->m_controls.m_CriticalSection;
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addPipeControlCmdWa();
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PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(&slbCS, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA, criticalSectionAddress, ExecutionModelCriticalSection::Free, false);
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uint64_t tagAddress = reinterpret_cast<uint64_t>(device->getDefaultEngine().commandStreamReceiver->getTagAddress());
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addPipeControlCmdWa();
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PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(&slbCS, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA, tagAddress, taskCount, false);
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addMediaStateClearCmds();
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auto pBBE = slbCS.getSpaceForCmd<MI_BATCH_BUFFER_END>();
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*pBBE = GfxFamily::cmdInitBatchBufferEnd;
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igilQueue->m_controls.m_CleanupSectionSize = (uint32_t)(slbCS.getUsed() - offset);
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}
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template <typename GfxFamily>
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void DeviceQueueHw<GfxFamily>::resetDSH() {
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if (heaps[IndirectHeap::DYNAMIC_STATE]) {
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heaps[IndirectHeap::DYNAMIC_STATE]->replaceBuffer(heaps[IndirectHeap::DYNAMIC_STATE]->getCpuBase(), heaps[IndirectHeap::DYNAMIC_STATE]->getMaxAvailableSpace());
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heaps[IndirectHeap::DYNAMIC_STATE]->getSpace(colorCalcStateSize);
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}
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}
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template <typename GfxFamily>
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IndirectHeap *DeviceQueueHw<GfxFamily>::getIndirectHeap(IndirectHeap::Type type) {
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if (!heaps[type]) {
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switch (type) {
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case IndirectHeap::DYNAMIC_STATE: {
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heaps[type] = new IndirectHeap(dshBuffer);
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// get space for colorCalc and 2 ID tables at the beginning
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heaps[type]->getSpace(colorCalcStateSize);
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break;
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}
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default:
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break;
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}
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}
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return heaps[type];
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}
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template <typename GfxFamily>
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size_t DeviceQueueHw<GfxFamily>::setSchedulerCrossThreadData(SchedulerKernel &scheduler) {
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using INTERFACE_DESCRIPTOR_DATA = typename GfxFamily::INTERFACE_DESCRIPTOR_DATA;
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size_t offset = dshBuffer->getUnderlyingBufferSize() - scheduler.getCurbeSize() - 4096; // Page size padding
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auto igilCmdQueue = reinterpret_cast<IGIL_CommandQueue *>(queueBuffer->getUnderlyingBuffer());
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igilCmdQueue->m_controls.m_SchedulerDSHOffset = (uint32_t)offset;
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igilCmdQueue->m_controls.m_SchedulerConstantBufferSize = (uint32_t)scheduler.getCurbeSize();
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return offset;
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}
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template <typename GfxFamily>
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void DeviceQueueHw<GfxFamily>::dispatchScheduler(LinearStream &commandStream, SchedulerKernel &scheduler, PreemptionMode preemptionMode, IndirectHeap *ssh, IndirectHeap *dsh) {
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GpgpuWalkerHelper<GfxFamily>::dispatchScheduler(commandStream,
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*this,
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preemptionMode,
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scheduler,
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ssh,
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dsh);
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return;
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}
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template <typename GfxFamily>
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size_t DeviceQueueHw<GfxFamily>::getCSPrefetchSize() {
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return 512;
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}
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template <typename GfxFamily>
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void DeviceQueueHw<GfxFamily>::addLriCmd(bool setArbCheck) {
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using MI_LOAD_REGISTER_IMM = typename GfxFamily::MI_LOAD_REGISTER_IMM;
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auto lri = slbCS.getSpaceForCmd<MI_LOAD_REGISTER_IMM>();
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*lri = GfxFamily::cmdInitLoadRegisterImm;
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lri->setRegisterOffset(0x2248); // CTXT_PREMP_DBG offset
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if (setArbCheck)
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lri->setDataDword(0x00000100); // set only bit 8 (Preempt On MI_ARB_CHK Only)
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else
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lri->setDataDword(0x0);
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}
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template <typename GfxFamily>
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size_t DeviceQueueHw<GfxFamily>::getExecutionModelCleanupSectionSize() {
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size_t totalSize = 0;
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totalSize += sizeof(PIPE_CONTROL) +
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2 * sizeof(MI_LOAD_REGISTER_REG) +
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sizeof(MI_LOAD_REGISTER_IMM) +
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sizeof(PIPE_CONTROL) +
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sizeof(MI_MATH) +
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NUM_ALU_INST_FOR_READ_MODIFY_WRITE * sizeof(MI_MATH_ALU_INST_INLINE);
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totalSize += getProfilingEndCmdsSize();
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totalSize += getMediaStateClearCmdsSize();
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totalSize += 4 * sizeof(PIPE_CONTROL);
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totalSize += sizeof(MI_BATCH_BUFFER_END);
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return totalSize;
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}
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template <typename GfxFamily>
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size_t DeviceQueueHw<GfxFamily>::getProfilingEndCmdsSize() {
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size_t size = 0;
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size += sizeof(PIPE_CONTROL) + sizeof(MI_STORE_REGISTER_MEM);
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size += sizeof(MI_LOAD_REGISTER_IMM);
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return size;
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}
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template <typename GfxFamily>
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void DeviceQueueHw<GfxFamily>::addDcFlushToPipeControlWa(PIPE_CONTROL *pc) {}
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} // namespace NEO
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