diff --git a/cmake/fill_core_types.cmake b/cmake/fill_core_types.cmake index 6ab9caf15a..67e6302c1f 100644 --- a/cmake/fill_core_types.cmake +++ b/cmake/fill_core_types.cmake @@ -10,5 +10,7 @@ list(APPEND ALL_CORE_TYPES "GEN11") list(APPEND ALL_CORE_TYPES "GEN12LP") list(APPEND ALL_CORE_TYPES "XE_HP_CORE") list(APPEND ALL_CORE_TYPES "XE_HPG_CORE") -list(APPEND XEHP_AND_LATER_CORE_TYPES "XE_HP_CORE" "XE_HPG_CORE") -list(APPEND DG2_AND_LATER_CORE_TYPES "XE_HPG_CORE") +list(APPEND ALL_CORE_TYPES "XE_HPC_CORE") +list(APPEND XEHP_AND_LATER_CORE_TYPES "XE_HP_CORE" "XE_HPG_CORE" "XE_HPC_CORE") +list(APPEND DG2_AND_LATER_CORE_TYPES "XE_HPG_CORE" "XE_HPC_CORE") +list(APPEND PVC_AND_LATER_CORE_TYPES "XE_HPC_CORE") diff --git a/cmake/setup_platform_flags.cmake b/cmake/setup_platform_flags.cmake index 94df56bf93..c4a5bd90d6 100644 --- a/cmake/setup_platform_flags.cmake +++ b/cmake/setup_platform_flags.cmake @@ -34,6 +34,15 @@ foreach(CORE_TYPE ${DG2_AND_LATER_CORE_TYPES}) endif() endforeach() +foreach(CORE_TYPE ${PVC_AND_LATER_CORE_TYPES}) + if(TESTS_${CORE_TYPE}) + set(TESTS_PVC_AND_LATER 1) + endif() + if(SUPPORT_${CORE_TYPE}) + set(SUPPORT_PVC_AND_LATER 1) + endif() +endforeach() + # Add supported and tested platforms if(SUPPORT_GEN8) set(CORE_GEN8_REVISIONS 0) @@ -261,3 +270,21 @@ if(SUPPORT_XE_HPG_CORE) endif() endif() endif() + +if(SUPPORT_XE_HPC_CORE) + set(XE_HPC_CORE_TEST_KERNELS_BLOCKLIST "CopyBuffer_simd8.cl") + set(CORE_XE_HPC_CORE_REVISIONS 0 3 30 157) + if(TESTS_XE_HPC_CORE) + ADD_ITEM_FOR_CORE_TYPE("FAMILY_NAME" "TESTED" "XE_HPC_CORE" "XE_HPC_COREFamily") + endif() + + if(SUPPORT_PVC) + ADD_PRODUCT("SUPPORTED" "PVC" "IGFX_PVC") + ADD_PLATFORM_FOR_CORE_TYPE("SUPPORTED" "XE_HPC_CORE" "PVC" "CORE") + ADD_PLATFORM_FOR_CORE_TYPE("SUPPORTED_AUX_TRANSLATION" "XE_HPC_CORE" "PVC" "CORE") + if(TESTS_PVC) + ADD_ITEM_FOR_CORE_TYPE("PLATFORMS" "TESTED" "XE_HPC_CORE" "PVC") + ADD_PRODUCT("TESTED" "PVC" "IGFX_PVC") + endif() + endif() +endif() diff --git a/level_zero/core/source/hw_helpers/l0_hw_helper_pvc_and_later.inl b/level_zero/core/source/hw_helpers/l0_hw_helper_pvc_and_later.inl new file mode 100644 index 0000000000..ac6fa31afc --- /dev/null +++ b/level_zero/core/source/hw_helpers/l0_hw_helper_pvc_and_later.inl @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/debug_settings/debug_settings_manager.h" +#include "shared/source/helpers/engine_node_helper.h" + +#include "level_zero/core/source/hw_helpers/l0_hw_helper.h" + +#include "engine_group_types.h" + +#include + +namespace L0 { + +template +void L0HwHelperHw::setAdditionalGroupProperty(ze_command_queue_group_properties_t &groupProperty, NEO::EngineGroupType groupType) const { + if (groupType == NEO::EngineGroupType::LinkedCopy) { + groupProperty.flags = ZE_COMMAND_QUEUE_GROUP_PROPERTY_FLAG_COPY; + groupProperty.maxMemoryFillPatternSize = sizeof(uint8_t); + } + + if (groupType == NEO::EngineGroupType::Copy && NEO::EngineHelpers::isBcsVirtualEngineEnabled()) { + groupProperty.flags = ZE_COMMAND_QUEUE_GROUP_PROPERTY_FLAG_COPY; + groupProperty.maxMemoryFillPatternSize = sizeof(uint8_t); + } +} + +} // namespace L0 diff --git a/level_zero/core/source/xe_hpc_core/CMakeLists.txt b/level_zero/core/source/xe_hpc_core/CMakeLists.txt new file mode 100644 index 0000000000..cfe7cd5c9e --- /dev/null +++ b/level_zero/core/source/xe_hpc_core/CMakeLists.txt @@ -0,0 +1,19 @@ +# +# Copyright (C) 2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# + +if(SUPPORT_XE_HPC_CORE) + set(HW_SOURCES_XE_HPC_CORE + ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt + ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_xe_hpc_core.inl + ${CMAKE_CURRENT_SOURCE_DIR}/debugger_xe_hpc_core.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/enable_family_full_l0_xe_hpc_core.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/l0_hw_helper_xe_hpc_core.cpp + ) + + add_subdirectories() + + target_sources(${L0_STATIC_LIB_NAME} PRIVATE ${HW_SOURCES_XE_HPC_CORE}) +endif() diff --git a/level_zero/core/source/xe_hpc_core/cmdlist_xe_hpc_core.inl b/level_zero/core/source/xe_hpc_core/cmdlist_xe_hpc_core.inl new file mode 100644 index 0000000000..39dd585c50 --- /dev/null +++ b/level_zero/core/source/xe_hpc_core/cmdlist_xe_hpc_core.inl @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "level_zero/core/source/cmdlist/cmdlist_hw.h" + +namespace L0 { + +template <> +NEO::PipeControlArgs CommandListCoreFamily::createBarrierFlags() { + NEO::PipeControlArgs args; + args.hdcPipelineFlush = true; + args.unTypedDataPortCacheFlush = true; + return args; +} + +template <> +ze_result_t CommandListCoreFamily::appendMemoryPrefetch(const void *ptr, size_t size) { + using MI_BATCH_BUFFER_END = GfxFamily::MI_BATCH_BUFFER_END; + auto allocData = device->getDriverHandle()->getSvmAllocsManager()->getSVMAlloc(ptr); + + if (!allocData) { + return ZE_RESULT_ERROR_INVALID_ARGUMENT; + } + + if (NEO::DebugManager.flags.AddStatePrefetchCmdToMemoryPrefetchAPI.get() != 1) { + return ZE_RESULT_SUCCESS; + } + + auto gpuAlloc = allocData->gpuAllocations.getGraphicsAllocation(device->getRootDeviceIndex()); + auto &hwInfo = device->getHwInfo(); + + commandContainer.addToResidencyContainer(gpuAlloc); + + size_t offset = ptrDiff(ptr, gpuAlloc->getGpuAddress()); + + NEO::LinearStream &cmdStream = *commandContainer.getCommandStream(); + + size_t estimatedSizeRequired = NEO::EncodeMemoryPrefetch::getSizeForMemoryPrefetch(size); + increaseCommandStreamSpace(estimatedSizeRequired); + + NEO::EncodeMemoryPrefetch::programMemoryPrefetch(cmdStream, *gpuAlloc, static_cast(size), offset, hwInfo); + + return ZE_RESULT_SUCCESS; +} +} // namespace L0 diff --git a/level_zero/core/source/xe_hpc_core/debugger_xe_hpc_core.cpp b/level_zero/core/source/xe_hpc_core/debugger_xe_hpc_core.cpp new file mode 100644 index 0000000000..8d92890ebb --- /dev/null +++ b/level_zero/core/source/xe_hpc_core/debugger_xe_hpc_core.cpp @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "level_zero/core/source/debugger/debugger_l0.inl" + +namespace NEO { +struct XE_HPC_COREFamily; +using GfxFamily = XE_HPC_COREFamily; + +} // namespace NEO + +namespace L0 { +template class DebuggerL0Hw; +DebuggerL0PopulateFactory debuggerXeHpcCore; +} // namespace L0 \ No newline at end of file diff --git a/level_zero/core/source/xe_hpc_core/enable_family_full_l0_xe_hpc_core.cpp b/level_zero/core/source/xe_hpc_core/enable_family_full_l0_xe_hpc_core.cpp new file mode 100644 index 0000000000..26328c51b2 --- /dev/null +++ b/level_zero/core/source/xe_hpc_core/enable_family_full_l0_xe_hpc_core.cpp @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/command_stream/aub_command_stream_receiver_hw.h" +#include "shared/source/command_stream/command_stream_receiver_hw.h" +#include "shared/source/command_stream/tbx_command_stream_receiver_hw.h" +#include "shared/source/helpers/populate_factory.h" + +#include "level_zero/core/source/helpers/l0_populate_factory.h" +#include "level_zero/core/source/hw_helpers/l0_hw_helper.h" + +namespace NEO { + +using Family = XE_HPC_COREFamily; + +struct EnableL0XeHpcCore { + EnableL0XeHpcCore() { + populateFactoryTable>(); + populateFactoryTable>(); + populateFactoryTable>(); + L0::populateFactoryTable>(); + } +}; + +static EnableL0XeHpcCore enable; +} // namespace NEO diff --git a/level_zero/core/source/xe_hpc_core/image_xe_hpc_core.inl b/level_zero/core/source/xe_hpc_core/image_xe_hpc_core.inl new file mode 100644 index 0000000000..bdae50d45c --- /dev/null +++ b/level_zero/core/source/xe_hpc_core/image_xe_hpc_core.inl @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/xe_hpc_core/hw_cmds.h" +#include "shared/source/xe_hpc_core/hw_info.h" + +#include "level_zero/core/source/image/image_hw.inl" diff --git a/level_zero/core/source/xe_hpc_core/l0_hw_helper_xe_hpc_core.cpp b/level_zero/core/source/xe_hpc_core/l0_hw_helper_xe_hpc_core.cpp new file mode 100644 index 0000000000..2a1e0c484e --- /dev/null +++ b/level_zero/core/source/xe_hpc_core/l0_hw_helper_xe_hpc_core.cpp @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "level_zero/core/source/helpers/l0_populate_factory.h" +#include "level_zero/core/source/hw_helpers/l0_hw_helper_base.inl" +#include "level_zero/core/source/hw_helpers/l0_hw_helper_pvc_and_later.inl" + +#include "hw_cmds.h" + +namespace L0 { + +using Family = NEO::XE_HPC_COREFamily; +static auto gfxCore = IGFX_XE_HPC_CORE; + +template <> +void populateFactoryTable>() { + extern L0HwHelper *l0HwHelperFactory[IGFX_MAX_CORE]; + l0HwHelperFactory[gfxCore] = &L0HwHelperHw::get(); +} + +template class L0HwHelperHw; + +} // namespace L0 diff --git a/level_zero/core/source/xe_hpc_core/pvc/CMakeLists.txt b/level_zero/core/source/xe_hpc_core/pvc/CMakeLists.txt new file mode 100644 index 0000000000..1b14a4f04e --- /dev/null +++ b/level_zero/core/source/xe_hpc_core/pvc/CMakeLists.txt @@ -0,0 +1,17 @@ +# +# Copyright (C) 2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# + +if(SUPPORT_PVC) + set(HW_SOURCES_XE_HPC_CORE + ${HW_SOURCES_XE_HPC_CORE} + ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt + ${CMAKE_CURRENT_SOURCE_DIR}/image_pvc.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/cmdlist_pvc.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/cmdqueue_pvc.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kernel_pvc.cpp + PARENT_SCOPE + ) +endif() diff --git a/level_zero/core/source/xe_hpc_core/pvc/cmdlist_pvc.cpp b/level_zero/core/source/xe_hpc_core/pvc/cmdlist_pvc.cpp new file mode 100644 index 0000000000..507248f49b --- /dev/null +++ b/level_zero/core/source/xe_hpc_core/pvc/cmdlist_pvc.cpp @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "level_zero/core/source/cmdlist/cmdlist_hw.inl" +#include "level_zero/core/source/cmdlist/cmdlist_hw_immediate.inl" +#include "level_zero/core/source/cmdlist/cmdlist_hw_xehp_and_later.inl" +#include "level_zero/core/source/xe_hpc_core/cmdlist_xe_hpc_core.inl" + +#include "cmdlist_extended.inl" + +namespace L0 { +template <> +void CommandListCoreFamily::applyMemoryRangesBarrier(uint32_t numRanges, + const size_t *pRangeSizes, + const void **pRanges) { + + increaseCommandStreamSpace(NEO::MemorySynchronizationCommands::getSizeForSinglePipeControl()); + + NEO::PipeControlArgs args = {}; + args.hdcPipelineFlush = true; + args.unTypedDataPortCacheFlush = true; + NEO::MemorySynchronizationCommands::addPipeControl(*commandContainer.getCommandStream(), args); +} + +template struct CommandListCoreFamily; + +template <> +struct CommandListProductFamily : public CommandListCoreFamily { + using CommandListCoreFamily::CommandListCoreFamily; +}; + +static CommandListPopulateFactory> + populatePVC; + +template <> +struct CommandListImmediateProductFamily : public CommandListCoreFamilyImmediate { + using CommandListCoreFamilyImmediate::CommandListCoreFamilyImmediate; +}; + +static CommandListImmediatePopulateFactory> + populatePVCImmediate; +} // namespace L0 diff --git a/level_zero/core/source/xe_hpc_core/pvc/cmdqueue_pvc.cpp b/level_zero/core/source/xe_hpc_core/pvc/cmdqueue_pvc.cpp new file mode 100644 index 0000000000..a2be0520bb --- /dev/null +++ b/level_zero/core/source/xe_hpc_core/pvc/cmdqueue_pvc.cpp @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/xe_hpc_core/hw_cmds.h" +#include "shared/source/xe_hpc_core/hw_info.h" + +#include "level_zero/core/source/cmdqueue/cmdqueue_hw.inl" +#include "level_zero/core/source/cmdqueue/cmdqueue_xe_hp_core_and_later.inl" + +#include "cmdqueue_extended.inl" +namespace L0 { +template struct CommandQueueHw; +static CommandQueuePopulateFactory> + populatePVC; + +} // namespace L0 diff --git a/level_zero/core/source/xe_hpc_core/pvc/image_pvc.cpp b/level_zero/core/source/xe_hpc_core/pvc/image_pvc.cpp new file mode 100644 index 0000000000..d273f182c1 --- /dev/null +++ b/level_zero/core/source/xe_hpc_core/pvc/image_pvc.cpp @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "level_zero/core/source/xe_hpc_core/image_xe_hpc_core.inl" + +namespace L0 { + +template <> +struct ImageProductFamily : public ImageCoreFamily { + using ImageCoreFamily::ImageCoreFamily; + + ze_result_t initialize(Device *device, const ze_image_desc_t *desc) override { + return ImageCoreFamily::initialize(device, desc); + }; +}; + +static ImagePopulateFactory> populatePVC; + +} // namespace L0 diff --git a/level_zero/core/source/xe_hpc_core/pvc/kernel_pvc.cpp b/level_zero/core/source/xe_hpc_core/pvc/kernel_pvc.cpp new file mode 100644 index 0000000000..6f43f546c4 --- /dev/null +++ b/level_zero/core/source/xe_hpc_core/pvc/kernel_pvc.cpp @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "level_zero/core/source/kernel/kernel_hw.h" + +namespace L0 { + +static KernelPopulateFactory> populatePVC; + +} // namespace L0 diff --git a/opencl/extensions/public/cl_ext_private.h b/opencl/extensions/public/cl_ext_private.h index 28f68eba17..d23183ad02 100644 --- a/opencl/extensions/public/cl_ext_private.h +++ b/opencl/extensions/public/cl_ext_private.h @@ -142,6 +142,7 @@ using cl_unified_shared_memory_capabilities_intel = cl_bitfield; #define CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_ROUND_ROBIN_INTEL 0x10023 #define CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_AFTER_DEPENDENCY_ROUND_ROBIN_INTEL 0x10024 #define CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_INTEL 0x10025 +#define CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_STALL_BASED_ROUND_ROBIN_INTEL 0x10026 /****************************** * SLICE COUNT SELECTING * diff --git a/opencl/source/helpers/CMakeLists.txt b/opencl/source/helpers/CMakeLists.txt index 71e9decdd0..bb28b36da9 100644 --- a/opencl/source/helpers/CMakeLists.txt +++ b/opencl/source/helpers/CMakeLists.txt @@ -58,6 +58,10 @@ if(SUPPORT_XEHP_AND_LATER) ) endif() +if(SUPPORT_PVC_AND_LATER) + list(APPEND RUNTIME_SRCS_HELPERS_BASE ${CMAKE_CURRENT_SOURCE_DIR}/cl_hw_helper_pvc_and_later.inl) +endif() + set(RUNTIME_SRCS_HELPERS_WINDOWS ${CMAKE_CURRENT_SOURCE_DIR}/windows/gl_helper.h ) diff --git a/opencl/source/helpers/cl_hw_helper_pvc_and_later.inl b/opencl/source/helpers/cl_hw_helper_pvc_and_later.inl new file mode 100644 index 0000000000..5bcb90a29c --- /dev/null +++ b/opencl/source/helpers/cl_hw_helper_pvc_and_later.inl @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "opencl/extensions/public/cl_ext_private.h" + +template <> +inline bool ClHwHelperHw::preferBlitterForLocalToLocalTransfers() const { + return true; +} + +template <> +std::vector ClHwHelperHw::getSupportedThreadArbitrationPolicies() const { + return std::vector{CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_OLDEST_FIRST_INTEL, CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_ROUND_ROBIN_INTEL, CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_AFTER_DEPENDENCY_ROUND_ROBIN_INTEL, CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_STALL_BASED_ROUND_ROBIN_INTEL}; +} + +template <> +bool ClHwHelperHw::allowImageCompression(cl_image_format format) const { + return true; +} diff --git a/opencl/source/xe_hpc_core/CMakeLists.txt b/opencl/source/xe_hpc_core/CMakeLists.txt new file mode 100644 index 0000000000..ade9f43d93 --- /dev/null +++ b/opencl/source/xe_hpc_core/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Copyright (C) 2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# + +if(SUPPORT_XE_HPC_CORE) + set(RUNTIME_SRCS_XE_HPC_CORE + ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt + ) + + target_sources(${NEO_STATIC_LIB_NAME} PRIVATE ${RUNTIME_SRCS_XE_HPC_CORE}) + set_property(GLOBAL PROPERTY RUNTIME_SRCS_XE_HPC_CORE ${RUNTIME_SRCS_XE_HPC_CORE}) +endif() diff --git a/opencl/source/xe_hpc_core/additionall_files_xe_hpc_core.cmake b/opencl/source/xe_hpc_core/additionall_files_xe_hpc_core.cmake new file mode 100644 index 0000000000..7d6e86b9da --- /dev/null +++ b/opencl/source/xe_hpc_core/additionall_files_xe_hpc_core.cmake @@ -0,0 +1,13 @@ +# +# Copyright (C) 2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# + +set(RUNTIME_SRCS_ADDITIONAL_FILES_XE_HPC_CORE + ${CMAKE_CURRENT_SOURCE_DIR}/xe_hpc_core/definitions${BRANCH_DIR_SUFFIX}gtpin_setup_xe_hpc_core.inl +) +include_directories(${NEO_SOURCE_DIR}/opencl/source/xe_hpc_core/definitions${BRANCH_DIR_SUFFIX}) + +target_sources(${NEO_STATIC_LIB_NAME} PRIVATE ${RUNTIME_SRCS_ADDITIONAL_FILES_XE_HPC_CORE}) +set_property(GLOBAL PROPERTY RUNTIME_SRCS_ADDITIONAL_FILES_XE_HPC_CORE ${RUNTIME_SRCS_ADDITIONAL_FILES_XE_HPC_CORE}) diff --git a/opencl/source/xe_hpc_core/buffer_xe_hpc_core.cpp b/opencl/source/xe_hpc_core/buffer_xe_hpc_core.cpp new file mode 100644 index 0000000000..aa2200bb58 --- /dev/null +++ b/opencl/source/xe_hpc_core/buffer_xe_hpc_core.cpp @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/xe_hpc_core/hw_cmds.h" + +#include "opencl/source/mem_obj/buffer_base.inl" + +namespace NEO { + +using Family = XE_HPC_COREFamily; +static auto gfxCore = IGFX_XE_HPC_CORE; + +template class BufferHw; + +#include "opencl/source/mem_obj/buffer_factory_init.inl" +} // namespace NEO diff --git a/opencl/source/xe_hpc_core/cl_hw_helper_xe_hpc_core.cpp b/opencl/source/xe_hpc_core/cl_hw_helper_xe_hpc_core.cpp new file mode 100644 index 0000000000..06d81ec284 --- /dev/null +++ b/opencl/source/xe_hpc_core/cl_hw_helper_xe_hpc_core.cpp @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/helpers/populate_factory.h" + +#include "opencl/source/helpers/cl_hw_helper_base.inl" +#include "opencl/source/helpers/cl_hw_helper_xehp_and_later.inl" + +#include "hw_cmds.h" + +namespace NEO { + +using Family = XE_HPC_COREFamily; +static auto gfxCore = IGFX_XE_HPC_CORE; + +#include "opencl/source/helpers/cl_hw_helper_pvc_and_later.inl" + +template <> +void populateFactoryTable>() { + extern ClHwHelper *clHwHelperFactory[IGFX_MAX_CORE]; + clHwHelperFactory[gfxCore] = &ClHwHelperHw::get(); +} + +template <> +bool ClHwHelperHw::requiresAuxResolves(const KernelInfo &kernelInfo, const HardwareInfo &hwInfo) const { + return false; +} + +template <> +inline bool ClHwHelperHw::getQueueFamilyName(std::string &name, EngineGroupType type) const { + switch (type) { + case EngineGroupType::RenderCompute: + name = "cccs"; + return true; + case EngineGroupType::LinkedCopy: + name = "linked bcs"; + return true; + default: + return false; + } +} + +template <> +cl_version ClHwHelperHw::getDeviceIpVersion(const HardwareInfo &hwInfo) const { + return makeDeviceIpVersion(12, 8, makeDeviceRevision(hwInfo)); +} + +template class ClHwHelperHw; + +} // namespace NEO diff --git a/opencl/source/xe_hpc_core/command_queue_xe_hpc_core.cpp b/opencl/source/xe_hpc_core/command_queue_xe_hpc_core.cpp new file mode 100644 index 0000000000..1f81a742db --- /dev/null +++ b/opencl/source/xe_hpc_core/command_queue_xe_hpc_core.cpp @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/helpers/populate_factory.h" +#include "shared/source/memory_manager/unified_memory_manager.h" + +#include "opencl/source/command_queue/command_queue_hw.h" +#include "opencl/source/command_queue/enqueue_resource_barrier.h" + +#include "enqueue_init_dispatch_globals.h" + +namespace NEO { + +using Family = XE_HPC_COREFamily; +static auto gfxCore = IGFX_XE_HPC_CORE; +} // namespace NEO + +#include "opencl/source/command_queue/command_queue_hw_xehp_and_later.inl" + +namespace NEO { +template <> +void populateFactoryTable>() { + extern CommandQueueCreateFunc commandQueueFactory[IGFX_MAX_CORE]; + commandQueueFactory[gfxCore] = CommandQueueHw::create; +} + +template <> +bool CommandQueueHw::isCacheFlushForBcsRequired() const { + if (DebugManager.flags.ForceCacheFlushForBcs.get() != -1) { + return !!DebugManager.flags.ForceCacheFlushForBcs.get(); + } + return false; +} +} // namespace NEO + +template class NEO::CommandQueueHw; diff --git a/opencl/source/xe_hpc_core/definitions/gtpin_setup_xe_hpc_core.inl b/opencl/source/xe_hpc_core/definitions/gtpin_setup_xe_hpc_core.inl new file mode 100644 index 0000000000..4ad9035052 --- /dev/null +++ b/opencl/source/xe_hpc_core/definitions/gtpin_setup_xe_hpc_core.inl @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +template <> +uint32_t GTPinHwHelperHw::getGenVersion() { + return gtpin::GTPIN_GEN_INVALID; +} \ No newline at end of file diff --git a/opencl/source/xe_hpc_core/enable_family_full_ocl_xe_hpc_core.cpp b/opencl/source/xe_hpc_core/enable_family_full_ocl_xe_hpc_core.cpp new file mode 100644 index 0000000000..ba7e8dd109 --- /dev/null +++ b/opencl/source/xe_hpc_core/enable_family_full_ocl_xe_hpc_core.cpp @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/command_stream/aub_command_stream_receiver_hw.h" +#include "shared/source/command_stream/tbx_command_stream_receiver_hw.h" +#include "shared/source/helpers/populate_factory.h" + +#include "opencl/source/command_queue/command_queue_hw.h" +#include "opencl/source/device_queue/device_queue_hw.h" +#include "opencl/source/helpers/cl_hw_helper.h" +#include "opencl/source/mem_obj/buffer.h" +#include "opencl/source/mem_obj/image.h" +#include "opencl/source/sampler/sampler.h" + +namespace NEO { + +using Family = XE_HPC_COREFamily; + +struct EnableOCLXeHpcCore { + EnableOCLXeHpcCore() { + populateFactoryTable>(); + populateFactoryTable>(); + populateFactoryTable>(); + populateFactoryTable>(); + populateFactoryTable>(); + populateFactoryTable>(); + populateFactoryTable>(); + populateFactoryTable>(); + } +}; + +static EnableOCLXeHpcCore enable; +} // namespace NEO diff --git a/opencl/source/xe_hpc_core/gpgpu_walker_xe_hpc_core.cpp b/opencl/source/xe_hpc_core/gpgpu_walker_xe_hpc_core.cpp new file mode 100644 index 0000000000..624e6cfeae --- /dev/null +++ b/opencl/source/xe_hpc_core/gpgpu_walker_xe_hpc_core.cpp @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "opencl/source/command_queue/gpgpu_walker_xehp_and_later.inl" +#include "opencl/source/command_queue/hardware_interface_xehp_and_later.inl" + +namespace NEO { + +template class GpgpuWalkerHelper; + +template class HardwareInterface; + +template struct EnqueueOperation; + +} // namespace NEO diff --git a/opencl/source/xe_hpc_core/gtpin_setup_xe_hpc_core.cpp b/opencl/source/xe_hpc_core/gtpin_setup_xe_hpc_core.cpp new file mode 100644 index 0000000000..1cc63b98aa --- /dev/null +++ b/opencl/source/xe_hpc_core/gtpin_setup_xe_hpc_core.cpp @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "opencl/source/gtpin/gtpin_hw_helper.h" +#include "opencl/source/gtpin/gtpin_hw_helper.inl" +#include "opencl/source/gtpin/gtpin_hw_helper_xehp_and_later.inl" + +#include "ocl_igc_shared/gtpin/gtpin_ocl_interface.h" + +namespace NEO { + +extern GTPinHwHelper *gtpinHwHelperFactory[IGFX_MAX_CORE]; + +using Family = XE_HPC_COREFamily; +static const auto gfxFamily = IGFX_XE_HPC_CORE; + +template class GTPinHwHelperHw; + +struct GTPinEnableXeHpcCore { + GTPinEnableXeHpcCore() { + gtpinHwHelperFactory[gfxFamily] = >PinHwHelperHw::get(); + } +}; + +#include "gtpin_setup_xe_hpc_core.inl" + +static GTPinEnableXeHpcCore gtpinEnable; + +} // namespace NEO diff --git a/opencl/source/xe_hpc_core/hardware_commands_helper_xe_hpc_core.cpp b/opencl/source/xe_hpc_core/hardware_commands_helper_xe_hpc_core.cpp new file mode 100644 index 0000000000..dc48f42f90 --- /dev/null +++ b/opencl/source/xe_hpc_core/hardware_commands_helper_xe_hpc_core.cpp @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/helpers/cache_flush_xehp_and_later.inl" +#include "shared/source/xe_hpc_core/hw_cmds.h" + +#include "opencl/source/helpers/hardware_commands_helper.h" +#include "opencl/source/helpers/hardware_commands_helper_base.inl" +#include "opencl/source/helpers/hardware_commands_helper_xehp_and_later.inl" + +namespace NEO { +using FamilyType = XE_HPC_COREFamily; + +template struct HardwareCommandsHelper; +} // namespace NEO diff --git a/opencl/source/xe_hpc_core/image_xe_hpc_core.cpp b/opencl/source/xe_hpc_core/image_xe_hpc_core.cpp new file mode 100644 index 0000000000..f6a47a449d --- /dev/null +++ b/opencl/source/xe_hpc_core/image_xe_hpc_core.cpp @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/gmm_helper/client_context/gmm_client_context.h" +#include "shared/source/xe_hpc_core/hw_cmds.h" + +#include "opencl/source/context/context.h" +#include "opencl/source/mem_obj/image.inl" + +namespace NEO { + +using Family = XE_HPC_COREFamily; +static auto gfxCore = IGFX_XE_HPC_CORE; + +} // namespace NEO + +#include "opencl/source/mem_obj/image_xehp_and_later.inl" + +namespace NEO { +// clang-format off +#include "opencl/source/mem_obj/image_tgllp_and_later.inl" +#include "opencl/source/mem_obj/image_factory_init.inl" +// clang-format on +} // namespace NEO diff --git a/opencl/source/xe_hpc_core/sampler_xe_hpc_core.cpp b/opencl/source/xe_hpc_core/sampler_xe_hpc_core.cpp new file mode 100644 index 0000000000..01a1080594 --- /dev/null +++ b/opencl/source/xe_hpc_core/sampler_xe_hpc_core.cpp @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/xe_hpc_core/hw_cmds_base.h" +using Family = NEO::XE_HPC_COREFamily; +constexpr static auto gfxCore = IGFX_XE_HPC_CORE; +#include "opencl/source/sampler/sampler_tgllp_and_later.inl" diff --git a/shared/source/aub_mem_dump/CMakeLists.txt b/shared/source/aub_mem_dump/CMakeLists.txt index e9140ecad3..972fcb53c7 100644 --- a/shared/source/aub_mem_dump/CMakeLists.txt +++ b/shared/source/aub_mem_dump/CMakeLists.txt @@ -28,5 +28,11 @@ if(SUPPORT_XEHP_AND_LATER) ) endif() +if(SUPPORT_PVC_AND_LATER) + list(APPEND NEO_CORE_AUB_MEM_DUMP + ${CMAKE_CURRENT_SOURCE_DIR}/aub_mem_dump_pvc_and_later.inl + ) +endif() + set_property(GLOBAL PROPERTY NEO_CORE_AUB_MEM_DUMP ${NEO_CORE_AUB_MEM_DUMP}) add_subdirectories() diff --git a/shared/source/aub_mem_dump/aub_mem_dump_pvc_and_later.inl b/shared/source/aub_mem_dump/aub_mem_dump_pvc_and_later.inl new file mode 100644 index 0000000000..dee046b69b --- /dev/null +++ b/shared/source/aub_mem_dump/aub_mem_dump_pvc_and_later.inl @@ -0,0 +1,322 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/aub_mem_dump/aub_alloc_dump.inl" +#include "shared/source/aub_mem_dump/aub_mem_dump.inl" +#include "shared/source/debug_settings/debug_settings_manager.h" +#include "shared/source/helpers/array_count.h" +#include "shared/source/helpers/completion_stamp.h" +#include "shared/source/helpers/hw_helper.h" + +#include "aub_mapper.h" +#include "config.h" +#include "reg_configs_common.h" + +namespace AubMemDump { + +enum { + device = deviceValue +}; + +// Instantiate these common template implementations. +template struct AubDump>; +template struct AubDump>; + +template struct AubPageTableHelper32>; +template struct AubPageTableHelper64>; +} // namespace AubMemDump + +namespace NEO { + +static const AubMemDump::LrcaHelperRcs rcs(0x002000); +static const AubMemDump::LrcaHelperBcs bcs(0x022000); +static const AubMemDump::LrcaHelperVcs vcs(0x1c0000); +static const AubMemDump::LrcaHelperVecs vecs(0x1c8000); +static const AubMemDump::LrcaHelperCcs ccs(0x1a000); +static const AubMemDump::LrcaHelperCcs ccs1(0x1c000); +static const AubMemDump::LrcaHelperCcs ccs2(0x1e000); +static const AubMemDump::LrcaHelperCcs ccs3(0x26000); +static const AubMemDump::LrcaHelperCccs cccs(-1); +static const AubMemDump::LrcaHelperLinkBcs linkBcs1(-1, 1); +static const AubMemDump::LrcaHelperLinkBcs linkBcs2(-1, 2); +static const AubMemDump::LrcaHelperLinkBcs linkBcs3(-1, 3); +static const AubMemDump::LrcaHelperLinkBcs linkBcs4(-1, 4); +static const AubMemDump::LrcaHelperLinkBcs linkBcs5(-1, 5); +static const AubMemDump::LrcaHelperLinkBcs linkBcs6(-1, 6); +static const AubMemDump::LrcaHelperLinkBcs linkBcs7(-1, 7); +static const AubMemDump::LrcaHelperLinkBcs linkBcs8(-1, 8); + +const AubMemDump::LrcaHelper *const AUBFamilyMapper::csTraits[aub_stream::NUM_ENGINES] = { + &rcs, + &bcs, + &vcs, + &vecs, + &ccs, + &ccs1, + &ccs2, + &ccs3, + &cccs, + &linkBcs1, + &linkBcs2, + &linkBcs3, + &linkBcs4, + &linkBcs5, + &linkBcs6, + &linkBcs7, + &linkBcs8}; + +const MMIOList AUBFamilyMapper::globalMMIO = { + // GLOBAL_MOCS + MMIOPair(0x00004000, 0x00000008), + MMIOPair(0x00004004, 0x00000038), + MMIOPair(0x00004008, 0x00000038), + MMIOPair(0x0000400C, 0x00000008), + MMIOPair(0x00004010, 0x00000018), + MMIOPair(0x00004014, 0x00060038), + MMIOPair(0x00004018, 0x00000000), + MMIOPair(0x0000401C, 0x00000033), + MMIOPair(0x00004020, 0x00060037), + MMIOPair(0x00004024, 0x0000003B), + MMIOPair(0x00004028, 0x00000032), + MMIOPair(0x0000402C, 0x00000036), + MMIOPair(0x00004030, 0x0000003A), + MMIOPair(0x00004034, 0x00000033), + MMIOPair(0x00004038, 0x00000037), + MMIOPair(0x0000403C, 0x0000003B), + MMIOPair(0x00004040, 0x00000030), + MMIOPair(0x00004044, 0x00000034), + MMIOPair(0x00004048, 0x00000038), + MMIOPair(0x0000404C, 0x00000031), + MMIOPair(0x00004050, 0x00000032), + MMIOPair(0x00004054, 0x00000036), + MMIOPair(0x00004058, 0x0000003A), + MMIOPair(0x0000405C, 0x00000033), + MMIOPair(0x00004060, 0x00000037), + MMIOPair(0x00004064, 0x0000003B), + MMIOPair(0x00004068, 0x00000032), + MMIOPair(0x0000406C, 0x00000036), + MMIOPair(0x00004070, 0x0000003A), + MMIOPair(0x00004074, 0x00000033), + MMIOPair(0x00004078, 0x00000037), + MMIOPair(0x0000407C, 0x0000003B), + MMIOPair(0x00004080, 0x00000030), + MMIOPair(0x00004084, 0x00000034), + MMIOPair(0x00004088, 0x00000038), + MMIOPair(0x0000408C, 0x00000031), + MMIOPair(0x00004090, 0x00000032), + MMIOPair(0x00004094, 0x00000036), + MMIOPair(0x00004098, 0x0000003A), + MMIOPair(0x0000409C, 0x00000033), + MMIOPair(0x000040A0, 0x00000037), + MMIOPair(0x000040A4, 0x0000003B), + MMIOPair(0x000040A8, 0x00000032), + MMIOPair(0x000040AC, 0x00000036), + MMIOPair(0x000040B0, 0x0000003A), + MMIOPair(0x000040B4, 0x00000033), + MMIOPair(0x000040B8, 0x00000037), + MMIOPair(0x000040BC, 0x0000003B), + MMIOPair(0x000040C0, 0x00000038), + MMIOPair(0x000040C4, 0x00000034), + MMIOPair(0x000040C8, 0x00000038), + MMIOPair(0x000040CC, 0x00000031), + MMIOPair(0x000040D0, 0x00000032), + MMIOPair(0x000040D4, 0x00000036), + MMIOPair(0x000040D8, 0x0000003A), + MMIOPair(0x000040DC, 0x00000033), + MMIOPair(0x000040E0, 0x00000037), + MMIOPair(0x000040E4, 0x0000003B), + MMIOPair(0x000040E8, 0x00000032), + MMIOPair(0x000040EC, 0x00000036), + MMIOPair(0x000040F0, 0x00000038), + MMIOPair(0x000040F4, 0x00000038), + MMIOPair(0x000040F8, 0x00000038), + MMIOPair(0x000040FC, 0x00000038), + + // LNCF_MOCS + MMIOPair(0x0000B020, 0x00300010), + MMIOPair(0x0000B024, 0x00300010), + MMIOPair(0x0000B028, 0x00300030), + MMIOPair(0x0000B02C, 0x00000000), + MMIOPair(0x0000B030, 0x0030001F), + MMIOPair(0x0000B034, 0x00170013), + MMIOPair(0x0000B038, 0x0000001F), + MMIOPair(0x0000B03C, 0x00000000), + MMIOPair(0x0000B040, 0x00100000), + MMIOPair(0x0000B044, 0x00170013), + MMIOPair(0x0000B048, 0x0010001F), + MMIOPair(0x0000B04C, 0x00170013), + MMIOPair(0x0000B050, 0x0030001F), + MMIOPair(0x0000B054, 0x00170013), + MMIOPair(0x0000B058, 0x0000001F), + MMIOPair(0x0000B05C, 0x00000000), + MMIOPair(0x0000B060, 0x00100000), + MMIOPair(0x0000B064, 0x00170013), + MMIOPair(0x0000B068, 0x0010001F), + MMIOPair(0x0000B06C, 0x00170013), + MMIOPair(0x0000B070, 0x0030001F), + MMIOPair(0x0000B074, 0x00170013), + MMIOPair(0x0000B078, 0x0000001F), + MMIOPair(0x0000B07C, 0x00000000), + MMIOPair(0x0000B080, 0x00300030), + MMIOPair(0x0000B084, 0x00170013), + MMIOPair(0x0000B088, 0x0010001F), + MMIOPair(0x0000B08C, 0x00170013), + MMIOPair(0x0000B090, 0x0030001F), + MMIOPair(0x0000B094, 0x00170013), + MMIOPair(0x0000B098, 0x00300010), + MMIOPair(0x0000B09C, 0x00300010), + + //PAT_INDEX + MMIOPair(0x00004100, 0x0000000), + MMIOPair(0x00004104, 0x0000000), + MMIOPair(0x00004108, 0x0000000), + MMIOPair(0x0000410c, 0x0000000), + MMIOPair(0x00004110, 0x0000000), + MMIOPair(0x00004114, 0x0000000), + MMIOPair(0x00004118, 0x0000000), + MMIOPair(0x0000411c, 0x0000000), + + MMIOPair(0x00004b80, 0xffff1001), //GACB_PERF_CTRL_REG + MMIOPair(0x00007000, 0xffff0000), //CACHE_MODE_0 + MMIOPair(0x00007004, 0xffff0000), //CACHE_MODE_1 + MMIOPair(0x000043F8, 0x00000000), //Gen12 (A-step) chicken bit for AuxT granularity + MMIOPair(0x00009008, 0x00000200), //IDICR + MMIOPair(0x0000900c, 0x00001b40), //SNPCR + MMIOPair(0x0000b120, 0x14000002), //LTCDREG + MMIOPair(0x00042080, 0x00000000), //CHICKEN_MISC_1 + MMIOPair(0x000020D4, 0xFFFF0000), //Chicken bit for CSFE + MMIOPair(0x0000B0A0, 0x00000000), //SCRATCH 2 for LNCF unit + MMIOPair(0x000094D4, 0x00000000), //Slice unit Level Clock Gating Control + + // Capture Perf MMIO register programming + MMIOPair(0x0000B004, 0x2FC0100B), //KM_ARBITER_CTRL_REG + MMIOPair(0x0000B404, 0x00000160), //KM_GLOBAL_INVALIDATION_REG + MMIOPair(0x00008708, 0x00000000), //KM_GEN12_IDI_CONTROL_REGISTER + + // Tiled Resources VA Translation Table L3 Pointer + MMIOPair(0x00004410, 0xffffffff), //GEN12_TRTT_NULL_TILE_REG + MMIOPair(0x00004414, 0xfffffffe), //GEN12_TRTT_INVD_TILE_REG + MMIOPair(0x00004404, 0x000000ff), //GEN12_TRTT_VA_MASKDATA_REG + MMIOPair(0x00004408, 0x00000000), //LDWORD GMM_GEN12_TRTT_L3_POINTER + MMIOPair(0x0000440C, 0x00000000), //UDWORD GMM_GEN12_TRTT_L3_POINTER + MMIOPair(0x00004400, 0x00000001), //GEN12_TRTT_TABLE_CONTROL + MMIOPair(0x00004DFC, 0x00000000), //GEN9_TR_CHICKEN_BIT_VECTOR +}; + +static const MMIOList mmioListRCS = { + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x00002058), 0x00000000), //CTX_WA_PTR_RCSUNIT + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000020a8), 0x00000000), //IMR + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE + + MMIOPair(0x00002090, 0xffff0000), //CHICKEN_PWR_CTX_RASTER_1 + MMIOPair(0x000020e0, 0xffff4000), //FF_SLICE_CS_CHICKEN1_RCSUNIT + MMIOPair(0x000020e4, 0xffff0000), //FF_SLICE_CS_CHICKEN2_RCSUNIT + MMIOPair(0x000020ec, 0xffff0051), //CS_DEBUG_MODE1 + + // FORCE_TO_NONPRIV + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024d0), 0x00007014), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024d4), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024d8), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024dc), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024e0), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024e4), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024e8), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024ec), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024f0), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024f4), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024f8), 0x0000e000), + MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x000024fc), 0x0000e000), + + MMIOPair(0x00002580, 0xffff0005), //CS_CHICKEN1 + MMIOPair(0x0000e194, 0xffff0002), //CHICKEN_SAMPLER_2 + + MMIOPair(0x0000B134, 0xA0000000) //L3ALLOCREG +}; + +static const MMIOList mmioListBCS = { + MMIOPair(AubMemDump::computeRegisterOffset(bcs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE +}; + +static const MMIOList mmioListVCS = { + MMIOPair(AubMemDump::computeRegisterOffset(vcs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE +}; + +static const MMIOList mmioListVECS = { + MMIOPair(AubMemDump::computeRegisterOffset(vecs.mmioBase, 0x0000229c), 0xffff8280), //GFX_MODE +}; + +static MMIOList mmioListCCSInstance(uint32_t mmioBase) { + MMIOList mmioList; + + mmioList.push_back(MMIOPair(0x0000ce90, 0x00030003)); //GFX_MULT_CTXT_CTL - enable multi-context with 4CCS + mmioList.push_back(MMIOPair(0x0000b170, 0x00030003)); //MULT_CTXT_CTL - enable multi-context with 4CCS + mmioList.push_back(MMIOPair(0x00014800, 0xFFFF0001)); //RCU_MODE + mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x0000229c), 0xffff8280)); //GFX_MODE + + // FORCE_TO_NONPRIV + mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024d0), 0x0000e000)); + mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024d4), 0x0000e000)); + mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024d8), 0x0000e000)); + mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024dc), 0x0000e000)); + mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024e0), 0x0000e000)); + mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024e4), 0x0000e000)); + mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024e8), 0x0000e000)); + mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024ec), 0x0000e000)); + mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024f0), 0x0000e000)); + mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024f4), 0x0000e000)); + mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024f8), 0x0000e000)); + mmioList.push_back(MMIOPair(AubMemDump::computeRegisterOffset(mmioBase, 0x000024fc), 0x0000e000)); + + mmioList.push_back(MMIOPair(0x0000B234, 0xA0000000)); //L3ALLOCREG_CCS0 + + return mmioList; +}; + +static const MMIOList mmioListCCS = mmioListCCSInstance(ccs.mmioBase); +static const MMIOList mmioListCCS1 = mmioListCCSInstance(ccs1.mmioBase); +static const MMIOList mmioListCCS2 = mmioListCCSInstance(ccs2.mmioBase); +static const MMIOList mmioListCCS3 = mmioListCCSInstance(ccs3.mmioBase); +static const MMIOList mmioListCCCS = {}; +static const MMIOList mmioListLinkBCS = {}; + +const MMIOList *AUBFamilyMapper::perEngineMMIO[aub_stream::NUM_ENGINES] = { + &mmioListRCS, + &mmioListBCS, + &mmioListVCS, + &mmioListVECS, + &mmioListCCS, + &mmioListCCS1, + &mmioListCCS2, + &mmioListCCS3, + &mmioListCCCS, + &mmioListLinkBCS, + &mmioListLinkBCS, + &mmioListLinkBCS, + &mmioListLinkBCS, + &mmioListLinkBCS, + &mmioListLinkBCS, + &mmioListLinkBCS, + &mmioListLinkBCS}; +} // namespace NEO + +namespace AubAllocDump { +using namespace NEO; + +template SurfaceInfo *getDumpSurfaceInfo(GraphicsAllocation &gfxAllocation, DumpFormat dumpFormat); + +template uint32_t getImageSurfaceTypeFromGmmResourceType(GMM_RESOURCE_TYPE gmmResourceType); + +template void dumpBufferInBinFormat(GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context); + +template void dumpImageInBmpFormat(GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context); + +template void dumpBufferInTreFormat(GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context); + +template void dumpImageInTreFormat(GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context); + +template void dumpAllocation(DumpFormat dumpFormat, GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context); +} // namespace AubAllocDump diff --git a/shared/source/aub_mem_dump/definitions/aub_services.h b/shared/source/aub_mem_dump/definitions/aub_services.h index 6e9d70ae78..de9c45d0d9 100644 --- a/shared/source/aub_mem_dump/definitions/aub_services.h +++ b/shared/source/aub_mem_dump/definitions/aub_services.h @@ -106,6 +106,7 @@ struct CmdServicesMemTraceVersion { XeHP_SDV = 29, Adlp = 34, Dg2 = 36, + Pvc = 39, }; }; struct RecordingMethodValues { diff --git a/shared/source/command_container/CMakeLists.txt b/shared/source/command_container/CMakeLists.txt index 0c143da55b..732bb1c18e 100644 --- a/shared/source/command_container/CMakeLists.txt +++ b/shared/source/command_container/CMakeLists.txt @@ -36,6 +36,12 @@ if(SUPPORT_DG2_AND_LATER) ) endif() +if(SUPPORT_PVC_AND_LATER) + list(APPEND NEO_CORE_COMMAND_CONTAINER + ${CMAKE_CURRENT_SOURCE_DIR}/memory_fence_encoder.h + ) +endif() + set_property(GLOBAL PROPERTY NEO_CORE_COMMAND_CONTAINER ${NEO_CORE_COMMAND_CONTAINER}) add_subdirectories() diff --git a/shared/source/command_container/memory_fence_encoder.h b/shared/source/command_container/memory_fence_encoder.h new file mode 100644 index 0000000000..6d234098e7 --- /dev/null +++ b/shared/source/command_container/memory_fence_encoder.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once + +#include "shared/source/command_stream/linear_stream.h" +#include "shared/source/memory_manager/graphics_allocation.h" + +namespace NEO { +template +struct EncodeMemoryFence { + using STATE_SYSTEM_MEM_FENCE_ADDRESS = typename GfxFamily::STATE_SYSTEM_MEM_FENCE_ADDRESS; + + static size_t getSystemMemoryFenceSize() { + return sizeof(STATE_SYSTEM_MEM_FENCE_ADDRESS); + } + static void encodeSystemMemoryFence(LinearStream &commandStream, const GraphicsAllocation *globalFenceAllocation) { + auto stateSystemFenceAddressSpace = commandStream.getSpaceForCmd(); + STATE_SYSTEM_MEM_FENCE_ADDRESS stateSystemFenceAddress = GfxFamily::cmdInitStateSystemMemFenceAddress; + stateSystemFenceAddress.setSystemMemoryFenceAddress(globalFenceAllocation->getGpuAddress()); + *stateSystemFenceAddressSpace = stateSystemFenceAddress; + } +}; +} // namespace NEO \ No newline at end of file diff --git a/shared/source/direct_submission/CMakeLists.txt b/shared/source/direct_submission/CMakeLists.txt index 043f509859..f9caa643f1 100644 --- a/shared/source/direct_submission/CMakeLists.txt +++ b/shared/source/direct_submission/CMakeLists.txt @@ -26,6 +26,12 @@ if(SUPPORT_XEHP_AND_LATER) ) endif() +if(SUPPORT_PVC_AND_LATER) + list(APPEND NEO_CORE_DIRECT_SUBMISSION + ${CMAKE_CURRENT_SOURCE_DIR}/direct_submission_prefetcher_pvc_and_later.inl + ) +endif() + set_property(GLOBAL PROPERTY NEO_CORE_DIRECT_SUBMISSION ${NEO_CORE_DIRECT_SUBMISSION}) add_subdirectories() diff --git a/shared/source/direct_submission/direct_submission_prefetcher_pvc_and_later.inl b/shared/source/direct_submission/direct_submission_prefetcher_pvc_and_later.inl new file mode 100644 index 0000000000..c0716e5c07 --- /dev/null +++ b/shared/source/direct_submission/direct_submission_prefetcher_pvc_and_later.inl @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/direct_submission/direct_submission_hw.h" + +namespace NEO { + +template +inline void DirectSubmissionHw::dispatchDisablePrefetcher(bool disable) { + using MI_ARB_CHECK = typename GfxFamily::MI_ARB_CHECK; + + MI_ARB_CHECK arbCheck = GfxFamily::cmdInitArbCheck; + arbCheck.setPreParserDisable(disable); + MI_ARB_CHECK *arbCheckSpace = ringCommandStream.getSpaceForCmd(); + *arbCheckSpace = arbCheck; +} + +} // namespace NEO \ No newline at end of file diff --git a/shared/source/gen_common/aub_mapper.h b/shared/source/gen_common/aub_mapper.h index d59eb595c2..194feab1c2 100644 --- a/shared/source/gen_common/aub_mapper.h +++ b/shared/source/gen_common/aub_mapper.h @@ -23,4 +23,7 @@ #endif #ifdef SUPPORT_XE_HPG_CORE #include "shared/source/xe_hpg_core/aub_mapper.h" -#endif \ No newline at end of file +#endif +#ifdef SUPPORT_XE_HPC_CORE +#include "shared/source/xe_hpc_core/aub_mapper.h" +#endif diff --git a/shared/source/generated/xe_hpc_core/hw_cmds_generated_xe_hpc_core.inl b/shared/source/generated/xe_hpc_core/hw_cmds_generated_xe_hpc_core.inl new file mode 100644 index 0000000000..1899f1ae2c --- /dev/null +++ b/shared/source/generated/xe_hpc_core/hw_cmds_generated_xe_hpc_core.inl @@ -0,0 +1,7533 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma pack(1) + +typedef struct tagBINDING_TABLE_STATE { + union tagTheStructure { + struct tagCommon { + uint32_t Reserved_0 : BITFIELD_RANGE(0, 5); + uint32_t SurfaceStatePointer : BITFIELD_RANGE(6, 31); + } Common; + uint32_t RawData[1]; + } TheStructure; + typedef enum tagPATCH_CONSTANTS { + SURFACESTATEPOINTER_BYTEOFFSET = 0x0, + SURFACESTATEPOINTER_INDEX = 0x0, + } PATCH_CONSTANTS; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + } + static tagBINDING_TABLE_STATE sInit() { + BINDING_TABLE_STATE state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 1); + return TheStructure.RawData[index]; + } + inline const uint32_t &getRawData(const uint32_t index) const { + DEBUG_BREAK_IF(index >= 1); + return TheStructure.RawData[index]; + } + typedef enum tagSURFACESTATEPOINTER { + SURFACESTATEPOINTER_BIT_SHIFT = 0x6, + SURFACESTATEPOINTER_ALIGN_SIZE = 0x40, + } SURFACESTATEPOINTER; + inline void setSurfaceStatePointer(const uint64_t value) { + DEBUG_BREAK_IF(value >= 0x100000000); + TheStructure.Common.SurfaceStatePointer = (uint32_t)value >> SURFACESTATEPOINTER_BIT_SHIFT; + } + inline uint32_t getSurfaceStatePointer() const { + return (TheStructure.Common.SurfaceStatePointer << SURFACESTATEPOINTER_BIT_SHIFT); + } +} BINDING_TABLE_STATE; +STATIC_ASSERT(4 == sizeof(BINDING_TABLE_STATE)); + +typedef struct tagMEDIA_SURFACE_STATE { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t CompressionFormat : BITFIELD_RANGE(0, 4); + uint32_t Reserved115_5 : BITFIELD_RANGE(5, 11); + uint32_t Reserved_12 : BITFIELD_RANGE(12, 15); + uint32_t Reserved_16 : BITFIELD_RANGE(16, 19); + uint32_t Reserved_20 : BITFIELD_RANGE(20, 26); + uint32_t Reserved_27 : BITFIELD_RANGE(27, 29); + uint32_t Rotation : BITFIELD_RANGE(30, 31); + // DWORD 1 + uint32_t Cr_VCb_UPixelOffsetVDirection : BITFIELD_RANGE(0, 1); + uint32_t PictureStructure : BITFIELD_RANGE(2, 3); + uint32_t Width : BITFIELD_RANGE(4, 17); + uint32_t Height : BITFIELD_RANGE(18, 31); + // DWORD 2 + uint32_t TileMode : BITFIELD_RANGE(0, 1); + uint32_t HalfPitchForChroma : BITFIELD_RANGE(2, 2); + uint32_t SurfacePitch : BITFIELD_RANGE(3, 20); + uint32_t AddressControl : BITFIELD_RANGE(21, 21); + uint32_t MemoryCompressionEnable : BITFIELD_RANGE(22, 22); + uint32_t MemoryCompressionType : BITFIELD_RANGE(23, 23); + uint32_t Cr_VCb_UPixelOffsetVDirectionMsb : BITFIELD_RANGE(24, 24); + uint32_t Cr_VCb_UPixelOffsetUDirection : BITFIELD_RANGE(25, 25); + uint32_t InterleaveChroma : BITFIELD_RANGE(26, 26); + uint32_t SurfaceFormat : BITFIELD_RANGE(27, 31); + // DWORD 3 + uint32_t YOffsetForU_Cb : BITFIELD_RANGE(0, 13); + uint32_t Reserved_110 : BITFIELD_RANGE(14, 15); + uint32_t XOffsetForU_Cb : BITFIELD_RANGE(16, 29); + uint32_t Reserved_126 : BITFIELD_RANGE(30, 31); + // DWORD 4 + uint32_t Reserved_128 : BITFIELD_RANGE(0, 14); + uint32_t Reserved_143 : BITFIELD_RANGE(15, 15); + uint32_t Reserved_144 : BITFIELD_RANGE(16, 29); + uint32_t Reserved_158 : BITFIELD_RANGE(30, 31); + // DWORD 5 + uint32_t SurfaceMemoryObjectControlStateReserved_160 : BITFIELD_RANGE(0, 0); + uint32_t SurfaceMemoryObjectControlStateIndexToMocsTables : BITFIELD_RANGE(1, 6); + uint32_t Reserved_167 : BITFIELD_RANGE(7, 17); + uint32_t Reserved_178 : BITFIELD_RANGE(18, 19); + uint32_t Reserved_180 : BITFIELD_RANGE(20, 29); + uint32_t VerticalLineStrideOffset : BITFIELD_RANGE(30, 30); + uint32_t VerticalLineStride : BITFIELD_RANGE(31, 31); + // DWORD 6 + uint32_t SurfaceBaseAddressLow; + // DWORD 7 + uint32_t SurfaceBaseAddressHigh : BITFIELD_RANGE(0, 15); + uint32_t Reserved_240 : BITFIELD_RANGE(16, 31); + } Common; + struct tagSurfaceFormatIsOneOfPlanarFormats { + // DWORD 0 + uint32_t Reserved_0 : BITFIELD_RANGE(0, 4); + uint32_t Reserved_5 : BITFIELD_RANGE(5, 11); + uint32_t Reserved_12 : BITFIELD_RANGE(12, 15); + uint32_t YOffset : BITFIELD_RANGE(16, 19); + uint32_t XOffset : BITFIELD_RANGE(20, 26); + uint32_t Reserved_27 : BITFIELD_RANGE(27, 29); + uint32_t Reserved_30 : BITFIELD_RANGE(30, 31); + // DWORD 1 + uint32_t Reserved_32 : BITFIELD_RANGE(0, 1); + uint32_t Reserved_34 : BITFIELD_RANGE(2, 3); + uint32_t Reserved_36 : BITFIELD_RANGE(4, 17); + uint32_t Reserved_50 : BITFIELD_RANGE(18, 31); + // DWORD 2 + uint32_t Reserved_64 : BITFIELD_RANGE(0, 1); + uint32_t Reserved_66 : BITFIELD_RANGE(2, 2); + uint32_t Reserved_67 : BITFIELD_RANGE(3, 20); + uint32_t Reserved_85 : BITFIELD_RANGE(21, 21); + uint32_t Reserved_86 : BITFIELD_RANGE(22, 22); + uint32_t Reserved_87 : BITFIELD_RANGE(23, 23); + uint32_t Reserved_88 : BITFIELD_RANGE(24, 24); + uint32_t Reserved_89 : BITFIELD_RANGE(25, 25); + uint32_t Reserved_90 : BITFIELD_RANGE(26, 26); + uint32_t Reserved_91 : BITFIELD_RANGE(27, 31); + // DWORD 3 + uint32_t Reserved_96 : BITFIELD_RANGE(0, 13); + uint32_t Reserved_110 : BITFIELD_RANGE(14, 15); + uint32_t Reserved_112 : BITFIELD_RANGE(16, 29); + uint32_t Reserved_126 : BITFIELD_RANGE(30, 31); + // DWORD 4 + uint32_t Reserved_128 : BITFIELD_RANGE(0, 14); + uint32_t Reserved_143 : BITFIELD_RANGE(15, 15); + uint32_t Reserved_144 : BITFIELD_RANGE(16, 29); + uint32_t Reserved_158 : BITFIELD_RANGE(30, 31); + // DWORD 5 + uint32_t Reserved_160 : BITFIELD_RANGE(0, 0); + uint32_t Reserved_161 : BITFIELD_RANGE(1, 6); + uint32_t Reserved_167 : BITFIELD_RANGE(7, 17); + uint32_t Reserved_178 : BITFIELD_RANGE(18, 19); + uint32_t Reserved_180 : BITFIELD_RANGE(20, 29); + uint32_t Reserved_190 : BITFIELD_RANGE(30, 30); + uint32_t Reserved_191 : BITFIELD_RANGE(31, 31); + // DWORD 6 + uint32_t Reserved_192; + // DWORD 7 + uint32_t Reserved_224 : BITFIELD_RANGE(0, 15); + uint32_t Reserved_240 : BITFIELD_RANGE(16, 31); + } SurfaceFormatIsOneOfPlanarFormats; + struct tag_SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0 { + // DWORD 0 + uint32_t Reserved_0 : BITFIELD_RANGE(0, 4); + uint32_t Reserved_5 : BITFIELD_RANGE(5, 11); + uint32_t Reserved_12 : BITFIELD_RANGE(12, 15); + uint32_t Reserved_16 : BITFIELD_RANGE(16, 19); + uint32_t Reserved_20 : BITFIELD_RANGE(20, 26); + uint32_t Reserved_27 : BITFIELD_RANGE(27, 29); + uint32_t Reserved_30 : BITFIELD_RANGE(30, 31); + // DWORD 1 + uint32_t Reserved_32 : BITFIELD_RANGE(0, 1); + uint32_t Reserved_34 : BITFIELD_RANGE(2, 3); + uint32_t Reserved_36 : BITFIELD_RANGE(4, 17); + uint32_t Reserved_50 : BITFIELD_RANGE(18, 31); + // DWORD 2 + uint32_t Reserved_64 : BITFIELD_RANGE(0, 1); + uint32_t Reserved_66 : BITFIELD_RANGE(2, 2); + uint32_t Reserved_67 : BITFIELD_RANGE(3, 20); + uint32_t Reserved_85 : BITFIELD_RANGE(21, 21); + uint32_t Reserved_86 : BITFIELD_RANGE(22, 22); + uint32_t Reserved_87 : BITFIELD_RANGE(23, 23); + uint32_t Reserved_88 : BITFIELD_RANGE(24, 24); + uint32_t Reserved_89 : BITFIELD_RANGE(25, 25); + uint32_t Reserved_90 : BITFIELD_RANGE(26, 26); + uint32_t Reserved_91 : BITFIELD_RANGE(27, 31); + // DWORD 3 + uint32_t Reserved_96 : BITFIELD_RANGE(0, 13); + uint32_t Reserved_110 : BITFIELD_RANGE(14, 15); + uint32_t Reserved_112 : BITFIELD_RANGE(16, 29); + uint32_t Reserved_126 : BITFIELD_RANGE(30, 31); + // DWORD 4 + uint32_t YOffsetForV_Cr : BITFIELD_RANGE(0, 14); + uint32_t Reserved_143 : BITFIELD_RANGE(15, 15); + uint32_t XOffsetForV_Cr : BITFIELD_RANGE(16, 29); + uint32_t Reserved_158 : BITFIELD_RANGE(30, 31); + // DWORD 5 + uint32_t Reserved_160 : BITFIELD_RANGE(0, 0); + uint32_t Reserved_161 : BITFIELD_RANGE(1, 6); + uint32_t Reserved_167 : BITFIELD_RANGE(7, 17); + uint32_t Reserved_178 : BITFIELD_RANGE(18, 19); + uint32_t Reserved_180 : BITFIELD_RANGE(20, 29); + uint32_t Reserved_190 : BITFIELD_RANGE(30, 30); + uint32_t Reserved_191 : BITFIELD_RANGE(31, 31); + // DWORD 6 + uint32_t Reserved_192; + // DWORD 7 + uint32_t Reserved_224 : BITFIELD_RANGE(0, 15); + uint32_t Reserved_240 : BITFIELD_RANGE(16, 31); + } _SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0; + uint32_t RawData[8]; + } TheStructure; + typedef enum tagCOMPRESSION_FORMAT { + COMPRESSION_FORMAT_RGBA16_FLOAT = 0x1, + COMPRESSION_FORMAT_Y210 = 0x2, + COMPRESSION_FORMAT_YUY2 = 0x3, + COMPRESSION_FORMAT_Y410_1010102 = 0x4, + COMPRESSION_FORMAT_Y216 = 0x5, + COMPRESSION_FORMAT_Y416 = 0x6, + COMPRESSION_FORMAT_P010 = 0x7, + COMPRESSION_FORMAT_P016 = 0x8, + COMPRESSION_FORMAT_AYUV = 0x9, + COMPRESSION_FORMAT_ARGB_8B = 0xa, + COMPRESSION_FORMAT_YCRCB_SWAPY = 0xb, + COMPRESSION_FORMAT_YCRCB_SWAPUV = 0xc, + COMPRESSION_FORMAT_YCRCB_SWAPUVY = 0xd, + COMPRESSION_FORMAT_RGB_10B = 0xe, + COMPRESSION_FORMAT_NV21NV12 = 0xf, + } COMPRESSION_FORMAT; + typedef enum tagROTATION { + ROTATION_NO_ROTATION_OR_0_DEGREE = 0x0, + ROTATION_90_DEGREE_ROTATION = 0x1, + ROTATION_180_DEGREE_ROTATION = 0x2, + ROTATION_270_DEGREE_ROTATION = 0x3, + } ROTATION; + typedef enum tagPICTURE_STRUCTURE { + PICTURE_STRUCTURE_FRAME_PICTURE = 0x0, + PICTURE_STRUCTURE_TOP_FIELD_PICTURE = 0x1, + PICTURE_STRUCTURE_BOTTOM_FIELD_PICTURE = 0x2, + PICTURE_STRUCTURE_INVALID_NOT_ALLOWED = 0x3, + } PICTURE_STRUCTURE; + typedef enum tagTILE_MODE { + TILE_MODE_TILEMODE_LINEAR = 0x0, + TILE_MODE_TILES_64K = 0x1, + TILE_MODE_TILEMODE_XMAJOR = 0x2, + TILE_MODE_TILEMODE_YMAJOR = 0x3, + } TILE_MODE; + typedef enum tagADDRESS_CONTROL { + ADDRESS_CONTROL_CLAMP = 0x0, + ADDRESS_CONTROL_MIRROR = 0x1, + } ADDRESS_CONTROL; + typedef enum tagMEMORY_COMPRESSION_TYPE { + MEMORY_COMPRESSION_TYPE_MEDIA_COMPRESSION = 0x0, + MEMORY_COMPRESSION_TYPE_RENDER_COMPRESSION = 0x1, + } MEMORY_COMPRESSION_TYPE; + typedef enum tagSURFACE_FORMAT { + SURFACE_FORMAT_YCRCB_NORMAL = 0x0, + SURFACE_FORMAT_YCRCB_SWAPUVY = 0x1, + SURFACE_FORMAT_YCRCB_SWAPUV = 0x2, + SURFACE_FORMAT_YCRCB_SWAPY = 0x3, + SURFACE_FORMAT_PLANAR_420_8 = 0x4, + SURFACE_FORMAT_Y8_UNORM_VA = 0x5, + SURFACE_FORMAT_R10G10B10A2_UNORM = 0x8, + SURFACE_FORMAT_R8G8B8A8_UNORM = 0x9, + SURFACE_FORMAT_R8B8_UNORM_CRCB = 0xa, + SURFACE_FORMAT_R8_UNORM_CRCB = 0xb, + SURFACE_FORMAT_Y8_UNORM = 0xc, + SURFACE_FORMAT_A8Y8U8V8_UNORM = 0xd, + SURFACE_FORMAT_B8G8R8A8_UNORM = 0xe, + SURFACE_FORMAT_R16G16B16A16 = 0xf, + SURFACE_FORMAT_Y1_UNORM = 0x10, + SURFACE_FORMAT_PLANAR_422_8 = 0x12, + SURFACE_FORMAT_PLANAR_420_16 = 0x17, + SURFACE_FORMAT_R16B16_UNORM_CRCB = 0x18, + SURFACE_FORMAT_R16_UNORM_CRCB = 0x19, + SURFACE_FORMAT_Y16_UNORM = 0x1a, + } SURFACE_FORMAT; + typedef enum tagSURFACE_MEMORY_OBJECT_CONTROL_STATE { + SURFACE_MEMORY_OBJECT_CONTROL_STATE_DEFAULTVAUEDESC = 0x0, + } SURFACE_MEMORY_OBJECT_CONTROL_STATE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.Rotation = ROTATION_NO_ROTATION_OR_0_DEGREE; + TheStructure.Common.PictureStructure = PICTURE_STRUCTURE_FRAME_PICTURE; + TheStructure.Common.TileMode = TILE_MODE_TILEMODE_LINEAR; + TheStructure.Common.AddressControl = ADDRESS_CONTROL_CLAMP; + TheStructure.Common.MemoryCompressionType = MEMORY_COMPRESSION_TYPE_MEDIA_COMPRESSION; + TheStructure.Common.SurfaceFormat = SURFACE_FORMAT_YCRCB_NORMAL; + } + static tagMEDIA_SURFACE_STATE sInit() { + MEDIA_SURFACE_STATE state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 8); + return TheStructure.RawData[index]; + } + inline void setCompressionFormat(uint32_t compressionFormat) { + UNRECOVERABLE_IF(compressionFormat > 0x1F); + TheStructure.Common.CompressionFormat = compressionFormat; + } + inline uint32_t getCompressionFormat() const { + return TheStructure.Common.CompressionFormat; + } + inline void setRotation(const ROTATION value) { + TheStructure.Common.Rotation = value; + } + inline ROTATION getRotation() const { + return static_cast(TheStructure.Common.Rotation); + } + inline void setCrVCbUPixelOffsetVDirection(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3); + TheStructure.Common.Cr_VCb_UPixelOffsetVDirection = value; + } + inline uint32_t getCrVCbUPixelOffsetVDirection() const { + return TheStructure.Common.Cr_VCb_UPixelOffsetVDirection; + } + inline void setPictureStructure(const PICTURE_STRUCTURE value) { + TheStructure.Common.PictureStructure = value; + } + inline PICTURE_STRUCTURE getPictureStructure() const { + return static_cast(TheStructure.Common.PictureStructure); + } + inline void setWidth(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3fff0); + TheStructure.Common.Width = value - 1; + } + inline uint32_t getWidth() const { + return TheStructure.Common.Width + 1; + } + inline void setHeight(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xfffc0000); + TheStructure.Common.Height = value - 1; + } + inline uint32_t getHeight() const { + return TheStructure.Common.Height + 1; + } + inline void setTileMode(const TILE_MODE value) { + TheStructure.Common.TileMode = value; + } + inline TILE_MODE getTileMode() const { + return static_cast(TheStructure.Common.TileMode); + } + inline void setHalfPitchForChroma(const bool value) { + TheStructure.Common.HalfPitchForChroma = value; + } + inline bool getHalfPitchForChroma() const { + return TheStructure.Common.HalfPitchForChroma; + } + inline void setSurfacePitch(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x1ffff8); + TheStructure.Common.SurfacePitch = value - 1; + } + inline uint32_t getSurfacePitch() const { + return TheStructure.Common.SurfacePitch + 1; + } + inline void setAddressControl(const ADDRESS_CONTROL value) { + TheStructure.Common.AddressControl = value; + } + inline ADDRESS_CONTROL getAddressControl() const { + return static_cast(TheStructure.Common.AddressControl); + } + inline void setMemoryCompressionEnable(const bool value) { + TheStructure.Common.MemoryCompressionEnable = value; + } + inline bool getMemoryCompressionEnable() const { + return TheStructure.Common.MemoryCompressionEnable; + } + inline void setMemoryCompressionType(const MEMORY_COMPRESSION_TYPE value) { + TheStructure.Common.MemoryCompressionType = value; + } + inline MEMORY_COMPRESSION_TYPE getMemoryCompressionType() const { + return static_cast(TheStructure.Common.MemoryCompressionType); + } + inline void setCrVCbUPixelOffsetVDirectionMsb(const bool value) { + TheStructure.Common.Cr_VCb_UPixelOffsetVDirectionMsb = value; + } + inline bool getCrVCbUPixelOffsetVDirectionMsb() const { + return TheStructure.Common.Cr_VCb_UPixelOffsetVDirectionMsb; + } + inline void setCrVCbUPixelOffsetUDirection(const bool value) { + TheStructure.Common.Cr_VCb_UPixelOffsetUDirection = value; + } + inline bool getCrVCbUPixelOffsetUDirection() const { + return TheStructure.Common.Cr_VCb_UPixelOffsetUDirection; + } + inline void setInterleaveChroma(const bool value) { + TheStructure.Common.InterleaveChroma = value; + } + inline bool getInterleaveChroma() const { + return TheStructure.Common.InterleaveChroma; + } + inline void setSurfaceFormat(const SURFACE_FORMAT value) { + TheStructure.Common.SurfaceFormat = value; + } + inline SURFACE_FORMAT getSurfaceFormat() const { + return static_cast(TheStructure.Common.SurfaceFormat); + } + inline void setYOffsetForUCb(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3fff); + TheStructure.Common.YOffsetForU_Cb = value; + } + inline uint32_t getYOffsetForUCb() const { + return TheStructure.Common.YOffsetForU_Cb; + } + inline void setXOffsetForUCb(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3fff0000); + TheStructure.Common.XOffsetForU_Cb = value; + } + inline uint32_t getXOffsetForUCb() const { + return TheStructure.Common.XOffsetForU_Cb; + } + inline void setSurfaceMemoryObjectControlStateIndexToMocsTables(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x7e); + TheStructure.Common.SurfaceMemoryObjectControlStateIndexToMocsTables = value; + } + inline uint32_t getSurfaceMemoryObjectControlStateIndexToMocsTables() const { + return TheStructure.Common.SurfaceMemoryObjectControlStateIndexToMocsTables; + } + inline void setVerticalLineStrideOffset(const bool value) { + TheStructure.Common.VerticalLineStrideOffset = value; + } + inline bool getVerticalLineStrideOffset() const { + return TheStructure.Common.VerticalLineStrideOffset; + } + inline void setVerticalLineStride(const bool value) { + TheStructure.Common.VerticalLineStride = value; + } + inline bool getVerticalLineStride() const { + return TheStructure.Common.VerticalLineStride; + } + inline void setSurfaceBaseAddress(const uint64_t value) { + TheStructure.Common.SurfaceBaseAddressLow = static_cast(value & 0xffffffff); + TheStructure.Common.SurfaceBaseAddressHigh = (value >> 32) & 0xffffffff; + } + inline uint64_t getSurfaceBaseAddress() const { + return (TheStructure.Common.SurfaceBaseAddressLow | + static_cast(TheStructure.Common.SurfaceBaseAddressHigh) << 32); + } + inline void setSurfaceBaseAddressHigh(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xffff); + TheStructure.Common.SurfaceBaseAddressHigh = value; + } + inline uint32_t getSurfaceBaseAddressHigh() const { + return TheStructure.Common.SurfaceBaseAddressHigh; + } + inline void setYOffset(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xf0000); + TheStructure.SurfaceFormatIsOneOfPlanarFormats.YOffset = value; + } + inline uint32_t getYOffset() const { + return TheStructure.SurfaceFormatIsOneOfPlanarFormats.YOffset; + } + inline void setXOffset(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x7f00000); + TheStructure.SurfaceFormatIsOneOfPlanarFormats.XOffset = value; + } + inline uint32_t getXOffset() const { + return TheStructure.SurfaceFormatIsOneOfPlanarFormats.XOffset; + } + inline void setYOffsetForVCr(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x7fff); + TheStructure._SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0.YOffsetForV_Cr = value; + } + inline uint32_t getYOffsetForVCr() const { + return TheStructure._SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0.YOffsetForV_Cr; + } + inline void setXOffsetForVCr(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3fff0000); + TheStructure._SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0.XOffsetForV_Cr = value; + } + inline uint32_t getXOffsetForVCr() const { + return TheStructure._SurfaceFormatIsOneOfPlanarAnd_InterleaveChromaIs0.XOffsetForV_Cr; + } +} MEDIA_SURFACE_STATE; +STATIC_ASSERT(32 == sizeof(MEDIA_SURFACE_STATE)); + +typedef struct tagMEM_COPY { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t CompressionFormat : BITFIELD_RANGE(8, 12); + uint32_t DestinationCompressionEnable : BITFIELD_RANGE(13, 13); + uint32_t Reserved_14 : BITFIELD_RANGE(14, 14); + uint32_t DestinationCompressible : BITFIELD_RANGE(15, 15); + uint32_t SourceCompressible : BITFIELD_RANGE(16, 16); + uint32_t CopyType : BITFIELD_RANGE(17, 18); + uint32_t Reserved_19 : BITFIELD_RANGE(19, 21); + uint32_t InstructionTarget_Opcode : BITFIELD_RANGE(22, 28); + uint32_t Client : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint32_t TransferWidth : BITFIELD_RANGE(0, 17); + uint32_t Reserved_50 : BITFIELD_RANGE(18, 31); + // DWORD 2 + uint32_t TransferHeight : BITFIELD_RANGE(0, 17); + uint32_t Reserved_82 : BITFIELD_RANGE(18, 31); + // DWORD 3 + uint32_t SourcePitch : BITFIELD_RANGE(0, 17); + uint32_t Reserved_114 : BITFIELD_RANGE(18, 31); + // DWORD 4 + uint32_t DestinationPitch : BITFIELD_RANGE(0, 17); + uint32_t Reserved_146 : BITFIELD_RANGE(18, 31); + // DWORD 5..6 + uint64_t SourceBaseAddress; + // DWORD 7..8 + uint64_t DestinationBaseAddress; + // DWORD 9 + uint32_t DestinationMocs : BITFIELD_RANGE(0, 6); + uint32_t Reserved_295 : BITFIELD_RANGE(7, 24); + uint32_t SourceMocs : BITFIELD_RANGE(25, 31); + } Common; + uint32_t RawData[10]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x8, + } DWORD_LENGTH; + typedef enum tagDESTINATION_COMPRESSION_ENABLE { + DESTINATION_COMPRESSION_ENABLE_DISABLE = 0x0, + DESTINATION_COMPRESSION_ENABLE_ENABLE = 0x1, + } DESTINATION_COMPRESSION_ENABLE; + typedef enum tagDESTINATION_COMPRESSIBLE { + DESTINATION_COMPRESSIBLE_NOT_COMPRESSIBLE = 0x0, + DESTINATION_COMPRESSIBLE_COMPRESSIBLE = 0x1, + } DESTINATION_COMPRESSIBLE; + typedef enum tagSOURCE_COMPRESSIBLE { + SOURCE_COMPRESSIBLE_NOT_COMPRESSIBLE = 0x0, + SOURCE_COMPRESSIBLE_COMPRESSIBLE = 0x1, + } SOURCE_COMPRESSIBLE; + typedef enum tagCOPY_TYPE { + COPY_TYPE_LINEAR_COPY = 0x0, + COPY_TYPE_MATRIX_COPY = 0x1, + } COPY_TYPE; + typedef enum tagINSTRUCTIONTARGET_OPCODE { + INSTRUCTIONTARGET_OPCODE_OPCODE = 0x5A, + } INSTRUCTIONTARGET_OPCODE; + typedef enum tagCLIENT { + CLIENT_2D_PROCESSOR = 0x2, + } CLIENT; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.DestinationCompressionEnable = DESTINATION_COMPRESSION_ENABLE_DISABLE; + TheStructure.Common.DestinationCompressible = DESTINATION_COMPRESSIBLE_NOT_COMPRESSIBLE; + TheStructure.Common.SourceCompressible = SOURCE_COMPRESSIBLE_NOT_COMPRESSIBLE; + TheStructure.Common.CopyType = COPY_TYPE_LINEAR_COPY; + TheStructure.Common.InstructionTarget_Opcode = INSTRUCTIONTARGET_OPCODE_OPCODE; + TheStructure.Common.Client = CLIENT_2D_PROCESSOR; + } + static tagMEM_COPY sInit() { + MEM_COPY state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 10); + return TheStructure.RawData[index]; + } + inline void setCompressionFormat(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x1f); + TheStructure.Common.CompressionFormat = value; + } + inline uint32_t getCompressionFormat() const { + return TheStructure.Common.CompressionFormat; + } + inline void setDestinationCompressionEnable(const DESTINATION_COMPRESSION_ENABLE value) { + TheStructure.Common.DestinationCompressionEnable = value; + } + inline DESTINATION_COMPRESSION_ENABLE getDestinationCompressionEnable() const { + return static_cast(TheStructure.Common.DestinationCompressionEnable); + } + inline void setDestinationCompressible(const DESTINATION_COMPRESSIBLE value) { + TheStructure.Common.DestinationCompressible = value; + } + inline DESTINATION_COMPRESSIBLE getDestinationCompressible() const { + return static_cast(TheStructure.Common.DestinationCompressible); + } + inline void setSourceCompressible(const SOURCE_COMPRESSIBLE value) { + TheStructure.Common.SourceCompressible = value; + } + inline SOURCE_COMPRESSIBLE getSourceCompressible() const { + return static_cast(TheStructure.Common.SourceCompressible); + } + inline void setCopyType(const COPY_TYPE value) { + TheStructure.Common.CopyType = value; + } + inline COPY_TYPE getCopyType() const { + return static_cast(TheStructure.Common.CopyType); + } + inline void setInstructionTargetOpcode(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x7f); + TheStructure.Common.InstructionTarget_Opcode = value; + } + inline uint32_t getInstructionTargetOpcode() const { + return TheStructure.Common.InstructionTarget_Opcode; + } + inline void setClient(const CLIENT value) { + TheStructure.Common.Client = value; + } + inline CLIENT getClient() const { + return static_cast(TheStructure.Common.Client); + } + inline void setDestinationX2CoordinateRight(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3ffff + 1); + TheStructure.Common.TransferWidth = value - 1; + } + inline uint32_t getDestinationX2CoordinateRight() const { + return TheStructure.Common.TransferWidth + 1; + } + inline void setDestinationY2CoordinateBottom(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3ffff + 1); + TheStructure.Common.TransferHeight = value - 1; + } + inline uint32_t getDestinationY2CoordinateBottom() const { + return TheStructure.Common.TransferHeight + 1; + } + inline void setSourcePitch(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3ffff + 1); + TheStructure.Common.SourcePitch = value - 1; + } + inline uint32_t getSourcePitch() const { + return TheStructure.Common.SourcePitch + 1; + } + inline void setDestinationPitch(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3ffff + 1); + TheStructure.Common.DestinationPitch = value - 1; + } + inline uint32_t getDestinationPitch() const { + return TheStructure.Common.DestinationPitch + 1; + } + inline void setSourceBaseAddress(const uint64_t value) { + TheStructure.Common.SourceBaseAddress = value; + } + inline uint64_t getSourceBaseAddress() const { + return TheStructure.Common.SourceBaseAddress; + } + inline void setDestinationBaseAddress(const uint64_t value) { + TheStructure.Common.DestinationBaseAddress = value; + } + inline uint64_t getDestinationBaseAddress() const { + return TheStructure.Common.DestinationBaseAddress; + } + inline void setDestinationMOCS(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x7f); + TheStructure.Common.DestinationMocs = value; + } + inline uint32_t getDestinationMOCS() const { + return TheStructure.Common.DestinationMocs; + } + inline void setSourceMOCS(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x7f); + TheStructure.Common.SourceMocs = value; + } + inline uint32_t getSourceMOCS() const { + return TheStructure.Common.SourceMocs; + } +} MEM_COPY; +STATIC_ASSERT(40 == sizeof(MEM_COPY)); + +typedef struct tagMI_MATH { + union _DW0 { + struct _BitField { + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved : BITFIELD_RANGE(8, 22); + uint32_t InstructionOpcode : BITFIELD_RANGE(23, 28); + uint32_t InstructionType : BITFIELD_RANGE(29, 31); + } BitField; + uint32_t Value; + } DW0; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_MATH = 0x1A, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; +} MI_MATH; + +typedef struct tagMI_MATH_ALU_INST_INLINE { + union _DW0 { + struct _BitField { + uint32_t Operand2 : BITFIELD_RANGE(0, 9); + uint32_t Operand1 : BITFIELD_RANGE(10, 19); + uint32_t ALUOpcode : BITFIELD_RANGE(20, 31); + } BitField; + uint32_t Value; + } DW0; +} MI_MATH_ALU_INST_INLINE; + +typedef struct tagPIPE_CONTROL { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t PredicateEnable : BITFIELD_RANGE(8, 8); + uint32_t HdcPipelineFlush : BITFIELD_RANGE(9, 9); + uint32_t Reserved_10 : BITFIELD_RANGE(10, 10); + uint32_t UnTypedDataPortCacheFlush : BITFIELD_RANGE(11, 11); + uint32_t Reserved_12 : BITFIELD_RANGE(12, 12); + uint32_t CompressionControlSurface_CcsFlush : BITFIELD_RANGE(13, 13); + uint32_t WorkloadPartitionIdOffsetEnable : BITFIELD_RANGE(14, 14); + uint32_t Reserved_15 : BITFIELD_RANGE(15, 15); + uint32_t _3DCommandSubOpcode : BITFIELD_RANGE(16, 23); + uint32_t _3DCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t CommandSubtype : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint32_t DepthCacheFlushEnable : BITFIELD_RANGE(0, 0); + uint32_t StallAtPixelScoreboard : BITFIELD_RANGE(1, 1); + uint32_t StateCacheInvalidationEnable : BITFIELD_RANGE(2, 2); + uint32_t ConstantCacheInvalidationEnable : BITFIELD_RANGE(3, 3); + uint32_t VfCacheInvalidationEnable : BITFIELD_RANGE(4, 4); + uint32_t DcFlushEnable : BITFIELD_RANGE(5, 5); + uint32_t Reserved_38 : BITFIELD_RANGE(6, 6); + uint32_t PipeControlFlushEnable : BITFIELD_RANGE(7, 7); + uint32_t NotifyEnable : BITFIELD_RANGE(8, 8); + uint32_t IndirectStatePointersDisable : BITFIELD_RANGE(9, 9); + uint32_t TextureCacheInvalidationEnable : BITFIELD_RANGE(10, 10); + uint32_t InstructionCacheInvalidateEnable : BITFIELD_RANGE(11, 11); + uint32_t RenderTargetCacheFlushEnable : BITFIELD_RANGE(12, 12); + uint32_t DepthStallEnable : BITFIELD_RANGE(13, 13); + uint32_t PostSyncOperation : BITFIELD_RANGE(14, 15); + uint32_t GenericMediaStateClear : BITFIELD_RANGE(16, 16); + uint32_t PssStallSyncEnable : BITFIELD_RANGE(17, 17); + uint32_t TlbInvalidate : BITFIELD_RANGE(18, 18); + uint32_t DepthStallSyncEnable : BITFIELD_RANGE(19, 19); + uint32_t CommandStreamerStallEnable : BITFIELD_RANGE(20, 20); + uint32_t StoreDataIndex : BITFIELD_RANGE(21, 21); + uint32_t Reserved_54 : BITFIELD_RANGE(22, 22); + uint32_t LriPostSyncOperation : BITFIELD_RANGE(23, 23); + uint32_t DestinationAddressType : BITFIELD_RANGE(24, 24); + uint32_t AmfsFlushEnable : BITFIELD_RANGE(25, 25); + uint32_t FlushLlc : BITFIELD_RANGE(26, 26); + uint32_t Reserved_59 : BITFIELD_RANGE(27, 27); + uint32_t TileCacheFlushEnable : BITFIELD_RANGE(28, 28); + uint32_t CommandCacheInvalidateEnable : BITFIELD_RANGE(29, 29); + uint32_t L3FabricFlush : BITFIELD_RANGE(30, 30); + uint32_t TbimrForceBatchClosure : BITFIELD_RANGE(31, 31); + // DWORD 2 + uint32_t Reserved_64 : BITFIELD_RANGE(0, 1); + uint32_t Address : BITFIELD_RANGE(2, 31); + // DWORD 3 + uint32_t AddressHigh; + // DWORD 4 + uint64_t ImmediateData; + } Common; + uint32_t RawData[6]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_DWORD_COUNT_N = 0x4, + } DWORD_LENGTH; + typedef enum tagUN_TYPED_DATA_PORT_CACHE_FLUSH { + UN_TYPED_DATA_PORT_CACHE_FLUSH_DISABLED = 0x0, + UN_TYPED_DATA_PORT_CACHE_FLUSH_ENABLED = 0x1, + } UN_TYPED_DATA_PORT_CACHE_FLUSH; + typedef enum tag_3D_COMMAND_SUB_OPCODE { + _3D_COMMAND_SUB_OPCODE_PIPE_CONTROL = 0x0, + } _3D_COMMAND_SUB_OPCODE; + typedef enum tag_3D_COMMAND_OPCODE { + _3D_COMMAND_OPCODE_PIPE_CONTROL = 0x2, + } _3D_COMMAND_OPCODE; + typedef enum tagCOMMAND_SUBTYPE { + COMMAND_SUBTYPE_GFXPIPE_3D = 0x3, + } COMMAND_SUBTYPE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + typedef enum tagPOST_SYNC_OPERATION { + POST_SYNC_OPERATION_NO_WRITE = 0x0, + POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA = 0x1, + POST_SYNC_OPERATION_WRITE_PS_DEPTH_COUNT = 0x2, + POST_SYNC_OPERATION_WRITE_TIMESTAMP = 0x3, + } POST_SYNC_OPERATION; + typedef enum tagLRI_POST_SYNC_OPERATION { + LRI_POST_SYNC_OPERATION_NO_LRI_OPERATION = 0x0, + LRI_POST_SYNC_OPERATION_MMIO_WRITE_IMMEDIATE_DATA = 0x1, + } LRI_POST_SYNC_OPERATION; + typedef enum tagDESTINATION_ADDRESS_TYPE { + DESTINATION_ADDRESS_TYPE_PPGTT = 0x0, + DESTINATION_ADDRESS_TYPE_GGTT = 0x1, + } DESTINATION_ADDRESS_TYPE; + typedef enum tagTBIMR_FORCE_BATCH_CLOSURE { + TBIMR_FORCE_BATCH_CLOSURE_NO_BATCH_CLOSURE = 0x0, + TBIMR_FORCE_BATCH_CLOSURE_CLOSE_BATCH = 0x1, + } TBIMR_FORCE_BATCH_CLOSURE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_DWORD_COUNT_N; + TheStructure.Common.UnTypedDataPortCacheFlush = UN_TYPED_DATA_PORT_CACHE_FLUSH_DISABLED; + TheStructure.Common._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_PIPE_CONTROL; + TheStructure.Common._3DCommandOpcode = _3D_COMMAND_OPCODE_PIPE_CONTROL; + TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_3D; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + TheStructure.Common.PostSyncOperation = POST_SYNC_OPERATION_NO_WRITE; + TheStructure.Common.LriPostSyncOperation = LRI_POST_SYNC_OPERATION_NO_LRI_OPERATION; + TheStructure.Common.DestinationAddressType = DESTINATION_ADDRESS_TYPE_PPGTT; + TheStructure.Common.TbimrForceBatchClosure = TBIMR_FORCE_BATCH_CLOSURE_NO_BATCH_CLOSURE; + TheStructure.Common.CommandStreamerStallEnable = 1; // Patched + } + static tagPIPE_CONTROL sInit() { + PIPE_CONTROL state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 6); + return TheStructure.RawData[index]; + } + inline void setPredicateEnable(const bool value) { + TheStructure.Common.PredicateEnable = value; + } + inline bool getPredicateEnable() const { + return TheStructure.Common.PredicateEnable; + } + inline void setHdcPipelineFlush(const bool value) { + TheStructure.Common.HdcPipelineFlush = value; + } + inline bool getHdcPipelineFlush() const { + return TheStructure.Common.HdcPipelineFlush; + } + inline void setUnTypedDataPortCacheFlush(const bool value) { + TheStructure.Common.UnTypedDataPortCacheFlush = value; + } + inline bool getUnTypedDataPortCacheFlush() const { + return TheStructure.Common.UnTypedDataPortCacheFlush; + } + inline void setCompressionControlSurfaceCcsFlush(const bool value) { + TheStructure.Common.CompressionControlSurface_CcsFlush = value; + } + inline bool getCompressionControlSurfaceCcsFlush() const { + return TheStructure.Common.CompressionControlSurface_CcsFlush; + } + inline void setWorkloadPartitionIdOffsetEnable(const bool value) { + TheStructure.Common.WorkloadPartitionIdOffsetEnable = value; + } + inline bool getWorkloadPartitionIdOffsetEnable() const { + return TheStructure.Common.WorkloadPartitionIdOffsetEnable; + } + inline void setDepthCacheFlushEnable(const bool value) { + TheStructure.Common.DepthCacheFlushEnable = value; + } + inline bool getDepthCacheFlushEnable() const { + return TheStructure.Common.DepthCacheFlushEnable; + } + inline void setStallAtPixelScoreboard(const bool value) { + TheStructure.Common.StallAtPixelScoreboard = value; + } + inline bool getStallAtPixelScoreboard() const { + return TheStructure.Common.StallAtPixelScoreboard; + } + inline void setStateCacheInvalidationEnable(const bool value) { + TheStructure.Common.StateCacheInvalidationEnable = value; + } + inline bool getStateCacheInvalidationEnable() const { + return TheStructure.Common.StateCacheInvalidationEnable; + } + inline void setConstantCacheInvalidationEnable(const bool value) { + TheStructure.Common.ConstantCacheInvalidationEnable = value; + } + inline bool getConstantCacheInvalidationEnable() const { + return TheStructure.Common.ConstantCacheInvalidationEnable; + } + inline void setVfCacheInvalidationEnable(const bool value) { + TheStructure.Common.VfCacheInvalidationEnable = value; + } + inline bool getVfCacheInvalidationEnable() const { + return TheStructure.Common.VfCacheInvalidationEnable; + } + inline void setDcFlushEnable(const bool value) { + TheStructure.Common.DcFlushEnable = value; + } + inline bool getDcFlushEnable() const { + return TheStructure.Common.DcFlushEnable; + } + inline void setPipeControlFlushEnable(const bool value) { + TheStructure.Common.PipeControlFlushEnable = value; + } + inline bool getPipeControlFlushEnable() const { + return TheStructure.Common.PipeControlFlushEnable; + } + inline void setNotifyEnable(const bool value) { + TheStructure.Common.NotifyEnable = value; + } + inline bool getNotifyEnable() const { + return TheStructure.Common.NotifyEnable; + } + inline void setIndirectStatePointersDisable(const bool value) { + TheStructure.Common.IndirectStatePointersDisable = value; + } + inline bool getIndirectStatePointersDisable() const { + return TheStructure.Common.IndirectStatePointersDisable; + } + inline void setTextureCacheInvalidationEnable(const bool value) { + TheStructure.Common.TextureCacheInvalidationEnable = value; + } + inline bool getTextureCacheInvalidationEnable() const { + return TheStructure.Common.TextureCacheInvalidationEnable; + } + inline void setInstructionCacheInvalidateEnable(const bool value) { + TheStructure.Common.InstructionCacheInvalidateEnable = value; + } + inline bool getInstructionCacheInvalidateEnable() const { + return TheStructure.Common.InstructionCacheInvalidateEnable; + } + inline void setRenderTargetCacheFlushEnable(const bool value) { + TheStructure.Common.RenderTargetCacheFlushEnable = value; + } + inline bool getRenderTargetCacheFlushEnable() const { + return TheStructure.Common.RenderTargetCacheFlushEnable; + } + inline void setDepthStallEnable(const bool value) { + TheStructure.Common.DepthStallEnable = value; + } + inline bool getDepthStallEnable() const { + return TheStructure.Common.DepthStallEnable; + } + inline void setPostSyncOperation(const POST_SYNC_OPERATION value) { + TheStructure.Common.PostSyncOperation = value; + } + inline POST_SYNC_OPERATION getPostSyncOperation() const { + return static_cast(TheStructure.Common.PostSyncOperation); + } + inline void setGenericMediaStateClear(const bool value) { + TheStructure.Common.GenericMediaStateClear = value; + } + inline bool getGenericMediaStateClear() const { + return TheStructure.Common.GenericMediaStateClear; + } + inline void setPssStallSyncEnable(const bool value) { + TheStructure.Common.PssStallSyncEnable = value; + } + inline bool getPssStallSyncEnable() const { + return TheStructure.Common.PssStallSyncEnable; + } + inline void setTlbInvalidate(const bool value) { + TheStructure.Common.TlbInvalidate = value; + } + inline bool getTlbInvalidate() const { + return TheStructure.Common.TlbInvalidate; + } + inline void setDepthStallSyncEnable(const bool value) { + TheStructure.Common.DepthStallSyncEnable = value; + } + inline bool getDepthStallSyncEnable() const { + return TheStructure.Common.DepthStallSyncEnable; + } + inline void setCommandStreamerStallEnable(const bool value) { + TheStructure.Common.CommandStreamerStallEnable = value; + } + inline bool getCommandStreamerStallEnable() const { + return TheStructure.Common.CommandStreamerStallEnable; + } + inline void setStoreDataIndex(const bool value) { + TheStructure.Common.StoreDataIndex = value; + } + inline bool getStoreDataIndex() const { + return TheStructure.Common.StoreDataIndex; + } + inline void setLriPostSyncOperation(const LRI_POST_SYNC_OPERATION value) { + TheStructure.Common.LriPostSyncOperation = value; + } + inline LRI_POST_SYNC_OPERATION getLriPostSyncOperation() const { + return static_cast(TheStructure.Common.LriPostSyncOperation); + } + inline void setDestinationAddressType(const DESTINATION_ADDRESS_TYPE value) { + TheStructure.Common.DestinationAddressType = value; + } + inline DESTINATION_ADDRESS_TYPE getDestinationAddressType() const { + return static_cast(TheStructure.Common.DestinationAddressType); + } + inline void setAmfsFlushEnable(const bool value) { + TheStructure.Common.AmfsFlushEnable = value; + } + inline bool getAmfsFlushEnable() const { + return TheStructure.Common.AmfsFlushEnable; + } + inline void setFlushLlc(const bool value) { + TheStructure.Common.FlushLlc = value; + } + inline bool getFlushLlc() const { + return TheStructure.Common.FlushLlc; + } + inline void setTileCacheFlushEnable(const bool value) { + TheStructure.Common.TileCacheFlushEnable = value; + } + inline bool getTileCacheFlushEnable() const { + return TheStructure.Common.TileCacheFlushEnable; + } + inline void setCommandCacheInvalidateEnable(const bool value) { + TheStructure.Common.CommandCacheInvalidateEnable = value; + } + inline bool getCommandCacheInvalidateEnable() const { + return TheStructure.Common.CommandCacheInvalidateEnable; + } + inline void setL3FabricFlush(const bool value) { + TheStructure.Common.L3FabricFlush = value; + } + inline bool getL3FabricFlush() const { + return TheStructure.Common.L3FabricFlush; + } + inline void setTbimrForceBatchClosure(const TBIMR_FORCE_BATCH_CLOSURE value) { + TheStructure.Common.TbimrForceBatchClosure = value; + } + inline TBIMR_FORCE_BATCH_CLOSURE getTbimrForceBatchClosure() const { + return static_cast(TheStructure.Common.TbimrForceBatchClosure); + } + typedef enum tagADDRESS { + ADDRESS_BIT_SHIFT = 0x2, + ADDRESS_ALIGN_SIZE = 0x4, + } ADDRESS; + inline void setAddress(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xffffffff); + TheStructure.Common.Address = value >> ADDRESS_BIT_SHIFT; + } + inline uint32_t getAddress() const { + return TheStructure.Common.Address << ADDRESS_BIT_SHIFT; + } + inline void setAddressHigh(const uint32_t value) { + TheStructure.Common.AddressHigh = value; + } + inline uint32_t getAddressHigh() const { + return TheStructure.Common.AddressHigh; + } + inline void setImmediateData(const uint64_t value) { + TheStructure.Common.ImmediateData = value; + } + inline uint64_t getImmediateData() const { + return TheStructure.Common.ImmediateData; + } +} PIPE_CONTROL; +STATIC_ASSERT(24 == sizeof(PIPE_CONTROL)); + +typedef struct tagMI_ATOMIC { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t AtomicOpcode : BITFIELD_RANGE(8, 15); + uint32_t ReturnDataControl : BITFIELD_RANGE(16, 16); + uint32_t CsStall : BITFIELD_RANGE(17, 17); + uint32_t InlineData : BITFIELD_RANGE(18, 18); + uint32_t DataSize : BITFIELD_RANGE(19, 20); + uint32_t PostSyncOperation : BITFIELD_RANGE(21, 21); + uint32_t MemoryType : BITFIELD_RANGE(22, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint64_t WorkloadPartitionIdOffsetEnable : BITFIELD_RANGE(0, 0); + uint64_t Reserved_33 : BITFIELD_RANGE(1, 1); + uint64_t MemoryAddress : BITFIELD_RANGE(2, 63); + // DWORD 3 + uint32_t Operand1DataDword0; + // DWORD 4 + uint32_t Operand2DataDword0; + // DWORD 5 + uint32_t Operand1DataDword1; + // DWORD 6 + uint32_t Operand2DataDword1; + // DWORD 7 + uint32_t Operand1DataDword2; + // DWORD 8 + uint32_t Operand2DataDword2; + // DWORD 9 + uint32_t Operand1DataDword3; + // DWORD 10 + uint32_t Operand2DataDword3; + } Common; + uint32_t RawData[11]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_INLINE_DATA_0 = 0x1, + DWORD_LENGTH_INLINE_DATA_1 = 0x9, + } DWORD_LENGTH; + typedef enum tagDATA_SIZE { + DATA_SIZE_DWORD = 0x0, + DATA_SIZE_QWORD = 0x1, + DATA_SIZE_OCTWORD = 0x2, + } DATA_SIZE; + typedef enum tagPOST_SYNC_OPERATION { + POST_SYNC_OPERATION_NO_POST_SYNC_OPERATION = 0x0, + POST_SYNC_OPERATION_POST_SYNC_OPERATION = 0x1, + } POST_SYNC_OPERATION; + typedef enum tagMEMORY_TYPE { + MEMORY_TYPE_PER_PROCESS_GRAPHICS_ADDRESS = 0x0, + MEMORY_TYPE_GLOBAL_GRAPHICS_ADDRESS = 0x1, + } MEMORY_TYPE; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_ATOMIC = 0x2f, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + typedef enum tagATOMIC_OPCODES { // patched + ATOMIC_4B_MOVE = 0x4, + ATOMIC_4B_INCREMENT = 0x5, + ATOMIC_4B_DECREMENT = 0x6, + ATOMIC_8B_MOVE = 0x24, + ATOMIC_8B_INCREMENT = 0x25, + ATOMIC_8B_DECREMENT = 0x26, + } ATOMIC_OPCODES; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_INLINE_DATA_0; + TheStructure.Common.DataSize = DATA_SIZE_DWORD; + TheStructure.Common.PostSyncOperation = POST_SYNC_OPERATION_NO_POST_SYNC_OPERATION; + TheStructure.Common.MemoryType = MEMORY_TYPE_PER_PROCESS_GRAPHICS_ADDRESS; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_ATOMIC; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_ATOMIC sInit() { + MI_ATOMIC state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 11); + return TheStructure.RawData[index]; + } + inline void setDwordLength(const DWORD_LENGTH value) { + TheStructure.Common.DwordLength = value; + } + inline DWORD_LENGTH getDwordLength() const { + return static_cast(TheStructure.Common.DwordLength); + } + inline void setAtomicOpcode(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xff); + TheStructure.Common.AtomicOpcode = value; + } + inline uint32_t getAtomicOpcode() const { + return TheStructure.Common.AtomicOpcode; + } + inline void setReturnDataControl(const bool value) { + TheStructure.Common.ReturnDataControl = value; + } + inline bool getReturnDataControl() const { + return TheStructure.Common.ReturnDataControl; + } + inline void setCsStall(const bool value) { + TheStructure.Common.CsStall = value; + } + inline bool getCsStall() const { + return TheStructure.Common.CsStall; + } + inline void setInlineData(const bool value) { + TheStructure.Common.InlineData = value; + } + inline bool getInlineData() const { + return TheStructure.Common.InlineData; + } + inline void setDataSize(const DATA_SIZE value) { + TheStructure.Common.DataSize = value; + } + inline DATA_SIZE getDataSize() const { + return static_cast(TheStructure.Common.DataSize); + } + inline void setPostSyncOperation(const POST_SYNC_OPERATION value) { + TheStructure.Common.PostSyncOperation = value; + } + inline POST_SYNC_OPERATION getPostSyncOperation() const { + return static_cast(TheStructure.Common.PostSyncOperation); + } + inline void setMemoryType(const MEMORY_TYPE value) { + TheStructure.Common.MemoryType = value; + } + inline MEMORY_TYPE getMemoryType() const { + return static_cast(TheStructure.Common.MemoryType); + } + inline void setWorkloadPartitionIdOffsetEnable(const bool value) { + TheStructure.Common.WorkloadPartitionIdOffsetEnable = value; + } + inline bool getWorkloadPartitionIdOffsetEnable() const { + return TheStructure.Common.WorkloadPartitionIdOffsetEnable; + } + typedef enum tagMEMORYADDRESS { + MEMORYADDRESS_BIT_SHIFT = 0x2, + MEMORYADDRESS_ALIGN_SIZE = 0x4, + } MEMORYADDRESS; + inline void setMemoryAddress(const uint64_t value) { + UNRECOVERABLE_IF(value > 0xffffffffffffffffL); + TheStructure.Common.MemoryAddress = value >> MEMORYADDRESS_BIT_SHIFT; + } + inline uint64_t getMemoryAddress() const { + return TheStructure.Common.MemoryAddress << MEMORYADDRESS_BIT_SHIFT; + } + inline void setOperand1DataDword0(const uint32_t value) { + TheStructure.Common.Operand1DataDword0 = value; + } + inline uint32_t getOperand1DataDword0() const { + return TheStructure.Common.Operand1DataDword0; + } + inline void setOperand2DataDword0(const uint32_t value) { + TheStructure.Common.Operand2DataDword0 = value; + } + inline uint32_t getOperand2DataDword0() const { + return TheStructure.Common.Operand2DataDword0; + } + inline void setOperand1DataDword1(const uint32_t value) { + TheStructure.Common.Operand1DataDword1 = value; + } + inline uint32_t getOperand1DataDword1() const { + return TheStructure.Common.Operand1DataDword1; + } + inline void setOperand2DataDword1(const uint32_t value) { + TheStructure.Common.Operand2DataDword1 = value; + } + inline uint32_t getOperand2DataDword1() const { + return TheStructure.Common.Operand2DataDword1; + } + inline void setOperand1DataDword2(const uint32_t value) { + TheStructure.Common.Operand1DataDword2 = value; + } + inline uint32_t getOperand1DataDword2() const { + return TheStructure.Common.Operand1DataDword2; + } + inline void setOperand2DataDword2(const uint32_t value) { + TheStructure.Common.Operand2DataDword2 = value; + } + inline uint32_t getOperand2DataDword2() const { + return TheStructure.Common.Operand2DataDword2; + } + inline void setOperand1DataDword3(const uint32_t value) { + TheStructure.Common.Operand1DataDword3 = value; + } + inline uint32_t getOperand1DataDword3() const { + return TheStructure.Common.Operand1DataDword3; + } + inline void setOperand2DataDword3(const uint32_t value) { + TheStructure.Common.Operand2DataDword3 = value; + } + inline uint32_t getOperand2DataDword3() const { + return TheStructure.Common.Operand2DataDword3; + } +} MI_ATOMIC; +STATIC_ASSERT(44 == sizeof(MI_ATOMIC)); + +typedef struct tagMI_BATCH_BUFFER_END { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t EndContext : BITFIELD_RANGE(0, 0); + uint32_t Reserved_1 : BITFIELD_RANGE(1, 14); + uint32_t PredicateEnable : BITFIELD_RANGE(15, 15); + uint32_t Reserved_16 : BITFIELD_RANGE(16, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + } Common; + uint32_t RawData[1]; + } TheStructure; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_BATCH_BUFFER_END = 0xa, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_BATCH_BUFFER_END; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_BATCH_BUFFER_END sInit() { + MI_BATCH_BUFFER_END state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 1); + return TheStructure.RawData[index]; + } + inline void setEndContext(const bool value) { + TheStructure.Common.EndContext = value; + } + inline bool getEndContext() const { + return TheStructure.Common.EndContext; + } + inline void setPredicateEnable(const bool value) { + TheStructure.Common.PredicateEnable = value; + } + inline bool getPredicateEnable() const { + return TheStructure.Common.PredicateEnable; + } +} MI_BATCH_BUFFER_END; +STATIC_ASSERT(4 == sizeof(MI_BATCH_BUFFER_END)); + +typedef struct tagMI_LOAD_REGISTER_IMM { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t ByteWriteDisables : BITFIELD_RANGE(8, 11); + uint32_t Reserved_12 : BITFIELD_RANGE(12, 16); + uint32_t MmioRemapEnable : BITFIELD_RANGE(17, 17); + uint32_t Reserved_18 : BITFIELD_RANGE(18, 18); + uint32_t AddCsMmioStartOffset : BITFIELD_RANGE(19, 19); + uint32_t Reserved_20 : BITFIELD_RANGE(20, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint64_t Reserved_32 : BITFIELD_RANGE(0, 1); + uint64_t RegisterOffset : BITFIELD_RANGE(2, 22); + uint64_t Reserved_55 : BITFIELD_RANGE(23, 31); + // DWORD 2 + uint64_t DataDword : BITFIELD_RANGE(32, 63); + } Common; + uint32_t RawData[3]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x1, + } DWORD_LENGTH; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_LOAD_REGISTER_IMM = 0x22, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_LOAD_REGISTER_IMM; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_LOAD_REGISTER_IMM sInit() { + MI_LOAD_REGISTER_IMM state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 3); + return TheStructure.RawData[index]; + } + inline void setByteWriteDisables(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xf); + TheStructure.Common.ByteWriteDisables = value; + } + inline uint32_t getByteWriteDisables() const { + return TheStructure.Common.ByteWriteDisables; + } + inline void setMmioRemapEnable(const bool value) { + TheStructure.Common.MmioRemapEnable = value; + } + inline bool getMmioRemapEnable() const { + return TheStructure.Common.MmioRemapEnable; + } + inline void setAddCsMmioStartOffset(const bool value) { + TheStructure.Common.AddCsMmioStartOffset = value; + } + inline bool getAddCsMmioStartOffset() const { + return TheStructure.Common.AddCsMmioStartOffset; + } + typedef enum tagREGISTEROFFSET { + REGISTEROFFSET_BIT_SHIFT = 0x2, + REGISTEROFFSET_ALIGN_SIZE = 0x4, + } REGISTEROFFSET; + inline void setRegisterOffset(const uint64_t value) { + UNRECOVERABLE_IF(value > 0x7fffffL); + TheStructure.Common.RegisterOffset = value >> REGISTEROFFSET_BIT_SHIFT; + } + inline uint64_t getRegisterOffset() const { + return TheStructure.Common.RegisterOffset << REGISTEROFFSET_BIT_SHIFT; + } + inline void setDataDword(const uint64_t value) { + TheStructure.Common.DataDword = value; + } + inline uint64_t getDataDword() const { + return TheStructure.Common.DataDword; + } +} MI_LOAD_REGISTER_IMM; +STATIC_ASSERT(12 == sizeof(MI_LOAD_REGISTER_IMM)); + +typedef struct tagMI_NOOP { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t IdentificationNumber : BITFIELD_RANGE(0, 21); + uint32_t IdentificationNumberRegisterWriteEnable : BITFIELD_RANGE(22, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + } Common; + uint32_t RawData[1]; + } TheStructure; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_NOOP = 0x0, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_NOOP; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_NOOP sInit() { + MI_NOOP state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 1); + return TheStructure.RawData[index]; + } + inline void setIdentificationNumber(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3fffff); + TheStructure.Common.IdentificationNumber = value; + } + inline uint32_t getIdentificationNumber() const { + return TheStructure.Common.IdentificationNumber; + } + inline void setIdentificationNumberRegisterWriteEnable(const bool value) { + TheStructure.Common.IdentificationNumberRegisterWriteEnable = value; + } + inline bool getIdentificationNumberRegisterWriteEnable() const { + return TheStructure.Common.IdentificationNumberRegisterWriteEnable; + } +} MI_NOOP; +STATIC_ASSERT(4 == sizeof(MI_NOOP)); + +typedef struct tagRENDER_SURFACE_STATE { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t CubeFaceEnablePositiveZ : BITFIELD_RANGE(0, 0); + uint32_t CubeFaceEnableNegativeZ : BITFIELD_RANGE(1, 1); + uint32_t CubeFaceEnablePositiveY : BITFIELD_RANGE(2, 2); + uint32_t CubeFaceEnableNegativeY : BITFIELD_RANGE(3, 3); + uint32_t CubeFaceEnablePositiveX : BITFIELD_RANGE(4, 4); + uint32_t CubeFaceEnableNegativeX : BITFIELD_RANGE(5, 5); + uint32_t MediaBoundaryPixelMode : BITFIELD_RANGE(6, 7); + uint32_t RenderCacheReadWriteMode : BITFIELD_RANGE(8, 8); + uint32_t SamplerL2OutOfOrderModeDisable : BITFIELD_RANGE(9, 9); + uint32_t VerticalLineStrideOffset : BITFIELD_RANGE(10, 10); + uint32_t VerticalLineStride : BITFIELD_RANGE(11, 11); + uint32_t TileMode : BITFIELD_RANGE(12, 13); + uint32_t SurfaceHorizontalAlignment : BITFIELD_RANGE(14, 15); + uint32_t SurfaceVerticalAlignment : BITFIELD_RANGE(16, 17); + uint32_t SurfaceFormat : BITFIELD_RANGE(18, 26); + uint32_t AstcEnable : BITFIELD_RANGE(27, 27); + uint32_t SurfaceArray : BITFIELD_RANGE(28, 28); + uint32_t SurfaceType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint32_t SurfaceQpitch : BITFIELD_RANGE(0, 14); + uint32_t SampleTapDiscardDisable : BITFIELD_RANGE(15, 15); + uint32_t Reserved_48 : BITFIELD_RANGE(16, 16); + uint32_t DoubleFetchDisable : BITFIELD_RANGE(17, 17); + uint32_t CornerTexelMode : BITFIELD_RANGE(18, 18); + uint32_t BaseMipLevel : BITFIELD_RANGE(19, 23); + uint32_t MemoryObjectControlStateReserved_56 : BITFIELD_RANGE(24, 24); + uint32_t MemoryObjectControlStateIndexToMocsTables : BITFIELD_RANGE(25, 30); + uint32_t Reserved_63 : BITFIELD_RANGE(31, 31); + // DWORD 2 + uint32_t Width : BITFIELD_RANGE(0, 13); + uint32_t Reserved_78 : BITFIELD_RANGE(14, 15); + uint32_t Height : BITFIELD_RANGE(16, 29); + uint32_t Reserved_94 : BITFIELD_RANGE(30, 30); + uint32_t DepthStencilResource : BITFIELD_RANGE(31, 31); + // DWORD 3 + uint32_t SurfacePitch : BITFIELD_RANGE(0, 17); + uint32_t NullProbingEnable : BITFIELD_RANGE(18, 18); + uint32_t Reserved_115 : BITFIELD_RANGE(19, 20); + uint32_t Depth : BITFIELD_RANGE(21, 31); + // DWORD 4 + uint32_t MultisamplePositionPaletteIndex : BITFIELD_RANGE(0, 2); + uint32_t NumberOfMultisamples : BITFIELD_RANGE(3, 5); + uint32_t MultisampledSurfaceStorageFormat : BITFIELD_RANGE(6, 6); + uint32_t RenderTargetViewExtent : BITFIELD_RANGE(7, 17); + uint32_t MinimumArrayElement : BITFIELD_RANGE(18, 28); + uint32_t RenderTargetAndSampleUnormRotation : BITFIELD_RANGE(29, 30); + uint32_t Reserved_159 : BITFIELD_RANGE(31, 31); + // DWORD 5 + uint32_t MipCountLod : BITFIELD_RANGE(0, 3); + uint32_t SurfaceMinLod : BITFIELD_RANGE(4, 7); + uint32_t MipTailStartLod : BITFIELD_RANGE(8, 11); + uint32_t Reserved_172 : BITFIELD_RANGE(12, 13); + uint32_t CoherencyType : BITFIELD_RANGE(14, 15); + uint32_t L1CachePolicyL1CacheControl : BITFIELD_RANGE(16, 18); + uint32_t Reserved_179 : BITFIELD_RANGE(19, 19); + uint32_t EwaDisableForCube : BITFIELD_RANGE(20, 20); + uint32_t YOffset : BITFIELD_RANGE(21, 23); + uint32_t Reserved_184 : BITFIELD_RANGE(24, 24); + uint32_t XOffset : BITFIELD_RANGE(25, 31); + // DWORD 6 + uint32_t Reserved_192 : BITFIELD_RANGE(0, 14); + uint32_t YuvInterpolationEnable : BITFIELD_RANGE(15, 15); + uint32_t Reserved_208 : BITFIELD_RANGE(16, 31); + // DWORD 7 + uint32_t ResourceMinLod : BITFIELD_RANGE(0, 11); + uint32_t Reserved_236 : BITFIELD_RANGE(12, 13); + uint32_t DisableSupportForMultiGpuAtomics : BITFIELD_RANGE(14, 14); + uint32_t DisableSupportForMultiGpuPartialWrites : BITFIELD_RANGE(15, 15); + uint32_t ShaderChannelSelectAlpha : BITFIELD_RANGE(16, 18); + uint32_t ShaderChannelSelectBlue : BITFIELD_RANGE(19, 21); + uint32_t ShaderChannelSelectGreen : BITFIELD_RANGE(22, 24); + uint32_t ShaderChannelSelectRed : BITFIELD_RANGE(25, 27); + uint32_t Reserved_252 : BITFIELD_RANGE(28, 29); + uint32_t MemoryCompressionEnable : BITFIELD_RANGE(30, 30); + uint32_t MemoryCompressionMode : BITFIELD_RANGE(31, 31); + // DWORD 8 + uint64_t SurfaceBaseAddress; + // DWORD 10 + uint64_t QuiltWidth : BITFIELD_RANGE(0, 4); + uint64_t QuiltHeight : BITFIELD_RANGE(5, 9); + uint64_t ClearValueAddressEnable : BITFIELD_RANGE(10, 10); + uint64_t ProceduralTexture : BITFIELD_RANGE(11, 11); + uint64_t Reserved_332 : BITFIELD_RANGE(12, 63); + // DWORD 12 + uint32_t CompressionFormat : BITFIELD_RANGE(0, 4); + uint32_t Reserved_389 : BITFIELD_RANGE(5, 5); + uint32_t ClearAddressLow : BITFIELD_RANGE(6, 31); + // DWORD 13 + uint32_t ClearAddressHigh : BITFIELD_RANGE(0, 15); + uint32_t Reserved_432 : BITFIELD_RANGE(16, 31); + // DWORD 14 + uint32_t Reserved_448; + // DWORD 15 + uint32_t Reserved_480; + } Common; + struct tag_SurfaceFormatIsPlanar { + // DWORD 0 + uint32_t Reserved_0; + // DWORD 1 + uint32_t Reserved_32; + // DWORD 2 + uint32_t Reserved_64; + // DWORD 3 + uint32_t Reserved_96; + // DWORD 4 + uint32_t Reserved_128; + // DWORD 5 + uint32_t Reserved_160; + // DWORD 6 + uint32_t YOffsetForUOrUvPlane : BITFIELD_RANGE(0, 13); + uint32_t Reserved_206 : BITFIELD_RANGE(14, 15); + uint32_t XOffsetForUOrUvPlane : BITFIELD_RANGE(16, 29); + uint32_t HalfPitchForChroma : BITFIELD_RANGE(30, 30); + uint32_t SeparateUvPlaneEnable : BITFIELD_RANGE(31, 31); + // DWORD 7 + uint32_t Reserved_224; + // DWORD 8 + uint64_t Reserved_256; + // DWORD 10 + uint64_t Reserved_320 : BITFIELD_RANGE(0, 11); + uint64_t Reserved_332 : BITFIELD_RANGE(12, 31); + // DWORD 11 + uint64_t YOffsetForVPlane : BITFIELD_RANGE(32, 45); + uint64_t Reserved_366 : BITFIELD_RANGE(46, 47); + uint64_t XOffsetForVPlane : BITFIELD_RANGE(48, 61); + uint64_t Reserved_382 : BITFIELD_RANGE(62, 63); + // DWORD 12 + uint32_t Reserved_384; + // DWORD 13 + uint32_t Reserved_416; + // DWORD 14 + uint32_t Reserved_448; + // DWORD 15 + uint32_t Reserved_480; + } _SurfaceFormatIsPlanar; + struct tag_SurfaceFormatIsnotPlanar { + // DWORD 0 + uint32_t Reserved_0; + // DWORD 1 + uint32_t Reserved_32; + // DWORD 2 + uint32_t Reserved_64; + // DWORD 3 + uint32_t Reserved_96; + // DWORD 4 + uint32_t Reserved_128; + // DWORD 5 + uint32_t Reserved_160; + // DWORD 6 + uint32_t AuxiliarySurfaceMode : BITFIELD_RANGE(0, 2); + uint32_t AuxiliarySurfacePitch : BITFIELD_RANGE(3, 12); + uint32_t Reserved_205 : BITFIELD_RANGE(13, 13); + uint32_t Reserved_206 : BITFIELD_RANGE(14, 15); + uint32_t AuxiliarySurfaceQpitch : BITFIELD_RANGE(16, 30); + uint32_t Reserved_223 : BITFIELD_RANGE(31, 31); + // DWORD 7 + uint32_t Reserved_224; + // DWORD 8 + uint64_t Reserved_256; + // DWORD 10 + uint64_t Reserved_320; + // DWORD 12 + uint32_t Reserved_384; + // DWORD 13 + uint32_t Reserved_416; + // DWORD 14 + uint32_t Reserved_448; + // DWORD 15 + uint32_t Reserved_480; + } _SurfaceFormatIsnotPlanar; + struct tag_SurfaceFormatIsnotPlanarAndMemoryCompressionEnableIs0 { + // DWORD 0 + uint32_t Reserved_0; + // DWORD 1 + uint32_t Reserved_32; + // DWORD 2 + uint32_t Reserved_64; + // DWORD 3 + uint32_t Reserved_96; + // DWORD 4 + uint32_t Reserved_128; + // DWORD 5 + uint32_t Reserved_160; + // DWORD 6 + uint32_t Reserved_192; + // DWORD 7 + uint32_t Reserved_224; + // DWORD 8 + uint64_t Reserved_256; + // DWORD 10 + uint64_t Reserved_320 : BITFIELD_RANGE(0, 11); + uint64_t AuxiliarySurfaceBaseAddress : BITFIELD_RANGE(12, 63); + // DWORD 12 + uint32_t Reserved_384; + // DWORD 13 + uint32_t Reserved_416; + // DWORD 14 + uint32_t Reserved_448; + // DWORD 15 + uint32_t Reserved_480; + } _SurfaceFormatIsnotPlanarAndMemoryCompressionEnableIs0; + uint32_t RawData[16]; + } TheStructure; + typedef enum tagMEDIA_BOUNDARY_PIXEL_MODE { + MEDIA_BOUNDARY_PIXEL_MODE_NORMAL_MODE = 0x0, + MEDIA_BOUNDARY_PIXEL_MODE_PROGRESSIVE_FRAME = 0x2, + MEDIA_BOUNDARY_PIXEL_MODE_INTERLACED_FRAME = 0x3, + } MEDIA_BOUNDARY_PIXEL_MODE; + typedef enum tagRENDER_CACHE_READ_WRITE_MODE { + RENDER_CACHE_READ_WRITE_MODE_WRITE_ONLY_CACHE = 0x0, + RENDER_CACHE_READ_WRITE_MODE_READ_WRITE_CACHE = 0x1, + } RENDER_CACHE_READ_WRITE_MODE; + typedef enum tagTILE_MODE { + TILE_MODE_LINEAR = 0x0, + TILE_MODE_TILE64 = 0x1, + TILE_MODE_XMAJOR = 0x2, + TILE_MODE_YMAJOR = 0x3, + } TILE_MODE; + typedef enum tagSURFACE_HORIZONTAL_ALIGNMENT { + SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_4 = 0x1, + SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_8 = 0x2, + SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_16 = 0x3, + } SURFACE_HORIZONTAL_ALIGNMENT; + typedef enum tagSURFACE_VERTICAL_ALIGNMENT { + SURFACE_VERTICAL_ALIGNMENT_VALIGN_4 = 0x1, + SURFACE_VERTICAL_ALIGNMENT_VALIGN_8 = 0x2, + SURFACE_VERTICAL_ALIGNMENT_VALIGN_16 = 0x3, + } SURFACE_VERTICAL_ALIGNMENT; + typedef enum tagSURFACE_FORMAT { + SURFACE_FORMAT_R32G32B32A32_FLOAT = 0x0, + SURFACE_FORMAT_R32G32B32A32_SINT = 0x1, + SURFACE_FORMAT_R32G32B32A32_UINT = 0x2, + SURFACE_FORMAT_R32G32B32A32_UNORM = 0x3, + SURFACE_FORMAT_R32G32B32A32_SNORM = 0x4, + SURFACE_FORMAT_R64G64_FLOAT = 0x5, + SURFACE_FORMAT_R32G32B32X32_FLOAT = 0x6, + SURFACE_FORMAT_R32G32B32A32_SSCALED = 0x7, + SURFACE_FORMAT_R32G32B32A32_USCALED = 0x8, + SURFACE_FORMAT_R32G32B32A32_SFIXED = 0x20, + SURFACE_FORMAT_R64G64_PASSTHRU = 0x21, + SURFACE_FORMAT_R32G32B32_FLOAT = 0x40, + SURFACE_FORMAT_R32G32B32_SINT = 0x41, + SURFACE_FORMAT_R32G32B32_UINT = 0x42, + SURFACE_FORMAT_R32G32B32_UNORM = 0x43, + SURFACE_FORMAT_R32G32B32_SNORM = 0x44, + SURFACE_FORMAT_R32G32B32_SSCALED = 0x45, + SURFACE_FORMAT_R32G32B32_USCALED = 0x46, + SURFACE_FORMAT_R32G32B32_SFIXED = 0x50, + SURFACE_FORMAT_R16G16B16A16_UNORM = 0x80, + SURFACE_FORMAT_R16G16B16A16_SNORM = 0x81, + SURFACE_FORMAT_R16G16B16A16_SINT = 0x82, + SURFACE_FORMAT_R16G16B16A16_UINT = 0x83, + SURFACE_FORMAT_R16G16B16A16_FLOAT = 0x84, + SURFACE_FORMAT_R32G32_FLOAT = 0x85, + SURFACE_FORMAT_R32G32_SINT = 0x86, + SURFACE_FORMAT_R32G32_UINT = 0x87, + SURFACE_FORMAT_R32_FLOAT_X8X24_TYPELESS = 0x88, + SURFACE_FORMAT_X32_TYPELESS_G8X24_UINT = 0x89, + SURFACE_FORMAT_L32A32_FLOAT = 0x8a, + SURFACE_FORMAT_R32G32_UNORM = 0x8b, + SURFACE_FORMAT_R32G32_SNORM = 0x8c, + SURFACE_FORMAT_R64_FLOAT = 0x8d, + SURFACE_FORMAT_R16G16B16X16_UNORM = 0x8e, + SURFACE_FORMAT_R16G16B16X16_FLOAT = 0x8f, + SURFACE_FORMAT_A32X32_FLOAT = 0x90, + SURFACE_FORMAT_L32X32_FLOAT = 0x91, + SURFACE_FORMAT_I32X32_FLOAT = 0x92, + SURFACE_FORMAT_R16G16B16A16_SSCALED = 0x93, + SURFACE_FORMAT_R16G16B16A16_USCALED = 0x94, + SURFACE_FORMAT_R32G32_SSCALED = 0x95, + SURFACE_FORMAT_R32G32_USCALED = 0x96, + SURFACE_FORMAT_R32G32_SFIXED = 0xa0, + SURFACE_FORMAT_R64_PASSTHRU = 0xa1, + SURFACE_FORMAT_B8G8R8A8_UNORM = 0xc0, + SURFACE_FORMAT_B8G8R8A8_UNORM_SRGB = 0xc1, + SURFACE_FORMAT_R10G10B10A2_UNORM = 0xc2, + SURFACE_FORMAT_R10G10B10A2_UNORM_SRGB = 0xc3, + SURFACE_FORMAT_R10G10B10A2_UINT = 0xc4, + SURFACE_FORMAT_R10G10B10_SNORM_A2_UNORM = 0xc5, + SURFACE_FORMAT_R8G8B8A8_UNORM = 0xc7, + SURFACE_FORMAT_R8G8B8A8_UNORM_SRGB = 0xc8, + SURFACE_FORMAT_R8G8B8A8_SNORM = 0xc9, + SURFACE_FORMAT_R8G8B8A8_SINT = 0xca, + SURFACE_FORMAT_R8G8B8A8_UINT = 0xcb, + SURFACE_FORMAT_R16G16_UNORM = 0xcc, + SURFACE_FORMAT_R16G16_SNORM = 0xcd, + SURFACE_FORMAT_R16G16_SINT = 0xce, + SURFACE_FORMAT_R16G16_UINT = 0xcf, + SURFACE_FORMAT_R16G16_FLOAT = 0xd0, + SURFACE_FORMAT_B10G10R10A2_UNORM = 0xd1, + SURFACE_FORMAT_B10G10R10A2_UNORM_SRGB = 0xd2, + SURFACE_FORMAT_R11G11B10_FLOAT = 0xd3, + SURFACE_FORMAT_R10G10B10_FLOAT_A2_UNORM = 0xd5, + SURFACE_FORMAT_R32_SINT = 0xd6, + SURFACE_FORMAT_R32_UINT = 0xd7, + SURFACE_FORMAT_R32_FLOAT = 0xd8, + SURFACE_FORMAT_R24_UNORM_X8_TYPELESS = 0xd9, + SURFACE_FORMAT_X24_TYPELESS_G8_UINT = 0xda, + SURFACE_FORMAT_L32_UNORM = 0xdd, + SURFACE_FORMAT_A32_UNORM = 0xde, + SURFACE_FORMAT_L16A16_UNORM = 0xdf, + SURFACE_FORMAT_I24X8_UNORM = 0xe0, + SURFACE_FORMAT_L24X8_UNORM = 0xe1, + SURFACE_FORMAT_A24X8_UNORM = 0xe2, + SURFACE_FORMAT_I32_FLOAT = 0xe3, + SURFACE_FORMAT_L32_FLOAT = 0xe4, + SURFACE_FORMAT_A32_FLOAT = 0xe5, + SURFACE_FORMAT_X8B8_UNORM_G8R8_SNORM = 0xe6, + SURFACE_FORMAT_A8X8_UNORM_G8R8_SNORM = 0xe7, + SURFACE_FORMAT_B8X8_UNORM_G8R8_SNORM = 0xe8, + SURFACE_FORMAT_B8G8R8X8_UNORM = 0xe9, + SURFACE_FORMAT_B8G8R8X8_UNORM_SRGB = 0xea, + SURFACE_FORMAT_R8G8B8X8_UNORM = 0xeb, + SURFACE_FORMAT_R8G8B8X8_UNORM_SRGB = 0xec, + SURFACE_FORMAT_R9G9B9E5_SHAREDEXP = 0xed, + SURFACE_FORMAT_B10G10R10X2_UNORM = 0xee, + SURFACE_FORMAT_L16A16_FLOAT = 0xf0, + SURFACE_FORMAT_R32_UNORM = 0xf1, + SURFACE_FORMAT_R32_SNORM = 0xf2, + SURFACE_FORMAT_R10G10B10X2_USCALED = 0xf3, + SURFACE_FORMAT_R8G8B8A8_SSCALED = 0xf4, + SURFACE_FORMAT_R8G8B8A8_USCALED = 0xf5, + SURFACE_FORMAT_R16G16_SSCALED = 0xf6, + SURFACE_FORMAT_R16G16_USCALED = 0xf7, + SURFACE_FORMAT_R32_SSCALED = 0xf8, + SURFACE_FORMAT_R32_USCALED = 0xf9, + SURFACE_FORMAT_B5G6R5_UNORM = 0x100, + SURFACE_FORMAT_B5G6R5_UNORM_SRGB = 0x101, + SURFACE_FORMAT_B5G5R5A1_UNORM = 0x102, + SURFACE_FORMAT_B5G5R5A1_UNORM_SRGB = 0x103, + SURFACE_FORMAT_B4G4R4A4_UNORM = 0x104, + SURFACE_FORMAT_B4G4R4A4_UNORM_SRGB = 0x105, + SURFACE_FORMAT_R8G8_UNORM = 0x106, + SURFACE_FORMAT_R8G8_SNORM = 0x107, + SURFACE_FORMAT_R8G8_SINT = 0x108, + SURFACE_FORMAT_R8G8_UINT = 0x109, + SURFACE_FORMAT_R16_UNORM = 0x10a, + SURFACE_FORMAT_R16_SNORM = 0x10b, + SURFACE_FORMAT_R16_SINT = 0x10c, + SURFACE_FORMAT_R16_UINT = 0x10d, + SURFACE_FORMAT_R16_FLOAT = 0x10e, + SURFACE_FORMAT_A8P8_UNORM_PALETTE0 = 0x10f, + SURFACE_FORMAT_A8P8_UNORM_PALETTE1 = 0x110, + SURFACE_FORMAT_I16_UNORM = 0x111, + SURFACE_FORMAT_L16_UNORM = 0x112, + SURFACE_FORMAT_A16_UNORM = 0x113, + SURFACE_FORMAT_L8A8_UNORM = 0x114, + SURFACE_FORMAT_I16_FLOAT = 0x115, + SURFACE_FORMAT_L16_FLOAT = 0x116, + SURFACE_FORMAT_A16_FLOAT = 0x117, + SURFACE_FORMAT_L8A8_UNORM_SRGB = 0x118, + SURFACE_FORMAT_R5G5_SNORM_B6_UNORM = 0x119, + SURFACE_FORMAT_B5G5R5X1_UNORM = 0x11a, + SURFACE_FORMAT_B5G5R5X1_UNORM_SRGB = 0x11b, + SURFACE_FORMAT_R8G8_SSCALED = 0x11c, + SURFACE_FORMAT_R8G8_USCALED = 0x11d, + SURFACE_FORMAT_R16_SSCALED = 0x11e, + SURFACE_FORMAT_R16_USCALED = 0x11f, + SURFACE_FORMAT_P8A8_UNORM_PALETTE0 = 0x122, + SURFACE_FORMAT_P8A8_UNORM_PALETTE1 = 0x123, + SURFACE_FORMAT_A1B5G5R5_UNORM = 0x124, + SURFACE_FORMAT_A4B4G4R4_UNORM = 0x125, + SURFACE_FORMAT_L8A8_UINT = 0x126, + SURFACE_FORMAT_L8A8_SINT = 0x127, + SURFACE_FORMAT_R8_UNORM = 0x140, + SURFACE_FORMAT_R8_SNORM = 0x141, + SURFACE_FORMAT_R8_SINT = 0x142, + SURFACE_FORMAT_R8_UINT = 0x143, + SURFACE_FORMAT_A8_UNORM = 0x144, + SURFACE_FORMAT_I8_UNORM = 0x145, + SURFACE_FORMAT_L8_UNORM = 0x146, + SURFACE_FORMAT_P4A4_UNORM_PALETTE0 = 0x147, + SURFACE_FORMAT_A4P4_UNORM_PALETTE0 = 0x148, + SURFACE_FORMAT_R8_SSCALED = 0x149, + SURFACE_FORMAT_R8_USCALED = 0x14a, + SURFACE_FORMAT_P8_UNORM_PALETTE0 = 0x14b, + SURFACE_FORMAT_L8_UNORM_SRGB = 0x14c, + SURFACE_FORMAT_P8_UNORM_PALETTE1 = 0x14d, + SURFACE_FORMAT_P4A4_UNORM_PALETTE1 = 0x14e, + SURFACE_FORMAT_A4P4_UNORM_PALETTE1 = 0x14f, + SURFACE_FORMAT_Y8_UNORM = 0x150, + SURFACE_FORMAT_L8_UINT = 0x152, + SURFACE_FORMAT_L8_SINT = 0x153, + SURFACE_FORMAT_I8_UINT = 0x154, + SURFACE_FORMAT_I8_SINT = 0x155, + SURFACE_FORMAT_DXT1_RGB_SRGB = 0x180, + SURFACE_FORMAT_R1_UNORM = 0x181, + SURFACE_FORMAT_YCRCB_NORMAL = 0x182, + SURFACE_FORMAT_YCRCB_SWAPUVY = 0x183, + SURFACE_FORMAT_P2_UNORM_PALETTE0 = 0x184, + SURFACE_FORMAT_P2_UNORM_PALETTE1 = 0x185, + SURFACE_FORMAT_BC1_UNORM = 0x186, + SURFACE_FORMAT_BC2_UNORM = 0x187, + SURFACE_FORMAT_BC3_UNORM = 0x188, + SURFACE_FORMAT_BC4_UNORM = 0x189, + SURFACE_FORMAT_BC5_UNORM = 0x18a, + SURFACE_FORMAT_BC1_UNORM_SRGB = 0x18b, + SURFACE_FORMAT_BC2_UNORM_SRGB = 0x18c, + SURFACE_FORMAT_BC3_UNORM_SRGB = 0x18d, + SURFACE_FORMAT_MONO8 = 0x18e, + SURFACE_FORMAT_YCRCB_SWAPUV = 0x18f, + SURFACE_FORMAT_YCRCB_SWAPY = 0x190, + SURFACE_FORMAT_DXT1_RGB = 0x191, + SURFACE_FORMAT_R8G8B8_UNORM = 0x193, + SURFACE_FORMAT_R8G8B8_SNORM = 0x194, + SURFACE_FORMAT_R8G8B8_SSCALED = 0x195, + SURFACE_FORMAT_R8G8B8_USCALED = 0x196, + SURFACE_FORMAT_R64G64B64A64_FLOAT = 0x197, + SURFACE_FORMAT_R64G64B64_FLOAT = 0x198, + SURFACE_FORMAT_BC4_SNORM = 0x199, + SURFACE_FORMAT_BC5_SNORM = 0x19a, + SURFACE_FORMAT_R16G16B16_FLOAT = 0x19b, + SURFACE_FORMAT_R16G16B16_UNORM = 0x19c, + SURFACE_FORMAT_R16G16B16_SNORM = 0x19d, + SURFACE_FORMAT_R16G16B16_SSCALED = 0x19e, + SURFACE_FORMAT_R16G16B16_USCALED = 0x19f, + SURFACE_FORMAT_BC6H_SF16 = 0x1a1, + SURFACE_FORMAT_BC7_UNORM = 0x1a2, + SURFACE_FORMAT_BC7_UNORM_SRGB = 0x1a3, + SURFACE_FORMAT_BC6H_UF16 = 0x1a4, + SURFACE_FORMAT_PLANAR_420_8 = 0x1a5, + SURFACE_FORMAT_PLANAR_420_16 = 0x1a6, + SURFACE_FORMAT_R8G8B8_UNORM_SRGB = 0x1a8, + SURFACE_FORMAT_ETC1_RGB8 = 0x1a9, + SURFACE_FORMAT_ETC2_RGB8 = 0x1aa, + SURFACE_FORMAT_EAC_R11 = 0x1ab, + SURFACE_FORMAT_EAC_RG11 = 0x1ac, + SURFACE_FORMAT_EAC_SIGNED_R11 = 0x1ad, + SURFACE_FORMAT_EAC_SIGNED_RG11 = 0x1ae, + SURFACE_FORMAT_ETC2_SRGB8 = 0x1af, + SURFACE_FORMAT_R16G16B16_UINT = 0x1b0, + SURFACE_FORMAT_R16G16B16_SINT = 0x1b1, + SURFACE_FORMAT_R32_SFIXED = 0x1b2, + SURFACE_FORMAT_R10G10B10A2_SNORM = 0x1b3, + SURFACE_FORMAT_R10G10B10A2_USCALED = 0x1b4, + SURFACE_FORMAT_R10G10B10A2_SSCALED = 0x1b5, + SURFACE_FORMAT_R10G10B10A2_SINT = 0x1b6, + SURFACE_FORMAT_B10G10R10A2_SNORM = 0x1b7, + SURFACE_FORMAT_B10G10R10A2_USCALED = 0x1b8, + SURFACE_FORMAT_B10G10R10A2_SSCALED = 0x1b9, + SURFACE_FORMAT_B10G10R10A2_UINT = 0x1ba, + SURFACE_FORMAT_B10G10R10A2_SINT = 0x1bb, + SURFACE_FORMAT_R64G64B64A64_PASSTHRU = 0x1bc, + SURFACE_FORMAT_R64G64B64_PASSTHRU = 0x1bd, + SURFACE_FORMAT_ETC2_RGB8_PTA = 0x1c0, + SURFACE_FORMAT_ETC2_SRGB8_PTA = 0x1c1, + SURFACE_FORMAT_ETC2_EAC_RGBA8 = 0x1c2, + SURFACE_FORMAT_ETC2_EAC_SRGB8_A8 = 0x1c3, + SURFACE_FORMAT_R8G8B8_UINT = 0x1c8, + SURFACE_FORMAT_R8G8B8_SINT = 0x1c9, + SURFACE_FORMAT_RAW = 0x1ff, + } SURFACE_FORMAT; + typedef enum tagSURFACE_TYPE { + SURFACE_TYPE_SURFTYPE_1D = 0x0, + SURFACE_TYPE_SURFTYPE_2D = 0x1, + SURFACE_TYPE_SURFTYPE_3D = 0x2, + SURFACE_TYPE_SURFTYPE_CUBE = 0x3, + SURFACE_TYPE_SURFTYPE_BUFFER = 0x4, + SURFACE_TYPE_SURFTYPE_SCRATCH = 0x6, + SURFACE_TYPE_SURFTYPE_NULL = 0x7, + } SURFACE_TYPE; + typedef enum tagSAMPLE_TAP_DISCARD_DISABLE { + SAMPLE_TAP_DISCARD_DISABLE_DISABLE = 0x0, + SAMPLE_TAP_DISCARD_DISABLE_ENABLE = 0x1, + } SAMPLE_TAP_DISCARD_DISABLE; + typedef enum tagNULL_PROBING_ENABLE { + NULL_PROBING_ENABLE_DISABLE = 0x0, + NULL_PROBING_ENABLE_ENABLE = 0x1, + } NULL_PROBING_ENABLE; + typedef enum tagNUMBER_OF_MULTISAMPLES { + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_1 = 0x0, + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_2 = 0x1, + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_4 = 0x2, + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_8 = 0x3, + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_16 = 0x4, + } NUMBER_OF_MULTISAMPLES; + typedef enum tagMULTISAMPLED_SURFACE_STORAGE_FORMAT { + MULTISAMPLED_SURFACE_STORAGE_FORMAT_MSS = 0x0, + MULTISAMPLED_SURFACE_STORAGE_FORMAT_DEPTH_STENCIL = 0x1, + } MULTISAMPLED_SURFACE_STORAGE_FORMAT; + typedef enum tagRENDER_TARGET_AND_SAMPLE_UNORM_ROTATION { + RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_0DEG = 0x0, + RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_90DEG = 0x1, + RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_180DEG = 0x2, + RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_270DEG = 0x3, + } RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION; + typedef enum tagCOHERENCY_TYPE { + COHERENCY_TYPE_GPU_COHERENT = 0x0, + COHERENCY_TYPE_IA_COHERENT = 0x1, + } COHERENCY_TYPE; + typedef enum tagL1_CACHE_POLICY { + L1_CACHE_POLICY_WBP = 0x0, + L1_CACHE_POLICY_UC = 0x1, + L1_CACHE_POLICY_WB = 0x2, + L1_CACHE_POLICY_WT = 0x3, + L1_CACHE_POLICY_WS = 0x4, + } L1_CACHE_POLICY; + typedef enum tagAUXILIARY_SURFACE_MODE { + AUXILIARY_SURFACE_MODE_AUX_NONE = 0x0, + AUXILIARY_SURFACE_MODE_AUX_CCS_D = 0x1, + AUXILIARY_SURFACE_MODE_AUX_APPEND = 0x2, + AUXILIARY_SURFACE_MODE_AUX_MCS_LCE = 0x4, + AUXILIARY_SURFACE_MODE_AUX_CCS_E = 0x5, + } AUXILIARY_SURFACE_MODE; + typedef enum tagHALF_PITCH_FOR_CHROMA { + HALF_PITCH_FOR_CHROMA_DISABLE = 0x0, + HALF_PITCH_FOR_CHROMA_ENABLE = 0x1, + } HALF_PITCH_FOR_CHROMA; + typedef enum tagSHADER_CHANNEL_SELECT { + SHADER_CHANNEL_SELECT_ZERO = 0x0, + SHADER_CHANNEL_SELECT_ONE = 0x1, + SHADER_CHANNEL_SELECT_RED = 0x4, + SHADER_CHANNEL_SELECT_GREEN = 0x5, + SHADER_CHANNEL_SELECT_BLUE = 0x6, + SHADER_CHANNEL_SELECT_ALPHA = 0x7, + } SHADER_CHANNEL_SELECT; + typedef enum tagMEMORY_COMPRESSION_MODE { + MEMORY_COMPRESSION_MODE_HORIZONTAL = 0x0, + } MEMORY_COMPRESSION_MODE; + typedef enum tagCOMPRESSION_FORMAT { + COMPRESSION_FORMAT_RGBA16_FLOAT = 0x1, + COMPRESSION_FORMAT_Y210 = 0x2, + COMPRESSION_FORMAT_YUY2 = 0x3, + COMPRESSION_FORMAT_Y410_1010102 = 0x4, + COMPRESSION_FORMAT_Y216 = 0x5, + COMPRESSION_FORMAT_Y416 = 0x6, + COMPRESSION_FORMAT_P010 = 0x7, + COMPRESSION_FORMAT_P016 = 0x8, + COMPRESSION_FORMAT_AYUV = 0x9, + COMPRESSION_FORMAT_ARGB_8B = 0xa, + COMPRESSION_FORMAT_YCRCB_SWAPY = 0xb, + COMPRESSION_FORMAT_YCRCB_SWAPUV = 0xc, + COMPRESSION_FORMAT_YCRCB_SWAPUVY = 0xd, + COMPRESSION_FORMAT_RGB_10B = 0xe, + COMPRESSION_FORMAT_NV21NV12 = 0xf, + } COMPRESSION_FORMAT; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.MediaBoundaryPixelMode = MEDIA_BOUNDARY_PIXEL_MODE_NORMAL_MODE; + TheStructure.Common.RenderCacheReadWriteMode = RENDER_CACHE_READ_WRITE_MODE_WRITE_ONLY_CACHE; + TheStructure.Common.TileMode = TILE_MODE_LINEAR; + TheStructure.Common.SurfaceHorizontalAlignment = SURFACE_HORIZONTAL_ALIGNMENT_HALIGN_16; + TheStructure.Common.SurfaceVerticalAlignment = SURFACE_VERTICAL_ALIGNMENT_VALIGN_4; + TheStructure.Common.SurfaceType = SURFACE_TYPE_SURFTYPE_1D; + TheStructure.Common.SampleTapDiscardDisable = SAMPLE_TAP_DISCARD_DISABLE_DISABLE; + TheStructure.Common.NullProbingEnable = NULL_PROBING_ENABLE_DISABLE; + TheStructure.Common.NumberOfMultisamples = NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_1; + TheStructure.Common.MultisampledSurfaceStorageFormat = MULTISAMPLED_SURFACE_STORAGE_FORMAT_MSS; + TheStructure.Common.RenderTargetAndSampleUnormRotation = RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_0DEG; + TheStructure.Common.CoherencyType = COHERENCY_TYPE_GPU_COHERENT; + TheStructure.Common.L1CachePolicyL1CacheControl = L1_CACHE_POLICY_WBP; + TheStructure.Common.MemoryCompressionMode = MEMORY_COMPRESSION_MODE_HORIZONTAL; + TheStructure._SurfaceFormatIsPlanar.HalfPitchForChroma = HALF_PITCH_FOR_CHROMA_DISABLE; + TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceMode = AUXILIARY_SURFACE_MODE_AUX_NONE; + TheStructure.Common.DisableSupportForMultiGpuAtomics = 1; + TheStructure.Common.DisableSupportForMultiGpuPartialWrites = 1; + } + static tagRENDER_SURFACE_STATE sInit() { + RENDER_SURFACE_STATE state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 16); + return TheStructure.RawData[index]; + } + inline void setCubeFaceEnablePositiveZ(const bool value) { + TheStructure.Common.CubeFaceEnablePositiveZ = value; + } + inline bool getCubeFaceEnablePositiveZ() const { + return TheStructure.Common.CubeFaceEnablePositiveZ; + } + inline void setCubeFaceEnableNegativeZ(const bool value) { + TheStructure.Common.CubeFaceEnableNegativeZ = value; + } + inline bool getCubeFaceEnableNegativeZ() const { + return TheStructure.Common.CubeFaceEnableNegativeZ; + } + inline void setCubeFaceEnablePositiveY(const bool value) { + TheStructure.Common.CubeFaceEnablePositiveY = value; + } + inline bool getCubeFaceEnablePositiveY() const { + return TheStructure.Common.CubeFaceEnablePositiveY; + } + inline void setCubeFaceEnableNegativeY(const bool value) { + TheStructure.Common.CubeFaceEnableNegativeY = value; + } + inline bool getCubeFaceEnableNegativeY() const { + return TheStructure.Common.CubeFaceEnableNegativeY; + } + inline void setCubeFaceEnablePositiveX(const bool value) { + TheStructure.Common.CubeFaceEnablePositiveX = value; + } + inline bool getCubeFaceEnablePositiveX() const { + return TheStructure.Common.CubeFaceEnablePositiveX; + } + inline void setCubeFaceEnableNegativeX(const bool value) { + TheStructure.Common.CubeFaceEnableNegativeX = value; + } + inline bool getCubeFaceEnableNegativeX() const { + return TheStructure.Common.CubeFaceEnableNegativeX; + } + inline void setMediaBoundaryPixelMode(const MEDIA_BOUNDARY_PIXEL_MODE value) { + TheStructure.Common.MediaBoundaryPixelMode = value; + } + inline MEDIA_BOUNDARY_PIXEL_MODE getMediaBoundaryPixelMode() const { + return static_cast(TheStructure.Common.MediaBoundaryPixelMode); + } + inline void setRenderCacheReadWriteMode(const RENDER_CACHE_READ_WRITE_MODE value) { + TheStructure.Common.RenderCacheReadWriteMode = value; + } + inline RENDER_CACHE_READ_WRITE_MODE getRenderCacheReadWriteMode() const { + return static_cast(TheStructure.Common.RenderCacheReadWriteMode); + } + inline void setSamplerL2OutOfOrderModeDisable(const bool value) { + TheStructure.Common.SamplerL2OutOfOrderModeDisable = value; + } + inline bool getSamplerL2OutOfOrderModeDisable() const { + return TheStructure.Common.SamplerL2OutOfOrderModeDisable; + } + inline void setVerticalLineStrideOffset(const bool value) { + TheStructure.Common.VerticalLineStrideOffset = value; + } + inline bool getVerticalLineStrideOffset() const { + return TheStructure.Common.VerticalLineStrideOffset; + } + inline void setVerticalLineStride(const bool value) { + TheStructure.Common.VerticalLineStride = value; + } + inline bool getVerticalLineStride() const { + return TheStructure.Common.VerticalLineStride; + } + inline void setTileMode(const TILE_MODE value) { + TheStructure.Common.TileMode = value; + } + inline TILE_MODE getTileMode() const { + return static_cast(TheStructure.Common.TileMode); + } + inline void setSurfaceHorizontalAlignment(const SURFACE_HORIZONTAL_ALIGNMENT value) { + TheStructure.Common.SurfaceHorizontalAlignment = value; + } + inline SURFACE_HORIZONTAL_ALIGNMENT getSurfaceHorizontalAlignment() const { + return static_cast(TheStructure.Common.SurfaceHorizontalAlignment); + } + inline void setSurfaceVerticalAlignment(const SURFACE_VERTICAL_ALIGNMENT value) { + TheStructure.Common.SurfaceVerticalAlignment = value; + } + inline SURFACE_VERTICAL_ALIGNMENT getSurfaceVerticalAlignment() const { + return static_cast(TheStructure.Common.SurfaceVerticalAlignment); + } + inline void setSurfaceFormat(const SURFACE_FORMAT value) { + TheStructure.Common.SurfaceFormat = value; + } + inline SURFACE_FORMAT getSurfaceFormat() const { + return static_cast(TheStructure.Common.SurfaceFormat); + } + inline void setAstcEnable(const bool value) { + TheStructure.Common.AstcEnable = value; + } + inline bool getAstcEnable() const { + return TheStructure.Common.AstcEnable; + } + inline void setSurfaceArray(const bool value) { + TheStructure.Common.SurfaceArray = value; + } + inline bool getSurfaceArray() const { + return TheStructure.Common.SurfaceArray; + } + inline void setSurfaceType(const SURFACE_TYPE value) { + TheStructure.Common.SurfaceType = value; + } + inline SURFACE_TYPE getSurfaceType() const { + return static_cast(TheStructure.Common.SurfaceType); + } + typedef enum tagSURFACEQPITCH { + SURFACEQPITCH_BIT_SHIFT = 0x2, + SURFACEQPITCH_ALIGN_SIZE = 0x4, + } SURFACEQPITCH; + inline void setSurfaceQpitch(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x1ffff); + TheStructure.Common.SurfaceQpitch = value >> SURFACEQPITCH_BIT_SHIFT; + } + inline uint32_t getSurfaceQpitch() const { + return TheStructure.Common.SurfaceQpitch << SURFACEQPITCH_BIT_SHIFT; + } + inline void setSampleTapDiscardDisable(const SAMPLE_TAP_DISCARD_DISABLE value) { + TheStructure.Common.SampleTapDiscardDisable = value; + } + inline SAMPLE_TAP_DISCARD_DISABLE getSampleTapDiscardDisable() const { + return static_cast(TheStructure.Common.SampleTapDiscardDisable); + } + inline void setDoubleFetchDisable(const bool value) { + TheStructure.Common.DoubleFetchDisable = value; + } + inline bool getDoubleFetchDisable() const { + return TheStructure.Common.DoubleFetchDisable; + } + inline void setCornerTexelMode(const bool value) { + TheStructure.Common.CornerTexelMode = value; + } + inline bool getCornerTexelMode() const { + return TheStructure.Common.CornerTexelMode; + } + inline void setBaseMipLevel(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x1f); + TheStructure.Common.BaseMipLevel = value; + } + inline uint32_t getBaseMipLevel() const { + return TheStructure.Common.BaseMipLevel; + } + inline void setMemoryObjectControlStateReserved(const uint32_t value) { + TheStructure.Common.MemoryObjectControlStateReserved_56 = value; + } + inline uint32_t getMemoryObjectControlStateReserved() const { + return (TheStructure.Common.MemoryObjectControlStateReserved_56); + } + inline void setMemoryObjectControlState(const uint32_t value) { + TheStructure.Common.MemoryObjectControlStateReserved_56 = value; + TheStructure.Common.MemoryObjectControlStateIndexToMocsTables = (value >> 1); + } + inline uint32_t getMemoryObjectControlState() const { + uint32_t mocs = TheStructure.Common.MemoryObjectControlStateReserved_56; + mocs |= (TheStructure.Common.MemoryObjectControlStateIndexToMocsTables << 1); + return (mocs); + } + inline void setMemoryObjectControlStateIndexToMocsTables(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3f); + TheStructure.Common.MemoryObjectControlStateIndexToMocsTables = value >> 1; + } + inline uint32_t getMemoryObjectControlStateIndexToMocsTables() const { + return (TheStructure.Common.MemoryObjectControlStateIndexToMocsTables << 1); + } + inline void setWidth(const uint32_t value) { + TheStructure.Common.Width = value - 1; + } + inline uint32_t getWidth() const { + return TheStructure.Common.Width + 1; + } + inline void setHeight(const uint32_t value) { + TheStructure.Common.Height = value - 1; + } + inline uint32_t getHeight() const { + return TheStructure.Common.Height + 1; + } + inline void setDepthStencilResource(const bool value) { + TheStructure.Common.DepthStencilResource = value; + } + inline bool getDepthStencilResource() const { + return TheStructure.Common.DepthStencilResource; + } + inline void setSurfacePitch(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x40000); + TheStructure.Common.SurfacePitch = value - 1; + } + inline uint32_t getSurfacePitch() const { + return TheStructure.Common.SurfacePitch + 1; + } + inline void setNullProbingEnable(const NULL_PROBING_ENABLE value) { + TheStructure.Common.NullProbingEnable = value; + } + inline NULL_PROBING_ENABLE getNullProbingEnable() const { + return static_cast(TheStructure.Common.NullProbingEnable); + } + inline void setDepth(const uint32_t value) { + TheStructure.Common.Depth = value - 1; + } + inline uint32_t getDepth() const { + return TheStructure.Common.Depth + 1; + } + inline void setMultisamplePositionPaletteIndex(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x7); + TheStructure.Common.MultisamplePositionPaletteIndex = value; + } + inline uint32_t getMultisamplePositionPaletteIndex() const { + return TheStructure.Common.MultisamplePositionPaletteIndex; + } + inline void setNumberOfMultisamples(const NUMBER_OF_MULTISAMPLES value) { + TheStructure.Common.NumberOfMultisamples = value; + } + inline NUMBER_OF_MULTISAMPLES getNumberOfMultisamples() const { + return static_cast(TheStructure.Common.NumberOfMultisamples); + } + inline void setMultisampledSurfaceStorageFormat(const MULTISAMPLED_SURFACE_STORAGE_FORMAT value) { + TheStructure.Common.MultisampledSurfaceStorageFormat = value; + } + inline MULTISAMPLED_SURFACE_STORAGE_FORMAT getMultisampledSurfaceStorageFormat() const { + return static_cast(TheStructure.Common.MultisampledSurfaceStorageFormat); + } + inline void setRenderTargetViewExtent(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x7ff); + TheStructure.Common.RenderTargetViewExtent = value - 1; + } + inline uint32_t getRenderTargetViewExtent() const { + return TheStructure.Common.RenderTargetViewExtent + 1; + } + inline void setMinimumArrayElement(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x7ff); + TheStructure.Common.MinimumArrayElement = value; + } + inline uint32_t getMinimumArrayElement() const { + return TheStructure.Common.MinimumArrayElement; + } + inline void setRenderTargetAndSampleUnormRotation(const RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION value) { + TheStructure.Common.RenderTargetAndSampleUnormRotation = value; + } + inline RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION getRenderTargetAndSampleUnormRotation() const { + return static_cast(TheStructure.Common.RenderTargetAndSampleUnormRotation); + } + inline void setMipCountLod(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xf); + TheStructure.Common.MipCountLod = value; + } + inline uint32_t getMipCountLod() const { + return TheStructure.Common.MipCountLod; + } + inline void setSurfaceMinLod(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xf); + TheStructure.Common.SurfaceMinLod = value; + } + inline uint32_t getSurfaceMinLod() const { + return TheStructure.Common.SurfaceMinLod; + } + inline void setMipTailStartLod(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xf); + TheStructure.Common.MipTailStartLod = value; + } + inline uint32_t getMipTailStartLod() const { + return TheStructure.Common.MipTailStartLod; + } + inline void setCoherencyType(const COHERENCY_TYPE value) { + TheStructure.Common.CoherencyType = value; + } + inline COHERENCY_TYPE getCoherencyType() const { + return static_cast(TheStructure.Common.CoherencyType); + } + inline void setL1CachePolicyL1CacheControl(const L1_CACHE_POLICY value) { + TheStructure.Common.L1CachePolicyL1CacheControl = value; + } + inline L1_CACHE_POLICY getL1CachePolicyL1CacheControl() const { + return static_cast(TheStructure.Common.L1CachePolicyL1CacheControl); + } + inline void setEwaDisableForCube(const bool value) { + TheStructure.Common.EwaDisableForCube = value; + } + inline bool getEwaDisableForCube() const { + return TheStructure.Common.EwaDisableForCube; + } + typedef enum tagYOFFSET { + YOFFSET_BIT_SHIFT = 0x2, + YOFFSET_ALIGN_SIZE = 0x4, + } YOFFSET; + inline void setYOffset(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x1f); + TheStructure.Common.YOffset = value >> YOFFSET_BIT_SHIFT; + } + inline uint32_t getYOffset() const { + return TheStructure.Common.YOffset << YOFFSET_BIT_SHIFT; + } + typedef enum tagXOFFSET { + XOFFSET_BIT_SHIFT = 0x2, + XOFFSET_ALIGN_SIZE = 0x4, + } XOFFSET; + inline void setXOffset(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x1ff); + TheStructure.Common.XOffset = value >> XOFFSET_BIT_SHIFT; + } + inline uint32_t getXOffset() const { + return TheStructure.Common.XOffset << XOFFSET_BIT_SHIFT; + } + inline void setYuvInterpolationEnable(const bool value) { + TheStructure.Common.YuvInterpolationEnable = value; + } + inline bool getYuvInterpolationEnable() const { + return TheStructure.Common.YuvInterpolationEnable; + } + inline void setResourceMinLod(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xfff); + TheStructure.Common.ResourceMinLod = value; + } + inline uint32_t getResourceMinLod() const { + return TheStructure.Common.ResourceMinLod; + } + inline void setDisableSupportForMultiGpuAtomics(const bool value) { + TheStructure.Common.DisableSupportForMultiGpuAtomics = value; + } + inline bool getDisableSupportForMultiGpuAtomics() const { + return TheStructure.Common.DisableSupportForMultiGpuAtomics; + } + inline void setDisableSupportForMultiGpuPartialWrites(const bool value) { + TheStructure.Common.DisableSupportForMultiGpuPartialWrites = value; + } + inline bool getDisableSupportForMultiGpuPartialWrites() const { + return TheStructure.Common.DisableSupportForMultiGpuPartialWrites; + } + + inline void setShaderChannelSelectAlpha(const SHADER_CHANNEL_SELECT value) { + TheStructure.Common.ShaderChannelSelectAlpha = value; + } + inline SHADER_CHANNEL_SELECT getShaderChannelSelectAlpha() const { + return static_cast(TheStructure.Common.ShaderChannelSelectAlpha); + } + inline void setShaderChannelSelectBlue(const SHADER_CHANNEL_SELECT value) { + TheStructure.Common.ShaderChannelSelectBlue = value; + } + inline SHADER_CHANNEL_SELECT getShaderChannelSelectBlue() const { + return static_cast(TheStructure.Common.ShaderChannelSelectBlue); + } + inline void setShaderChannelSelectGreen(const SHADER_CHANNEL_SELECT value) { + TheStructure.Common.ShaderChannelSelectGreen = value; + } + inline SHADER_CHANNEL_SELECT getShaderChannelSelectGreen() const { + return static_cast(TheStructure.Common.ShaderChannelSelectGreen); + } + inline void setShaderChannelSelectRed(const SHADER_CHANNEL_SELECT value) { + TheStructure.Common.ShaderChannelSelectRed = value; + } + inline SHADER_CHANNEL_SELECT getShaderChannelSelectRed() const { + return static_cast(TheStructure.Common.ShaderChannelSelectRed); + } + inline void setMemoryCompressionEnable(const bool value) { + TheStructure.Common.MemoryCompressionEnable = value; + } + inline bool getMemoryCompressionEnable() const { + return TheStructure.Common.MemoryCompressionEnable; + } + inline void setMemoryCompressionMode(const MEMORY_COMPRESSION_MODE value) { + TheStructure.Common.MemoryCompressionMode = value; + } + inline MEMORY_COMPRESSION_MODE getMemoryCompressionMode() const { + return static_cast(TheStructure.Common.MemoryCompressionMode); + } + inline void setSurfaceBaseAddress(const uint64_t value) { + TheStructure.Common.SurfaceBaseAddress = value; + } + inline uint64_t getSurfaceBaseAddress() const { + return TheStructure.Common.SurfaceBaseAddress; + } + inline void setQuiltWidth(const uint64_t value) { + UNRECOVERABLE_IF(value > 0x1fL); + TheStructure.Common.QuiltWidth = value; + } + inline uint64_t getQuiltWidth() const { + return TheStructure.Common.QuiltWidth; + } + inline void setQuiltHeight(const uint64_t value) { + UNRECOVERABLE_IF(value > 0x1fL); + TheStructure.Common.QuiltHeight = value; + } + inline uint64_t getQuiltHeight() const { + return TheStructure.Common.QuiltHeight; + } + inline void setClearValueAddressEnable(const bool value) { + TheStructure.Common.ClearValueAddressEnable = value; + } + inline bool getClearValueAddressEnable() const { + return TheStructure.Common.ClearValueAddressEnable; + } + inline void setProceduralTexture(const bool value) { + TheStructure.Common.ProceduralTexture = value; + } + inline bool getProceduralTexture() const { + return TheStructure.Common.ProceduralTexture; + } + inline void setCompressionFormat(uint32_t compressionFormat) { + UNRECOVERABLE_IF(compressionFormat > 0x1F); + TheStructure.Common.CompressionFormat = compressionFormat; + } + inline uint32_t getCompressionFormat() const { + return TheStructure.Common.CompressionFormat; + } + typedef enum tagCLEARADDRESSLOW { + CLEARADDRESSLOW_BIT_SHIFT = 0x6, + CLEARADDRESSLOW_ALIGN_SIZE = 0x40, + } CLEARADDRESSLOW; + inline void setClearColorAddress(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xffffffff); + TheStructure.Common.ClearAddressLow = value >> CLEARADDRESSLOW_BIT_SHIFT; + } + inline uint32_t getClearColorAddress() const { + return TheStructure.Common.ClearAddressLow << CLEARADDRESSLOW_BIT_SHIFT; + } + inline void setClearColorAddressHigh(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xffff); + TheStructure.Common.ClearAddressHigh = value; + } + inline uint32_t getClearColorAddressHigh() const { + return TheStructure.Common.ClearAddressHigh; + } + inline void setYOffsetForUOrUvPlane(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3fff); + TheStructure._SurfaceFormatIsPlanar.YOffsetForUOrUvPlane = value; + } + inline uint32_t getYOffsetForUOrUvPlane() const { + return TheStructure._SurfaceFormatIsPlanar.YOffsetForUOrUvPlane; + } + inline void setXOffsetForUOrUvPlane(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3fff); + TheStructure._SurfaceFormatIsPlanar.XOffsetForUOrUvPlane = value; + } + inline uint32_t getXOffsetForUOrUvPlane() const { + return TheStructure._SurfaceFormatIsPlanar.XOffsetForUOrUvPlane; + } + inline void setHalfPitchForChroma(const HALF_PITCH_FOR_CHROMA value) { + TheStructure._SurfaceFormatIsPlanar.HalfPitchForChroma = value; + } + inline HALF_PITCH_FOR_CHROMA getHalfPitchForChroma() const { + return static_cast(TheStructure._SurfaceFormatIsPlanar.HalfPitchForChroma); + } + inline void setSeparateUvPlaneEnable(const bool value) { + TheStructure._SurfaceFormatIsPlanar.SeparateUvPlaneEnable = value; + } + inline bool getSeparateUvPlaneEnable() const { + return TheStructure._SurfaceFormatIsPlanar.SeparateUvPlaneEnable; + } + inline void setYOffsetForVPlane(const uint64_t value) { + UNRECOVERABLE_IF(value > 0x3fffL); + TheStructure._SurfaceFormatIsPlanar.YOffsetForVPlane = value; + } + inline uint64_t getYOffsetForVPlane() const { + return TheStructure._SurfaceFormatIsPlanar.YOffsetForVPlane; + } + inline void setXOffsetForVPlane(const uint64_t value) { + UNRECOVERABLE_IF(value > 0x3fffL); + TheStructure._SurfaceFormatIsPlanar.XOffsetForVPlane = value; + } + inline uint64_t getXOffsetForVPlane() const { + return TheStructure._SurfaceFormatIsPlanar.XOffsetForVPlane; + } + inline void setAuxiliarySurfaceMode(const AUXILIARY_SURFACE_MODE value) { + TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceMode = value; + } + inline AUXILIARY_SURFACE_MODE getAuxiliarySurfaceMode() const { + return static_cast(TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceMode); + } + inline void setAuxiliarySurfacePitch(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3ff); + TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfacePitch = value - 1; + } + inline uint32_t getAuxiliarySurfacePitch() const { + return TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfacePitch + 1; + } + typedef enum tagAUXILIARYSURFACEQPITCH { + AUXILIARYSURFACEQPITCH_BIT_SHIFT = 0x2, + AUXILIARYSURFACEQPITCH_ALIGN_SIZE = 0x4, + } AUXILIARYSURFACEQPITCH; + inline void setAuxiliarySurfaceQpitch(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x1ffff); + TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceQpitch = value >> AUXILIARYSURFACEQPITCH_BIT_SHIFT; + } + inline uint32_t getAuxiliarySurfaceQpitch() const { + return TheStructure._SurfaceFormatIsnotPlanar.AuxiliarySurfaceQpitch << AUXILIARYSURFACEQPITCH_BIT_SHIFT; + } + typedef enum tagAUXILIARYSURFACEBASEADDRESS { + AUXILIARYSURFACEBASEADDRESS_BIT_SHIFT = 0xc, + AUXILIARYSURFACEBASEADDRESS_ALIGN_SIZE = 0x1000, + } AUXILIARYSURFACEBASEADDRESS; + inline void setAuxiliarySurfaceBaseAddress(const uint64_t value) { + UNRECOVERABLE_IF(value > 0xffffffffffffffffL); + TheStructure._SurfaceFormatIsnotPlanarAndMemoryCompressionEnableIs0.AuxiliarySurfaceBaseAddress = value >> AUXILIARYSURFACEBASEADDRESS_BIT_SHIFT; + } + inline uint64_t getAuxiliarySurfaceBaseAddress() const { + return TheStructure._SurfaceFormatIsnotPlanarAndMemoryCompressionEnableIs0.AuxiliarySurfaceBaseAddress << AUXILIARYSURFACEBASEADDRESS_BIT_SHIFT; + } +} RENDER_SURFACE_STATE; +STATIC_ASSERT(64 == sizeof(RENDER_SURFACE_STATE)); + +typedef struct tagSAMPLER_STATE { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t LodAlgorithm : BITFIELD_RANGE(0, 0); + uint32_t TextureLodBias : BITFIELD_RANGE(1, 13); + uint32_t MinModeFilter : BITFIELD_RANGE(14, 16); + uint32_t MagModeFilter : BITFIELD_RANGE(17, 19); + uint32_t MipModeFilter : BITFIELD_RANGE(20, 21); + uint32_t Reserved_22 : BITFIELD_RANGE(22, 25); + uint32_t Reserved_26 : BITFIELD_RANGE(26, 26); + uint32_t LodPreclampMode : BITFIELD_RANGE(27, 28); + uint32_t Reserved_29 : BITFIELD_RANGE(29, 29); + uint32_t CpsLodCompensationEnable : BITFIELD_RANGE(30, 30); + uint32_t SamplerDisable : BITFIELD_RANGE(31, 31); + // DWORD 1 + uint32_t CubeSurfaceControlMode : BITFIELD_RANGE(0, 0); + uint32_t ShadowFunction : BITFIELD_RANGE(1, 3); + uint32_t ChromakeyMode : BITFIELD_RANGE(4, 4); + uint32_t ChromakeyIndex : BITFIELD_RANGE(5, 6); + uint32_t ChromakeyEnable : BITFIELD_RANGE(7, 7); + uint32_t MaxLod : BITFIELD_RANGE(8, 19); + uint32_t MinLod : BITFIELD_RANGE(20, 31); + // DWORD 2 + uint32_t LodClampMagnificationMode : BITFIELD_RANGE(0, 0); + uint32_t SrgbDecode : BITFIELD_RANGE(1, 1); + uint32_t ReturnFilterWeightForNullTexels : BITFIELD_RANGE(2, 2); + uint32_t ReturnFilterWeightForBorderTexels : BITFIELD_RANGE(3, 3); + uint32_t Reserved_68 : BITFIELD_RANGE(4, 4); + uint32_t ForceGather4Behavior : BITFIELD_RANGE(5, 5); + uint32_t IndirectStatePointer : BITFIELD_RANGE(6, 23); + uint32_t ExtendedIndirectStatePointer : BITFIELD_RANGE(24, 31); + // DWORD 3 + uint32_t TczAddressControlMode : BITFIELD_RANGE(0, 2); + uint32_t TcyAddressControlMode : BITFIELD_RANGE(3, 5); + uint32_t TcxAddressControlMode : BITFIELD_RANGE(6, 8); + uint32_t ReductionTypeEnable : BITFIELD_RANGE(9, 9); + uint32_t NonNormalizedCoordinateEnable : BITFIELD_RANGE(10, 10); + uint32_t MipLinearFilterQuality : BITFIELD_RANGE(11, 12); + uint32_t RAddressMinFilterRoundingEnable : BITFIELD_RANGE(13, 13); + uint32_t RAddressMagFilterRoundingEnable : BITFIELD_RANGE(14, 14); + uint32_t VAddressMinFilterRoundingEnable : BITFIELD_RANGE(15, 15); + uint32_t VAddressMagFilterRoundingEnable : BITFIELD_RANGE(16, 16); + uint32_t UAddressMinFilterRoundingEnable : BITFIELD_RANGE(17, 17); + uint32_t UAddressMagFilterRoundingEnable : BITFIELD_RANGE(18, 18); + uint32_t MaximumAnisotropy : BITFIELD_RANGE(19, 21); + uint32_t ReductionType : BITFIELD_RANGE(22, 23); + uint32_t AllowLowQualityLodCalculation : BITFIELD_RANGE(24, 24); + uint32_t Reserved_121 : BITFIELD_RANGE(25, 25); + uint32_t LowQualityFilter : BITFIELD_RANGE(26, 26); + uint32_t Reserved_123 : BITFIELD_RANGE(27, 31); + } Common; + uint32_t RawData[4]; + } TheStructure; + typedef enum tagLOD_ALGORITHM { + LOD_ALGORITHM_LEGACY = 0x0, + LOD_ALGORITHM_EWA_APPROXIMATION = 0x1, + } LOD_ALGORITHM; + typedef enum tagMIN_MODE_FILTER { + MIN_MODE_FILTER_NEAREST = 0x0, + MIN_MODE_FILTER_LINEAR = 0x1, + MIN_MODE_FILTER_ANISOTROPIC = 0x2, + } MIN_MODE_FILTER; + typedef enum tagMAG_MODE_FILTER { + MAG_MODE_FILTER_NEAREST = 0x0, + MAG_MODE_FILTER_LINEAR = 0x1, + MAG_MODE_FILTER_ANISOTROPIC = 0x2, + } MAG_MODE_FILTER; + typedef enum tagMIP_MODE_FILTER { + MIP_MODE_FILTER_NONE = 0x0, + MIP_MODE_FILTER_NEAREST = 0x1, + MIP_MODE_FILTER_LINEAR = 0x3, + } MIP_MODE_FILTER; + typedef enum tagLOD_PRECLAMP_MODE { + LOD_PRECLAMP_MODE_NONE = 0x0, + LOD_PRECLAMP_MODE_OGL = 0x2, + } LOD_PRECLAMP_MODE; + typedef enum tagCUBE_SURFACE_CONTROL_MODE { + CUBE_SURFACE_CONTROL_MODE_PROGRAMMED = 0x0, + CUBE_SURFACE_CONTROL_MODE_OVERRIDE = 0x1, + } CUBE_SURFACE_CONTROL_MODE; + typedef enum tagSHADOW_FUNCTION { + SHADOW_FUNCTION_PREFILTEROP_ALWAYS = 0x0, + SHADOW_FUNCTION_PREFILTEROP_NEVER = 0x1, + SHADOW_FUNCTION_PREFILTEROP_LESS = 0x2, + SHADOW_FUNCTION_PREFILTEROP_EQUAL = 0x3, + SHADOW_FUNCTION_PREFILTEROP_LEQUAL = 0x4, + SHADOW_FUNCTION_PREFILTEROP_GREATER = 0x5, + SHADOW_FUNCTION_PREFILTEROP_NOTEQUAL = 0x6, + SHADOW_FUNCTION_PREFILTEROP_GEQUAL = 0x7, + } SHADOW_FUNCTION; + typedef enum tagCHROMAKEY_MODE { + CHROMAKEY_MODE_KEYFILTER_KILL_ON_ANY_MATCH = 0x0, + CHROMAKEY_MODE_KEYFILTER_REPLACE_BLACK = 0x1, + } CHROMAKEY_MODE; + typedef enum tagLOD_CLAMP_MAGNIFICATION_MODE { + LOD_CLAMP_MAGNIFICATION_MODE_MIPNONE = 0x0, + LOD_CLAMP_MAGNIFICATION_MODE_MIPFILTER = 0x1, + } LOD_CLAMP_MAGNIFICATION_MODE; + typedef enum tagSRGB_DECODE { + SRGB_DECODE_DECODE_EXT = 0x0, + SRGB_DECODE_SKIP_DECODE_EXT = 0x1, + } SRGB_DECODE; + typedef enum tagRETURN_FILTER_WEIGHT_FOR_NULL_TEXELS { + RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS_DISABLE = 0x0, + RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS_ENABLE = 0x1, + } RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS; + typedef enum tagRETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS { + RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS_DISABLE = 0x0, + RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS_ENABLE = 0x1, + } RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS; + typedef enum tagTEXTURE_COORDINATE_MODE { + TEXTURE_COORDINATE_MODE_WRAP = 0x0, + TEXTURE_COORDINATE_MODE_MIRROR = 0x1, + TEXTURE_COORDINATE_MODE_CLAMP = 0x2, + TEXTURE_COORDINATE_MODE_CUBE = 0x3, + TEXTURE_COORDINATE_MODE_CLAMP_BORDER = 0x4, + TEXTURE_COORDINATE_MODE_MIRROR_ONCE = 0x5, + TEXTURE_COORDINATE_MODE_HALF_BORDER = 0x6, + TEXTURE_COORDINATE_MODE_MIRROR_101 = 0x7, + } TEXTURE_COORDINATE_MODE; + typedef enum tagMIP_LINEAR_FILTER_QUALITY { + MIP_LINEAR_FILTER_QUALITY_FULL_QUALITY = 0x0, + MIP_LINEAR_FILTER_QUALITY_HIGH_QUALITY = 0x1, + MIP_LINEAR_FILTER_QUALITY_MEDIUM_QUALITY = 0x2, + MIP_LINEAR_FILTER_QUALITY_LOW_QUALITY = 0x3, + } MIP_LINEAR_FILTER_QUALITY; + typedef enum tagMAXIMUM_ANISOTROPY { + MAXIMUM_ANISOTROPY_RATIO_21 = 0x0, + MAXIMUM_ANISOTROPY_RATIO_41 = 0x1, + MAXIMUM_ANISOTROPY_RATIO_61 = 0x2, + MAXIMUM_ANISOTROPY_RATIO_81 = 0x3, + MAXIMUM_ANISOTROPY_RATIO_101 = 0x4, + MAXIMUM_ANISOTROPY_RATIO_121 = 0x5, + MAXIMUM_ANISOTROPY_RATIO_141 = 0x6, + MAXIMUM_ANISOTROPY_RATIO_161 = 0x7, + } MAXIMUM_ANISOTROPY; + typedef enum tagREDUCTION_TYPE { + REDUCTION_TYPE_STD_FILTER = 0x0, + REDUCTION_TYPE_COMPARISON = 0x1, + REDUCTION_TYPE_MINIMUM = 0x2, + REDUCTION_TYPE_MAXIMUM = 0x3, + } REDUCTION_TYPE; + typedef enum tagLOW_QUALITY_FILTER { + LOW_QUALITY_FILTER_DISABLE = 0x0, + LOW_QUALITY_FILTER_ENABLE = 0x1, + } LOW_QUALITY_FILTER; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.LodAlgorithm = LOD_ALGORITHM_LEGACY; + TheStructure.Common.MinModeFilter = MIN_MODE_FILTER_NEAREST; + TheStructure.Common.MagModeFilter = MAG_MODE_FILTER_NEAREST; + TheStructure.Common.MipModeFilter = MIP_MODE_FILTER_NONE; + TheStructure.Common.LodPreclampMode = LOD_PRECLAMP_MODE_NONE; + TheStructure.Common.CubeSurfaceControlMode = CUBE_SURFACE_CONTROL_MODE_PROGRAMMED; + TheStructure.Common.ShadowFunction = SHADOW_FUNCTION_PREFILTEROP_ALWAYS; + TheStructure.Common.ChromakeyMode = CHROMAKEY_MODE_KEYFILTER_KILL_ON_ANY_MATCH; + TheStructure.Common.LodClampMagnificationMode = LOD_CLAMP_MAGNIFICATION_MODE_MIPNONE; + TheStructure.Common.SrgbDecode = SRGB_DECODE_DECODE_EXT; + TheStructure.Common.ReturnFilterWeightForNullTexels = RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS_DISABLE; + TheStructure.Common.ReturnFilterWeightForBorderTexels = RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS_DISABLE; + TheStructure.Common.TczAddressControlMode = TEXTURE_COORDINATE_MODE_WRAP; + TheStructure.Common.TcyAddressControlMode = TEXTURE_COORDINATE_MODE_WRAP; + TheStructure.Common.TcxAddressControlMode = TEXTURE_COORDINATE_MODE_WRAP; + TheStructure.Common.MipLinearFilterQuality = MIP_LINEAR_FILTER_QUALITY_FULL_QUALITY; + TheStructure.Common.MaximumAnisotropy = MAXIMUM_ANISOTROPY_RATIO_21; + TheStructure.Common.ReductionType = REDUCTION_TYPE_STD_FILTER; + TheStructure.Common.LowQualityFilter = LOW_QUALITY_FILTER_DISABLE; + } + static tagSAMPLER_STATE sInit() { + SAMPLER_STATE state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 4); + return TheStructure.RawData[index]; + } + inline void setLodAlgorithm(const LOD_ALGORITHM value) { + TheStructure.Common.LodAlgorithm = value; + } + inline LOD_ALGORITHM getLodAlgorithm() const { + return static_cast(TheStructure.Common.LodAlgorithm); + } + inline void setTextureLodBias(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3ffe); + TheStructure.Common.TextureLodBias = value; + } + inline uint32_t getTextureLodBias() const { + return TheStructure.Common.TextureLodBias; + } + inline void setMinModeFilter(const MIN_MODE_FILTER value) { + TheStructure.Common.MinModeFilter = value; + } + inline MIN_MODE_FILTER getMinModeFilter() const { + return static_cast(TheStructure.Common.MinModeFilter); + } + inline void setMagModeFilter(const MAG_MODE_FILTER value) { + TheStructure.Common.MagModeFilter = value; + } + inline MAG_MODE_FILTER getMagModeFilter() const { + return static_cast(TheStructure.Common.MagModeFilter); + } + inline void setMipModeFilter(const MIP_MODE_FILTER value) { + TheStructure.Common.MipModeFilter = value; + } + inline MIP_MODE_FILTER getMipModeFilter() const { + return static_cast(TheStructure.Common.MipModeFilter); + } + inline void setLodPreclampMode(const LOD_PRECLAMP_MODE value) { + TheStructure.Common.LodPreclampMode = value; + } + inline LOD_PRECLAMP_MODE getLodPreclampMode() const { + return static_cast(TheStructure.Common.LodPreclampMode); + } + inline void setCpsLodCompensationEnable(const bool value) { + TheStructure.Common.CpsLodCompensationEnable = value; + } + inline bool getCpsLodCompensationEnable() const { + return TheStructure.Common.CpsLodCompensationEnable; + } + inline void setSamplerDisable(const bool value) { + TheStructure.Common.SamplerDisable = value; + } + inline bool getSamplerDisable() const { + return TheStructure.Common.SamplerDisable; + } + inline void setCubeSurfaceControlMode(const CUBE_SURFACE_CONTROL_MODE value) { + TheStructure.Common.CubeSurfaceControlMode = value; + } + inline CUBE_SURFACE_CONTROL_MODE getCubeSurfaceControlMode() const { + return static_cast(TheStructure.Common.CubeSurfaceControlMode); + } + inline void setShadowFunction(const SHADOW_FUNCTION value) { + TheStructure.Common.ShadowFunction = value; + } + inline SHADOW_FUNCTION getShadowFunction() const { + return static_cast(TheStructure.Common.ShadowFunction); + } + inline void setChromakeyMode(const CHROMAKEY_MODE value) { + TheStructure.Common.ChromakeyMode = value; + } + inline CHROMAKEY_MODE getChromakeyMode() const { + return static_cast(TheStructure.Common.ChromakeyMode); + } + inline void setChromakeyIndex(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x60); + TheStructure.Common.ChromakeyIndex = value; + } + inline uint32_t getChromakeyIndex() const { + return TheStructure.Common.ChromakeyIndex; + } + inline void setChromakeyEnable(const bool value) { + TheStructure.Common.ChromakeyEnable = value; + } + inline bool getChromakeyEnable() const { + return TheStructure.Common.ChromakeyEnable; + } + inline void setMaxLod(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xfff00); + TheStructure.Common.MaxLod = value; + } + inline uint32_t getMaxLod() const { + return TheStructure.Common.MaxLod; + } + inline void setMinLod(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xfff00000); + TheStructure.Common.MinLod = value; + } + inline uint32_t getMinLod() const { + return TheStructure.Common.MinLod; + } + inline void setLodClampMagnificationMode(const LOD_CLAMP_MAGNIFICATION_MODE value) { + TheStructure.Common.LodClampMagnificationMode = value; + } + inline LOD_CLAMP_MAGNIFICATION_MODE getLodClampMagnificationMode() const { + return static_cast(TheStructure.Common.LodClampMagnificationMode); + } + inline void setSrgbDecode(const SRGB_DECODE value) { + TheStructure.Common.SrgbDecode = value; + } + inline SRGB_DECODE getSrgbDecode() const { + return static_cast(TheStructure.Common.SrgbDecode); + } + inline void setReturnFilterWeightForNullTexels(const RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS value) { + TheStructure.Common.ReturnFilterWeightForNullTexels = value; + } + inline RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS getReturnFilterWeightForNullTexels() const { + return static_cast(TheStructure.Common.ReturnFilterWeightForNullTexels); + } + inline void setReturnFilterWeightForBorderTexels(const RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS value) { + TheStructure.Common.ReturnFilterWeightForBorderTexels = value; + } + inline RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS getReturnFilterWeightForBorderTexels() const { + return static_cast(TheStructure.Common.ReturnFilterWeightForBorderTexels); + } + inline void setForceGather4Behavior(const bool value) { + TheStructure.Common.ForceGather4Behavior = value; + } + inline bool getForceGather4Behavior() const { + return TheStructure.Common.ForceGather4Behavior; + } + typedef enum tagINDIRECTSTATEPOINTER { + INDIRECTSTATEPOINTER_BIT_SHIFT = 0x6, + INDIRECTSTATEPOINTER_ALIGN_SIZE = 0x40, + } INDIRECTSTATEPOINTER; + inline void setIndirectStatePointer(const uint64_t value) { + UNRECOVERABLE_IF(value > 0xffffc0L); + TheStructure.Common.IndirectStatePointer = static_cast(value) >> INDIRECTSTATEPOINTER_BIT_SHIFT; + } + inline uint64_t getIndirectStatePointer() const { + return TheStructure.Common.IndirectStatePointer << INDIRECTSTATEPOINTER_BIT_SHIFT; + } + inline void setTczAddressControlMode(const TEXTURE_COORDINATE_MODE value) { + TheStructure.Common.TczAddressControlMode = value; + } + inline TEXTURE_COORDINATE_MODE getTczAddressControlMode() const { + return static_cast(TheStructure.Common.TczAddressControlMode); + } + inline void setTcyAddressControlMode(const TEXTURE_COORDINATE_MODE value) { + TheStructure.Common.TcyAddressControlMode = value; + } + inline TEXTURE_COORDINATE_MODE getTcyAddressControlMode() const { + return static_cast(TheStructure.Common.TcyAddressControlMode); + } + inline void setTcxAddressControlMode(const TEXTURE_COORDINATE_MODE value) { + TheStructure.Common.TcxAddressControlMode = value; + } + inline TEXTURE_COORDINATE_MODE getTcxAddressControlMode() const { + return static_cast(TheStructure.Common.TcxAddressControlMode); + } + inline void setReductionTypeEnable(const bool value) { + TheStructure.Common.ReductionTypeEnable = value; + } + inline bool getReductionTypeEnable() const { + return TheStructure.Common.ReductionTypeEnable; + } + inline void setNonNormalizedCoordinateEnable(const bool value) { + TheStructure.Common.NonNormalizedCoordinateEnable = value; + } + inline bool getNonNormalizedCoordinateEnable() const { + return TheStructure.Common.NonNormalizedCoordinateEnable; + } + inline void setMipLinearFilterQuality(const MIP_LINEAR_FILTER_QUALITY value) { + TheStructure.Common.MipLinearFilterQuality = value; + } + inline MIP_LINEAR_FILTER_QUALITY getMipLinearFilterQuality() const { + return static_cast(TheStructure.Common.MipLinearFilterQuality); + } + inline void setRAddressMinFilterRoundingEnable(const bool value) { + TheStructure.Common.RAddressMinFilterRoundingEnable = value; + } + inline bool getRAddressMinFilterRoundingEnable() const { + return TheStructure.Common.RAddressMinFilterRoundingEnable; + } + inline void setRAddressMagFilterRoundingEnable(const bool value) { + TheStructure.Common.RAddressMagFilterRoundingEnable = value; + } + inline bool getRAddressMagFilterRoundingEnable() const { + return TheStructure.Common.RAddressMagFilterRoundingEnable; + } + inline void setVAddressMinFilterRoundingEnable(const bool value) { + TheStructure.Common.VAddressMinFilterRoundingEnable = value; + } + inline bool getVAddressMinFilterRoundingEnable() const { + return TheStructure.Common.VAddressMinFilterRoundingEnable; + } + inline void setVAddressMagFilterRoundingEnable(const bool value) { + TheStructure.Common.VAddressMagFilterRoundingEnable = value; + } + inline bool getVAddressMagFilterRoundingEnable() const { + return TheStructure.Common.VAddressMagFilterRoundingEnable; + } + inline void setUAddressMinFilterRoundingEnable(const bool value) { + TheStructure.Common.UAddressMinFilterRoundingEnable = value; + } + inline bool getUAddressMinFilterRoundingEnable() const { + return TheStructure.Common.UAddressMinFilterRoundingEnable; + } + inline void setUAddressMagFilterRoundingEnable(const bool value) { + TheStructure.Common.UAddressMagFilterRoundingEnable = value; + } + inline bool getUAddressMagFilterRoundingEnable() const { + return TheStructure.Common.UAddressMagFilterRoundingEnable; + } + inline void setMaximumAnisotropy(const MAXIMUM_ANISOTROPY value) { + TheStructure.Common.MaximumAnisotropy = value; + } + inline MAXIMUM_ANISOTROPY getMaximumAnisotropy() const { + return static_cast(TheStructure.Common.MaximumAnisotropy); + } + inline void setReductionType(const REDUCTION_TYPE value) { + TheStructure.Common.ReductionType = value; + } + inline REDUCTION_TYPE getReductionType() const { + return static_cast(TheStructure.Common.ReductionType); + } + inline void setLowQualityFilter(const LOW_QUALITY_FILTER value) { + TheStructure.Common.LowQualityFilter = value; + } + inline LOW_QUALITY_FILTER getLowQualityFilter() const { + return static_cast(TheStructure.Common.LowQualityFilter); + } + inline void setAllowLowQualityLodCalculation(const bool value) { + TheStructure.Common.AllowLowQualityLodCalculation = value; + } + inline bool getAllowLowQualityLodCalculation() const { + return TheStructure.Common.AllowLowQualityLodCalculation; + } +} SAMPLER_STATE; +STATIC_ASSERT(16 == sizeof(SAMPLER_STATE)); + +typedef struct tagSTATE_BASE_ADDRESS { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 15); + uint32_t _3DCommandSubOpcode : BITFIELD_RANGE(16, 23); + uint32_t _3DCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t CommandSubtype : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint64_t GeneralStateBaseAddressModifyEnable : BITFIELD_RANGE(0, 0); + uint64_t Reserved_33 : BITFIELD_RANGE(1, 4); + uint64_t GeneralStateMemoryObjectControlStateIndexToMocsTables : BITFIELD_RANGE(5, 10); + uint64_t Reserved_43 : BITFIELD_RANGE(11, 11); + uint64_t GeneralStateBaseAddress : BITFIELD_RANGE(12, 56); + uint64_t GeneralStateBaseAddressReserved_89 : BITFIELD_RANGE(57, 63); + // DWORD 3 + uint32_t CoherencySettingModifyEnable : BITFIELD_RANGE(0, 0); + uint32_t Reserved_97 : BITFIELD_RANGE(1, 12); + uint32_t EnableMemoryCompressionForAllStatelessAccesses : BITFIELD_RANGE(13, 13); + uint32_t DisableSupportForMultiGpuAtomicsForStatelessAccesses : BITFIELD_RANGE(14, 14); + uint32_t DisableSupportForMultiGpuPartialWritesForStatelessMessages : BITFIELD_RANGE(15, 15); + uint32_t StatelessDataPortAccessMemoryObjectControlStateReserved_112 : BITFIELD_RANGE(16, 16); + uint32_t StatelessDataPortAccessMemoryObjectControlStateIndexToMocsTables : BITFIELD_RANGE(17, 22); + uint32_t L1CachePolicyL1CacheControl : BITFIELD_RANGE(23, 25); + uint32_t Reserved_122 : BITFIELD_RANGE(26, 31); + // DWORD 4 + uint64_t SurfaceStateBaseAddressModifyEnable : BITFIELD_RANGE(0, 0); + uint64_t Reserved_129 : BITFIELD_RANGE(1, 4); + uint64_t SurfaceStateMemoryObjectControlStateIndexToMocsTables : BITFIELD_RANGE(5, 10); + uint64_t Reserved_139 : BITFIELD_RANGE(11, 11); + uint64_t SurfaceStateBaseAddress : BITFIELD_RANGE(12, 63); + // DWORD 6 + uint64_t DynamicStateBaseAddressModifyEnable : BITFIELD_RANGE(0, 0); + uint64_t Reserved_193 : BITFIELD_RANGE(1, 4); + uint64_t DynamicStateMemoryObjectControlStateIndexToMocsTables : BITFIELD_RANGE(5, 10); + uint64_t Reserved_203 : BITFIELD_RANGE(11, 11); + uint64_t DynamicStateBaseAddress : BITFIELD_RANGE(12, 63); + // DWORD 8 + uint64_t Reserved8 : BITFIELD_RANGE(0, 63); + // DWORD 10 + uint64_t InstructionBaseAddressModifyEnable : BITFIELD_RANGE(0, 0); + uint64_t Reserved_321 : BITFIELD_RANGE(1, 3); + uint64_t InstructionMemoryObjectControlStateReserved_324 : BITFIELD_RANGE(4, 4); // patched + uint64_t InstructionMemoryObjectControlStateIndexToMocsTables : BITFIELD_RANGE(5, 10); + uint64_t Reserved_331 : BITFIELD_RANGE(11, 11); + uint64_t InstructionBaseAddress : BITFIELD_RANGE(12, 63); + // DWORD 12 + uint32_t GeneralStateBufferSizeModifyEnable : BITFIELD_RANGE(0, 0); + uint32_t Reserved_385 : BITFIELD_RANGE(1, 11); + uint32_t GeneralStateBufferSize : BITFIELD_RANGE(12, 31); + // DWORD 13 + uint32_t DynamicStateBufferSizeModifyEnable : BITFIELD_RANGE(0, 0); + uint32_t Reserved_417 : BITFIELD_RANGE(1, 11); + uint32_t DynamicStateBufferSize : BITFIELD_RANGE(12, 31); + // DWORD 14 + uint32_t IndirectObjectBufferSizeModifyEnable : BITFIELD_RANGE(0, 0); + uint32_t Reserved_449 : BITFIELD_RANGE(1, 11); + uint32_t IndirectObjectBufferSize : BITFIELD_RANGE(12, 31); + // DWORD 15 + uint32_t InstructionBufferSizeModifyEnable : BITFIELD_RANGE(0, 0); + uint32_t Reserved_481 : BITFIELD_RANGE(1, 11); + uint32_t InstructionBufferSize : BITFIELD_RANGE(12, 31); + // DWORD 16 + uint64_t BindlessSurfaceStateBaseAddressModifyEnable : BITFIELD_RANGE(0, 0); + uint64_t Reserved_513 : BITFIELD_RANGE(1, 4); + uint64_t BindlessSurfaceStateMemoryObjectControlStateIndexToMocsTables : BITFIELD_RANGE(5, 10); + uint64_t Reserved_523 : BITFIELD_RANGE(11, 11); + uint64_t BindlessSurfaceStateBaseAddress : BITFIELD_RANGE(12, 63); + // DWORD 18 + uint32_t BindlessSurfaceStateSize; + // DWORD 19 + uint64_t BindlessSamplerStateBaseAddressModifyEnable : BITFIELD_RANGE(0, 0); + uint64_t Reserved_609 : BITFIELD_RANGE(1, 3); + uint64_t BindlessSamplerStateMemoryObjectControlStateReserved_612 : BITFIELD_RANGE(4, 4); + uint64_t BindlessSamplerStateMemoryObjectControlStateIndexToMocsTables : BITFIELD_RANGE(5, 10); + uint64_t Reserved_619 : BITFIELD_RANGE(11, 11); + uint64_t BindlessSamplerStateBaseAddress : BITFIELD_RANGE(12, 63); + // DWORD 21 + uint32_t Reserved_672 : BITFIELD_RANGE(0, 11); + uint32_t BindlessSamplerStateBufferSize : BITFIELD_RANGE(12, 31); + } Common; + uint32_t RawData[22]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_DWORD_COUNT_N = 0x14, + } DWORD_LENGTH; + typedef enum tag_3D_COMMAND_SUB_OPCODE { + _3D_COMMAND_SUB_OPCODE_STATE_BASE_ADDRESS = 0x1, + } _3D_COMMAND_SUB_OPCODE; + typedef enum tag_3D_COMMAND_OPCODE { + _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED = 0x1, + } _3D_COMMAND_OPCODE; + typedef enum tagCOMMAND_SUBTYPE { + COMMAND_SUBTYPE_GFXPIPE_COMMON = 0x0, + } COMMAND_SUBTYPE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + typedef enum tagCOHERENCY_SETTING_MODIFY_ENABLE { + COHERENCY_SETTING_MODIFY_ENABLE_DISABLE_WRITE_TO_THIS_DW = 0x0, + COHERENCY_SETTING_MODIFY_ENABLE_ENABLE_WRITE_TO_THIS_DW = 0x1, + } COHERENCY_SETTING_MODIFY_ENABLE; + typedef enum tagENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES { + ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES_DISABLED = 0x0, + ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES_ENABLED = 0x1, + } ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES; + typedef enum tagL1_CACHE_POLICY { + L1_CACHE_POLICY_WBP = 0x0, + L1_CACHE_POLICY_UC = 0x1, + L1_CACHE_POLICY_WB = 0x2, + L1_CACHE_POLICY_WT = 0x3, + L1_CACHE_POLICY_WS = 0x4, + } L1_CACHE_POLICY; + typedef enum tagPATCH_CONSTANTS { // patched + GENERALSTATEBASEADDRESS_BYTEOFFSET = 0x4, + GENERALSTATEBASEADDRESS_INDEX = 0x1, + SURFACESTATEBASEADDRESS_BYTEOFFSET = 0x10, + SURFACESTATEBASEADDRESS_INDEX = 0x4, + DYNAMICSTATEBASEADDRESS_BYTEOFFSET = 0x18, + DYNAMICSTATEBASEADDRESS_INDEX = 0x6, + INSTRUCTIONBASEADDRESS_BYTEOFFSET = 0x28, + INSTRUCTIONBASEADDRESS_INDEX = 0xa, + BINDLESSSURFACESTATEBASEADDRESS_BYTEOFFSET = 0x40, + BINDLESSSURFACESTATEBASEADDRESS_INDEX = 0x10, + BINDLESSSAMPLERSTATEBASEADDRESS_BYTEOFFSET = 0x4c, + BINDLESSSAMPLERSTATEBASEADDRESS_INDEX = 0x13, + } PATCH_CONSTANTS; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_DWORD_COUNT_N; + TheStructure.Common._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_STATE_BASE_ADDRESS; + TheStructure.Common._3DCommandOpcode = _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED; + TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_COMMON; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + TheStructure.Common.CoherencySettingModifyEnable = COHERENCY_SETTING_MODIFY_ENABLE_DISABLE_WRITE_TO_THIS_DW; + TheStructure.Common.EnableMemoryCompressionForAllStatelessAccesses = ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES_DISABLED; + TheStructure.Common.L1CachePolicyL1CacheControl = L1_CACHE_POLICY_WBP; + } + static tagSTATE_BASE_ADDRESS sInit() { + STATE_BASE_ADDRESS state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 22); + return TheStructure.RawData[index]; + } + inline void setGeneralStateBaseAddressModifyEnable(const bool value) { + TheStructure.Common.GeneralStateBaseAddressModifyEnable = value; + } + inline bool getGeneralStateBaseAddressModifyEnable() const { + return TheStructure.Common.GeneralStateBaseAddressModifyEnable; + } + inline void setGeneralStateMemoryObjectControlStateIndexToMocsTables(const uint64_t value) { + UNRECOVERABLE_IF(value > 0x7fL); + TheStructure.Common.GeneralStateMemoryObjectControlStateIndexToMocsTables = (value >> 1); // patched + } + inline uint64_t getGeneralStateMemoryObjectControlStateIndexToMocsTables() const { + return TheStructure.Common.GeneralStateMemoryObjectControlStateIndexToMocsTables << 1; // patched + } + typedef enum tagGENERALSTATEBASEADDRESS { + GENERALSTATEBASEADDRESS_BIT_SHIFT = 0xc, + GENERALSTATEBASEADDRESS_ALIGN_SIZE = 0x1000, + } GENERALSTATEBASEADDRESS; + inline void setGeneralStateBaseAddress(const uint64_t value) { + UNRECOVERABLE_IF(value > 0x1ffffffffffffffL); + TheStructure.Common.GeneralStateBaseAddress = value >> GENERALSTATEBASEADDRESS_BIT_SHIFT; + } + inline uint64_t getGeneralStateBaseAddress() const { + return TheStructure.Common.GeneralStateBaseAddress << GENERALSTATEBASEADDRESS_BIT_SHIFT; + } + inline void setCoherencySettingModifyEnable(const COHERENCY_SETTING_MODIFY_ENABLE value) { + TheStructure.Common.CoherencySettingModifyEnable = value; + } + inline COHERENCY_SETTING_MODIFY_ENABLE getCoherencySettingModifyEnable() const { + return static_cast(TheStructure.Common.CoherencySettingModifyEnable); + } + inline void setEnableMemoryCompressionForAllStatelessAccesses(const ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES value) { + TheStructure.Common.EnableMemoryCompressionForAllStatelessAccesses = value; + } + inline ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES getEnableMemoryCompressionForAllStatelessAccesses() const { + return static_cast(TheStructure.Common.EnableMemoryCompressionForAllStatelessAccesses); + } + inline void setDisableSupportForMultiGpuAtomicsForStatelessAccesses(const bool value) { + TheStructure.Common.DisableSupportForMultiGpuAtomicsForStatelessAccesses = value; + } + inline bool getDisableSupportForMultiGpuAtomicsForStatelessAccesses() const { + return TheStructure.Common.DisableSupportForMultiGpuAtomicsForStatelessAccesses; + } + inline void setDisableSupportForMultiGpuPartialWritesForStatelessMessages(const bool value) { + TheStructure.Common.DisableSupportForMultiGpuPartialWritesForStatelessMessages = value; + } + inline bool getDisableSupportForMultiGpuPartialWritesForStatelessMessages() const { + return TheStructure.Common.DisableSupportForMultiGpuPartialWritesForStatelessMessages; + } + inline void setStatelessDataPortAccessMemoryObjectControlStateIndexToMocsTables(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x7f); + TheStructure.Common.StatelessDataPortAccessMemoryObjectControlStateIndexToMocsTables = (value >> 1); // patched + } + inline uint32_t getStatelessDataPortAccessMemoryObjectControlStateIndexToMocsTables() const { + return TheStructure.Common.StatelessDataPortAccessMemoryObjectControlStateIndexToMocsTables << 1; // patched + } + inline void setStatelessDataPortAccessMemoryObjectControlState(const uint32_t value) { // patched + TheStructure.Common.StatelessDataPortAccessMemoryObjectControlStateReserved_112 = value; + TheStructure.Common.StatelessDataPortAccessMemoryObjectControlStateIndexToMocsTables = (value >> 1); + } + inline uint32_t getStatelessDataPortAccessMemoryObjectControlState() const { // patched + uint32_t mocs = TheStructure.Common.StatelessDataPortAccessMemoryObjectControlStateReserved_112; + mocs |= TheStructure.Common.StatelessDataPortAccessMemoryObjectControlStateIndexToMocsTables << 1; + return (mocs); + } + inline void setL1CachePolicyL1CacheControl(const L1_CACHE_POLICY value) { + TheStructure.Common.L1CachePolicyL1CacheControl = value; + } + inline L1_CACHE_POLICY getL1CachePolicyL1CacheControl() const { + return static_cast(TheStructure.Common.L1CachePolicyL1CacheControl); + } + + inline void setSurfaceStateBaseAddressModifyEnable(const bool value) { + TheStructure.Common.SurfaceStateBaseAddressModifyEnable = value; + } + inline bool getSurfaceStateBaseAddressModifyEnable() const { + return TheStructure.Common.SurfaceStateBaseAddressModifyEnable; + } + inline void setSurfaceStateMemoryObjectControlStateIndexToMocsTables(const uint64_t value) { + UNRECOVERABLE_IF(value > 0x7fL); + TheStructure.Common.SurfaceStateMemoryObjectControlStateIndexToMocsTables = (value >> 1); // patched + } + inline uint64_t getSurfaceStateMemoryObjectControlStateIndexToMocsTables() const { + return TheStructure.Common.SurfaceStateMemoryObjectControlStateIndexToMocsTables << 1; // patched + } + typedef enum tagSURFACESTATEBASEADDRESS { + SURFACESTATEBASEADDRESS_BIT_SHIFT = 0xc, + SURFACESTATEBASEADDRESS_ALIGN_SIZE = 0x1000, + } SURFACESTATEBASEADDRESS; + inline void setSurfaceStateBaseAddress(const uint64_t value) { + UNRECOVERABLE_IF(value > 0xffffffffffffffffL); + TheStructure.Common.SurfaceStateBaseAddress = value >> SURFACESTATEBASEADDRESS_BIT_SHIFT; + } + inline uint64_t getSurfaceStateBaseAddress() const { + return TheStructure.Common.SurfaceStateBaseAddress << SURFACESTATEBASEADDRESS_BIT_SHIFT; + } + inline void setDynamicStateBaseAddressModifyEnable(const bool value) { + TheStructure.Common.DynamicStateBaseAddressModifyEnable = value; + } + inline bool getDynamicStateBaseAddressModifyEnable() const { + return TheStructure.Common.DynamicStateBaseAddressModifyEnable; + } + inline void setDynamicStateMemoryObjectControlStateIndexToMocsTables(const uint64_t value) { + UNRECOVERABLE_IF(value > 0x7fL); + TheStructure.Common.DynamicStateMemoryObjectControlStateIndexToMocsTables = (value >> 1); // patched + } + inline uint64_t getDynamicStateMemoryObjectControlStateIndexToMocsTables() const { + return TheStructure.Common.DynamicStateMemoryObjectControlStateIndexToMocsTables << 1; // patched + } + typedef enum tagDYNAMICSTATEBASEADDRESS { + DYNAMICSTATEBASEADDRESS_BIT_SHIFT = 0xc, + DYNAMICSTATEBASEADDRESS_ALIGN_SIZE = 0x1000, + } DYNAMICSTATEBASEADDRESS; + inline void setDynamicStateBaseAddress(const uint64_t value) { + UNRECOVERABLE_IF(value > 0xffffffffffffffffL); + TheStructure.Common.DynamicStateBaseAddress = value >> DYNAMICSTATEBASEADDRESS_BIT_SHIFT; + } + inline uint64_t getDynamicStateBaseAddress() const { + return TheStructure.Common.DynamicStateBaseAddress << DYNAMICSTATEBASEADDRESS_BIT_SHIFT; + } + inline void setInstructionBaseAddressModifyEnable(const bool value) { + TheStructure.Common.InstructionBaseAddressModifyEnable = value; + } + inline bool getInstructionBaseAddressModifyEnable() const { + return TheStructure.Common.InstructionBaseAddressModifyEnable; + } + inline void setInstructionMemoryObjectControlStateIndexToMocsTables(const uint64_t value) { + UNRECOVERABLE_IF(value > 0x7fL); + TheStructure.Common.InstructionMemoryObjectControlStateIndexToMocsTables = (value >> 1); // patched + } + inline uint64_t getInstructionMemoryObjectControlStateIndexToMocsTables() const { + return TheStructure.Common.InstructionMemoryObjectControlStateIndexToMocsTables << 1; //patched + } + inline void setInstructionMemoryObjectControlState(const uint32_t value) { // patched + uint64_t val = static_cast(value); + TheStructure.Common.InstructionMemoryObjectControlStateReserved_324 = val; + TheStructure.Common.InstructionMemoryObjectControlStateIndexToMocsTables = (val >> 1); + } + inline uint32_t getInstructionMemoryObjectControlState() const { // patched + uint64_t mocs = TheStructure.Common.InstructionMemoryObjectControlStateReserved_324; + mocs |= (TheStructure.Common.InstructionMemoryObjectControlStateIndexToMocsTables << 1); + return static_cast(mocs); + } + typedef enum tagINSTRUCTIONBASEADDRESS { + INSTRUCTIONBASEADDRESS_BIT_SHIFT = 0xc, + INSTRUCTIONBASEADDRESS_ALIGN_SIZE = 0x1000, + } INSTRUCTIONBASEADDRESS; + inline void setInstructionBaseAddress(const uint64_t value) { + UNRECOVERABLE_IF(value > 0xffffffffffffffffL); + TheStructure.Common.InstructionBaseAddress = value >> INSTRUCTIONBASEADDRESS_BIT_SHIFT; + } + inline uint64_t getInstructionBaseAddress() const { + return TheStructure.Common.InstructionBaseAddress << INSTRUCTIONBASEADDRESS_BIT_SHIFT; + } + inline void setGeneralStateBufferSizeModifyEnable(const bool value) { + TheStructure.Common.GeneralStateBufferSizeModifyEnable = value; + } + inline bool getGeneralStateBufferSizeModifyEnable() const { + return TheStructure.Common.GeneralStateBufferSizeModifyEnable; + } + inline void setGeneralStateBufferSize(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xfffff); + TheStructure.Common.GeneralStateBufferSize = value; + } + inline uint32_t getGeneralStateBufferSize() const { + return TheStructure.Common.GeneralStateBufferSize; + } + inline void setDynamicStateBufferSizeModifyEnable(const bool value) { + TheStructure.Common.DynamicStateBufferSizeModifyEnable = value; + } + inline bool getDynamicStateBufferSizeModifyEnable() const { + return TheStructure.Common.DynamicStateBufferSizeModifyEnable; + } + inline void setDynamicStateBufferSize(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xfffff); + TheStructure.Common.DynamicStateBufferSize = value; + } + inline uint32_t getDynamicStateBufferSize() const { + return TheStructure.Common.DynamicStateBufferSize; + } + inline void setIndirectObjectBufferSizeModifyEnable(const bool value) { + TheStructure.Common.IndirectObjectBufferSizeModifyEnable = value; + } + inline bool getIndirectObjectBufferSizeModifyEnable() const { + return TheStructure.Common.IndirectObjectBufferSizeModifyEnable; + } + inline void setIndirectObjectBufferSize(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xfffff); + TheStructure.Common.IndirectObjectBufferSize = value; + } + inline uint32_t getIndirectObjectBufferSize() const { + return TheStructure.Common.IndirectObjectBufferSize; + } + inline void setInstructionBufferSizeModifyEnable(const bool value) { + TheStructure.Common.InstructionBufferSizeModifyEnable = value; + } + inline bool getInstructionBufferSizeModifyEnable() const { + return TheStructure.Common.InstructionBufferSizeModifyEnable; + } + inline void setInstructionBufferSize(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xfffff); + TheStructure.Common.InstructionBufferSize = value; + } + inline uint32_t getInstructionBufferSize() const { + return TheStructure.Common.InstructionBufferSize; + } + inline void setBindlessSurfaceStateBaseAddressModifyEnable(const bool value) { + TheStructure.Common.BindlessSurfaceStateBaseAddressModifyEnable = value; + } + inline bool getBindlessSurfaceStateBaseAddressModifyEnable() const { + return TheStructure.Common.BindlessSurfaceStateBaseAddressModifyEnable; + } + inline void setBindlessSurfaceStateMemoryObjectControlStateIndexToMocsTables(const uint64_t value) { + UNRECOVERABLE_IF((value >> 1) > 0x3fL); + TheStructure.Common.BindlessSurfaceStateMemoryObjectControlStateIndexToMocsTables = value >> 1; + } + inline uint64_t getBindlessSurfaceStateMemoryObjectControlStateIndexToMocsTables() const { + return (TheStructure.Common.BindlessSurfaceStateMemoryObjectControlStateIndexToMocsTables << 1); + } + typedef enum tagBINDLESSSURFACESTATEBASEADDRESS { + BINDLESSSURFACESTATEBASEADDRESS_BIT_SHIFT = 0xc, + BINDLESSSURFACESTATEBASEADDRESS_ALIGN_SIZE = 0x1000, + } BINDLESSSURFACESTATEBASEADDRESS; + inline void setBindlessSurfaceStateBaseAddress(const uint64_t value) { + UNRECOVERABLE_IF(value > 0xffffffffffffffffL); + TheStructure.Common.BindlessSurfaceStateBaseAddress = value >> BINDLESSSURFACESTATEBASEADDRESS_BIT_SHIFT; + } + inline uint64_t getBindlessSurfaceStateBaseAddress() const { + return TheStructure.Common.BindlessSurfaceStateBaseAddress << BINDLESSSURFACESTATEBASEADDRESS_BIT_SHIFT; + } + inline void setBindlessSurfaceStateSize(const uint32_t value) { + TheStructure.Common.BindlessSurfaceStateSize = value; + } + inline uint32_t getBindlessSurfaceStateSize() const { + return TheStructure.Common.BindlessSurfaceStateSize; + } + inline void setBindlessSamplerStateBaseAddressModifyEnable(const bool value) { + TheStructure.Common.BindlessSamplerStateBaseAddressModifyEnable = value; + } + inline bool getBindlessSamplerStateBaseAddressModifyEnable() const { + return TheStructure.Common.BindlessSamplerStateBaseAddressModifyEnable; + } + inline void setBindlessSamplerStateMemoryObjectControlStateReserved(const uint64_t value) { + TheStructure.Common.BindlessSamplerStateMemoryObjectControlStateReserved_612 = value; + } + inline uint64_t getBindlessSamplerStateMemoryObjectControlStateReserved() const { + return (TheStructure.Common.BindlessSamplerStateMemoryObjectControlStateReserved_612); + } + inline void setBindlessSamplerStateMemoryObjectControlStateIndexToMocsTables(const uint64_t value) { + UNRECOVERABLE_IF((value >> 1) > 0x3fL); + TheStructure.Common.BindlessSamplerStateMemoryObjectControlStateIndexToMocsTables = value >> 1; + } + inline uint64_t getBindlessSamplerStateMemoryObjectControlStateIndexToMocsTables() const { + return (TheStructure.Common.BindlessSamplerStateMemoryObjectControlStateIndexToMocsTables << 1); + } + typedef enum tagBINDLESSSAMPLERSTATEBASEADDRESS { + BINDLESSSAMPLERSTATEBASEADDRESS_BIT_SHIFT = 0xc, + BINDLESSSAMPLERSTATEBASEADDRESS_ALIGN_SIZE = 0x1000, + } BINDLESSSAMPLERSTATEBASEADDRESS; + inline void setBindlessSamplerStateBaseAddress(const uint64_t value) { + UNRECOVERABLE_IF(value > 0xffffffffffffffffL); + TheStructure.Common.BindlessSamplerStateBaseAddress = value >> BINDLESSSAMPLERSTATEBASEADDRESS_BIT_SHIFT; + } + inline uint64_t getBindlessSamplerStateBaseAddress() const { + return TheStructure.Common.BindlessSamplerStateBaseAddress << BINDLESSSAMPLERSTATEBASEADDRESS_BIT_SHIFT; + } + inline void setBindlessSamplerStateBufferSize(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xfffff); + TheStructure.Common.BindlessSamplerStateBufferSize = value; + } + inline uint32_t getBindlessSamplerStateBufferSize() const { + return TheStructure.Common.BindlessSamplerStateBufferSize; + } +} STATE_BASE_ADDRESS; +STATIC_ASSERT(88 == sizeof(STATE_BASE_ADDRESS)); + +typedef struct tagMI_REPORT_PERF_COUNT { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 5); + uint32_t Reserved_6 : BITFIELD_RANGE(6, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint64_t UseGlobalGtt : BITFIELD_RANGE(0, 0); + uint64_t Reserved_33 : BITFIELD_RANGE(1, 3); + uint64_t CoreModeEnable : BITFIELD_RANGE(4, 4); + uint64_t Reserved_37 : BITFIELD_RANGE(5, 5); + uint64_t MemoryAddress : BITFIELD_RANGE(6, 63); + // DWORD 3 + uint32_t ReportId; + } Common; + uint32_t RawData[4]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x2, + } DWORD_LENGTH; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_REPORT_PERF_COUNT = 0x28, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + typedef enum tagPATCH_CONSTANTS { + MEMORYADDRESS_BYTEOFFSET = 0x4, + MEMORYADDRESS_INDEX = 0x1, + } PATCH_CONSTANTS; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_REPORT_PERF_COUNT; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_REPORT_PERF_COUNT sInit() { + MI_REPORT_PERF_COUNT state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 4); + return TheStructure.RawData[index]; + } + inline void setUseGlobalGtt(const bool value) { + TheStructure.Common.UseGlobalGtt = value; + } + inline bool getUseGlobalGtt() const { + return TheStructure.Common.UseGlobalGtt; + } + inline void setCoreModeEnable(const bool value) { + TheStructure.Common.CoreModeEnable = value; + } + inline bool getCoreModeEnable() const { + return TheStructure.Common.CoreModeEnable; + } + typedef enum tagMEMORYADDRESS { + MEMORYADDRESS_BIT_SHIFT = 0x6, + MEMORYADDRESS_ALIGN_SIZE = 0x40, + } MEMORYADDRESS; + inline void setMemoryAddress(const uint64_t value) { + UNRECOVERABLE_IF(value > 0xffffffffffffffffL); + TheStructure.Common.MemoryAddress = value >> MEMORYADDRESS_BIT_SHIFT; + } + inline uint64_t getMemoryAddress() const { + return TheStructure.Common.MemoryAddress << MEMORYADDRESS_BIT_SHIFT; + } + inline void setReportId(const uint32_t value) { + TheStructure.Common.ReportId = value; + } + inline uint32_t getReportId() const { + return TheStructure.Common.ReportId; + } +} MI_REPORT_PERF_COUNT; +STATIC_ASSERT(16 == sizeof(MI_REPORT_PERF_COUNT)); + +struct MI_USER_INTERRUPT { + union tagTheStructure { + struct tagCommon { + uint32_t Reserved_0 : BITFIELD_RANGE(0, 22); + uint32_t MICommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + } Common; + uint32_t RawData[1]; + } TheStructure; + enum MI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_USER_INTERRUPT = 2, + }; + enum COMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0, + }; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.MICommandOpcode = MI_COMMAND_OPCODE_MI_USER_INTERRUPT; + } + static MI_USER_INTERRUPT sInit() { + MI_USER_INTERRUPT state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + return TheStructure.RawData[index]; + } +}; +STATIC_ASSERT(4 == sizeof(MI_USER_INTERRUPT)); + +typedef struct tagMI_SET_PREDICATE { + union tagTheStructure { + struct tagCommon { + uint32_t PredicateEnable : BITFIELD_RANGE(0, 3); + uint32_t PredicateEnableWparid : BITFIELD_RANGE(4, 5); + uint32_t Reserved_6 : BITFIELD_RANGE(6, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + } Common; + uint32_t RawData[1]; + } TheStructure; + typedef enum tagPREDICATE_ENABLE { + PREDICATE_ENABLE_PREDICATE_DISABLE = 0x0, + PREDICATE_ENABLE_PREDICATE_ON_CLEAR = 0x1, + PREDICATE_ENABLE_PREDICATE_ON_SET = 0x2, + PREDICATE_ENABLE_NOOP_ALWAYS = 0xf, + } PREDICATE_ENABLE; + typedef enum tagPREDICATE_ENABLE_WPARID { + PREDICATE_ENABLE_WPARID_NOOP_NEVER = 0x0, + PREDICATE_ENABLE_WPARID_NOOP_ON_ZERO_VALUE = 0x1, + PREDICATE_ENABLE_WPARID_NOOP_ON_NON_ZERO_VALUE = 0x2, + } PREDICATE_ENABLE_WPARID; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_SET_PREDICATE = 0x1, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.PredicateEnable = PREDICATE_ENABLE_PREDICATE_DISABLE; + TheStructure.Common.PredicateEnableWparid = PREDICATE_ENABLE_WPARID_NOOP_NEVER; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_SET_PREDICATE; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_SET_PREDICATE sInit() { + MI_SET_PREDICATE state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 1); + return TheStructure.RawData[index]; + } + inline void setPredicateEnable(const PREDICATE_ENABLE value) { + TheStructure.Common.PredicateEnable = value; + } + inline PREDICATE_ENABLE getPredicateEnable() const { + return static_cast(TheStructure.Common.PredicateEnable); + } + inline void setPredicateEnableWparid(const PREDICATE_ENABLE_WPARID value) { + TheStructure.Common.PredicateEnableWparid = value; + } + inline PREDICATE_ENABLE_WPARID getPredicateEnableWparid() const { + return static_cast(TheStructure.Common.PredicateEnableWparid); + } +} MI_SET_PREDICATE; +STATIC_ASSERT(4 == sizeof(MI_SET_PREDICATE)); + +typedef struct tagMI_CONDITIONAL_BATCH_BUFFER_END { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 11); + uint32_t CompareOperation : BITFIELD_RANGE(12, 14); + uint32_t PredicateEnable : BITFIELD_RANGE(15, 15); + uint32_t Reserved_16 : BITFIELD_RANGE(16, 17); + uint32_t EndCurrentBatchBufferLevel : BITFIELD_RANGE(18, 18); + uint32_t CompareMaskMode : BITFIELD_RANGE(19, 19); + uint32_t Reserved_20 : BITFIELD_RANGE(20, 20); + uint32_t CompareSemaphore : BITFIELD_RANGE(21, 21); + uint32_t UseGlobalGtt : BITFIELD_RANGE(22, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint32_t CompareDataDword; + // DWORD 2 + uint64_t Reserved_64 : BITFIELD_RANGE(0, 2); + uint64_t CompareAddress : BITFIELD_RANGE(3, 56); + uint64_t CompareAddressReserved_121 : BITFIELD_RANGE(57, 63); + } Common; + uint32_t RawData[4]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x2, + } DWORD_LENGTH; + typedef enum tagCOMPARE_OPERATION { + COMPARE_OPERATION_MAD_GREATER_THAN_IDD = 0x0, + COMPARE_OPERATION_MAD_GREATER_THAN_OR_EQUAL_IDD = 0x1, + COMPARE_OPERATION_MAD_LESS_THAN_IDD = 0x2, + COMPARE_OPERATION_MAD_LESS_THAN_OR_EQUAL_IDD = 0x3, + COMPARE_OPERATION_MAD_EQUAL_IDD = 0x4, + COMPARE_OPERATION_MAD_NOT_EQUAL_IDD = 0x5, + } COMPARE_OPERATION; + typedef enum tagCOMPARE_MASK_MODE { + COMPARE_MASK_MODE_COMPARE_MASK_MODE_DISABLED = 0x0, + COMPARE_MASK_MODE_COMPARE_MASK_MODE_ENABLED = 0x1, + } COMPARE_MASK_MODE; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_CONDITIONAL_BATCH_BUFFER_END = 0x36, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.CompareOperation = COMPARE_OPERATION_MAD_GREATER_THAN_IDD; + TheStructure.Common.CompareMaskMode = COMPARE_MASK_MODE_COMPARE_MASK_MODE_DISABLED; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_CONDITIONAL_BATCH_BUFFER_END; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_CONDITIONAL_BATCH_BUFFER_END sInit() { + MI_CONDITIONAL_BATCH_BUFFER_END state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 4); + return TheStructure.RawData[index]; + } + inline void setCompareOperation(const COMPARE_OPERATION value) { + TheStructure.Common.CompareOperation = value; + } + inline COMPARE_OPERATION getCompareOperation() const { + return static_cast(TheStructure.Common.CompareOperation); + } + inline void setPredicateEnable(const bool value) { + TheStructure.Common.PredicateEnable = value; + } + inline bool getPredicateEnable() const { + return TheStructure.Common.PredicateEnable; + } + inline void setEndCurrentBatchBufferLevel(const bool value) { + TheStructure.Common.EndCurrentBatchBufferLevel = value; + } + inline bool getEndCurrentBatchBufferLevel() const { + return TheStructure.Common.EndCurrentBatchBufferLevel; + } + inline void setCompareMaskMode(const COMPARE_MASK_MODE value) { + TheStructure.Common.CompareMaskMode = value; + } + inline COMPARE_MASK_MODE getCompareMaskMode() const { + return static_cast(TheStructure.Common.CompareMaskMode); + } + inline void setCompareSemaphore(const bool value) { + TheStructure.Common.CompareSemaphore = value; + } + inline bool getCompareSemaphore() const { + return TheStructure.Common.CompareSemaphore; + } + inline void setUseGlobalGtt(const bool value) { + TheStructure.Common.UseGlobalGtt = value; + } + inline bool getUseGlobalGtt() const { + return TheStructure.Common.UseGlobalGtt; + } + inline void setCompareDataDword(const uint32_t value) { + TheStructure.Common.CompareDataDword = value; + } + inline uint32_t getCompareDataDword() const { + return TheStructure.Common.CompareDataDword; + } + typedef enum tagCOMPAREADDRESS { + COMPAREADDRESS_BIT_SHIFT = 0x3, + COMPAREADDRESS_ALIGN_SIZE = 0x8, + } COMPAREADDRESS; + inline void setCompareAddress(const uint64_t value) { + TheStructure.Common.CompareAddress = value >> COMPAREADDRESS_BIT_SHIFT; + } + inline uint64_t getCompareAddress() const { + return TheStructure.Common.CompareAddress << COMPAREADDRESS_BIT_SHIFT; + } +} MI_CONDITIONAL_BATCH_BUFFER_END; +STATIC_ASSERT(16 == sizeof(MI_CONDITIONAL_BATCH_BUFFER_END)); + +struct XY_BLOCK_COPY_BLT { + union tagTheStructure { + struct tagCommon { + /// DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 8); + uint32_t NumberofMultisamples : BITFIELD_RANGE(9, 11); + uint32_t SpecialModeofOperation : BITFIELD_RANGE(12, 13); + uint32_t Reserved_14 : BITFIELD_RANGE(14, 18); + uint32_t ColorDepth : BITFIELD_RANGE(19, 21); + uint32_t InstructionTarget_Opcode : BITFIELD_RANGE(22, 28); + uint32_t Client : BITFIELD_RANGE(29, 31); + + /// DWORD 1 + uint32_t DestinationPitch : BITFIELD_RANGE(0, 17); + uint32_t DestinationAuxiliarysurfacemode : BITFIELD_RANGE(18, 20); + uint32_t DestinationMOCS : BITFIELD_RANGE(21, 27); + uint32_t DestinationCompressionType : BITFIELD_RANGE(28, 28); + uint32_t DestinationCompressionEnable : BITFIELD_RANGE(29, 29); + uint32_t DestinationTiling : BITFIELD_RANGE(30, 31); + + /// DWORD 2 + uint32_t DestinationX1Coordinate_Left : BITFIELD_RANGE(0, 15); + uint32_t DestinationY1Coordinate_Top : BITFIELD_RANGE(16, 31); + + /// DWORD 3 + uint32_t DestinationX2Coordinate_Right : BITFIELD_RANGE(0, 15); + uint32_t DestinationY2Coordinate_Bottom : BITFIELD_RANGE(16, 31); + + /// DWORD 4..5 + uint64_t DestinationBaseAddress; + + /// DWORD 6 + uint32_t DestinationXoffset : BITFIELD_RANGE(0, 13); + uint32_t Reserved_206 : BITFIELD_RANGE(14, 15); + uint32_t DestinationYoffset : BITFIELD_RANGE(16, 29); + uint32_t Reserved_222 : BITFIELD_RANGE(30, 30); + uint32_t DestinationTargetMemory : BITFIELD_RANGE(31, 31); + + /// DWORD 7 + uint32_t SourceX1Coordinate_Left : BITFIELD_RANGE(0, 15); + uint32_t SourceY1Coordinate_Top : BITFIELD_RANGE(16, 31); + + /// DWORD 8 + uint32_t SourcePitch : BITFIELD_RANGE(0, 17); + uint32_t SourceAuxiliarysurfacemode : BITFIELD_RANGE(18, 20); + uint32_t SourceMOCS : BITFIELD_RANGE(21, 27); + uint32_t SourceCompressionType : BITFIELD_RANGE(28, 28); + uint32_t SourceCompressionEnable : BITFIELD_RANGE(29, 29); + uint32_t SourceTiling : BITFIELD_RANGE(30, 31); + + /// DWORD 9..10 + uint64_t SourceBaseAddress; + + /// DWORD 11 + uint32_t SourceXoffset : BITFIELD_RANGE(0, 13); + uint32_t Reserved_366 : BITFIELD_RANGE(14, 15); + uint32_t SourceYoffset : BITFIELD_RANGE(16, 29); + uint32_t Reserved_382 : BITFIELD_RANGE(30, 30); + uint32_t SourceTargetMemory : BITFIELD_RANGE(31, 31); + + /// DWORD 12 + uint32_t SourceCompressionFormat : BITFIELD_RANGE(0, 4); + uint32_t SourceClearValueEnable : BITFIELD_RANGE(5, 5); + uint32_t SourceClearAddressLow : BITFIELD_RANGE(6, 31); + + /// DWORD 13 + uint32_t SourceClearAddressHigh : BITFIELD_RANGE(0, 15); + uint32_t Reserved_432 : BITFIELD_RANGE(16, 31); + + /// DWORD 14 + uint32_t DestinationCompressionFormat : BITFIELD_RANGE(0, 4); + uint32_t DestinationClearValueEnable : BITFIELD_RANGE(5, 5); + uint32_t DestinationClearAddressLow : BITFIELD_RANGE(6, 31); + + /// DWORD 15 + uint32_t DestinationClearAddressHigh : BITFIELD_RANGE(0, 15); + uint32_t Reserved_496 : BITFIELD_RANGE(16, 31); + + /// DWORD 16 + uint32_t DestinationSurfaceHeight : BITFIELD_RANGE(0, 13); + uint32_t DestinationSurfaceWidth : BITFIELD_RANGE(14, 27); + uint32_t Reserved_540 : BITFIELD_RANGE(28, 28); + uint32_t DestinationSurfaceType : BITFIELD_RANGE(29, 31); + + /// DWORD 17 + uint32_t DestinationLOD : BITFIELD_RANGE(0, 3); + uint32_t DestinationSurfaceQpitch : BITFIELD_RANGE(4, 20); + uint32_t DestinationSurfaceDepth : BITFIELD_RANGE(21, 31); + + /// DWORD 18 + uint32_t DestinationHorizontalAlign : BITFIELD_RANGE(0, 1); + uint32_t Reserved_578 : BITFIELD_RANGE(2, 2); + uint32_t DestinationVerticalAlign : BITFIELD_RANGE(3, 4); + uint32_t DestinationSSID : BITFIELD_RANGE(5, 7); + uint32_t DestinationMipTailStartLOD : BITFIELD_RANGE(8, 11); + uint32_t Reserved_588 : BITFIELD_RANGE(12, 17); + uint32_t DestinationDepthStencilResource : BITFIELD_RANGE(18, 18); + uint32_t Reserved_595 : BITFIELD_RANGE(19, 20); + uint32_t DestinationArrayIndex : BITFIELD_RANGE(21, 31); + + /// DWORD 19 + uint32_t SourceSurfaceHeight : BITFIELD_RANGE(0, 13); + uint32_t SourceSurfaceWidth : BITFIELD_RANGE(14, 27); + uint32_t Reserved_636 : BITFIELD_RANGE(28, 28); + uint32_t SourceSurfaceType : BITFIELD_RANGE(29, 31); + + /// DWORD 20 + uint32_t SourceLOD : BITFIELD_RANGE(0, 3); + uint32_t SourceSurfaceQpitch : BITFIELD_RANGE(4, 20); + uint32_t SourceSurfaceDepth : BITFIELD_RANGE(21, 31); + + /// DWORD 21 + uint32_t SourceHorizontalAlign : BITFIELD_RANGE(0, 1); + uint32_t Reserved_674 : BITFIELD_RANGE(2, 2); + uint32_t SourceVerticalAlign : BITFIELD_RANGE(3, 4); + uint32_t SourceSSID : BITFIELD_RANGE(5, 7); + uint32_t SourceMipTailStartLOD : BITFIELD_RANGE(8, 11); + uint32_t Reserved_684 : BITFIELD_RANGE(12, 17); + uint32_t SourceDepthStencilResource : BITFIELD_RANGE(18, 18); + uint32_t Reserved_691 : BITFIELD_RANGE(19, 20); + uint32_t SourceArrayIndex : BITFIELD_RANGE(21, 31); + + } Common; + uint32_t RawData[22]; + } TheStructure; + + enum DWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 20, + }; + + enum NUMBER_OF_MULTISAMPLES { + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_1 = 0, + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_2 = 1, + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_4 = 2, + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_8 = 3, + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_16 = 4, + }; + + enum SPECIAL_MODE_OF_OPERATION { + SPECIAL_MODE_OF_OPERATION_NONE = 0, + SPECIAL_MODE_OF_OPERATION_FULL_RESOLVE = 1, + SPECIAL_MODE_OF_OPERATION_PARTIAL_RESOLVE = 2, + }; + + enum COLOR_DEPTH { + COLOR_DEPTH_8_BIT_COLOR = 0, + COLOR_DEPTH_16_BIT_COLOR = 1, + COLOR_DEPTH_32_BIT_COLOR = 2, + COLOR_DEPTH_64_BIT_COLOR = 3, + COLOR_DEPTH_96_BIT_COLOR_ONLY_LINEAR_CASE_IS_SUPPORTED = 4, + COLOR_DEPTH_128_BIT_COLOR = 5, + }; + + enum CLIENT { + CLIENT_2D_PROCESSOR = 2, + }; + + enum AUXILIARY_SURFACE_MODE { + AUXILIARY_SURFACE_MODE_AUX_NONE = 0, + AUXILIARY_SURFACE_MODE_AUX_CCS_E = 5, + }; + + enum COMPRESSION_TYPE { + COMPRESSION_TYPE_3D_COMPRESSION = 0, + COMPRESSION_TYPE_MEDIA_COMPRESSION = 1, + }; + + enum COMPRESSION_ENABLE { + COMPRESSION_ENABLE_COMPRESSION_DISABLE = 0, + COMPRESSION_ENABLE_COMPRESSION_ENABLE = 1, + }; + + enum TILING { + TILING_LINEAR = 0, + TILING_TILE4 = 2, + TILING_TILE64 = 3, + }; + + enum TARGET_MEMORY { + TARGET_MEMORY_LOCAL_MEM = 0, + TARGET_MEMORY_SYSTEM_MEM = 1, + }; + + enum CLEAR_VALUE_ENABLE { + CLEAR_VALUE_ENABLE_DISABLE = 0, + CLEAR_VALUE_ENABLE_ENABLE = 1, + }; + + enum SURFACE_TYPE { + SURFACE_TYPE_SURFTYPE_1D = 0, + SURFACE_TYPE_SURFTYPE_2D = 1, + SURFACE_TYPE_SURFTYPE_3D = 2, + SURFACE_TYPE_SURFTYPE_CUBE = 3, + SURFACE_TYPE_SURFTYPE_BUFFER = 4, + SURFACE_TYPE_SURFTYPE_STRBUF = 5, + SURFACE_TYPE_SURFTYPE_NULL = 7, + }; + + enum INSTRUCTIONTARGET_OPCODE { + INSTRUCTIONTARGET_OPCODE_OPCODE = 0x41, + }; + + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH::DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.InstructionTarget_Opcode = INSTRUCTIONTARGET_OPCODE_OPCODE; + TheStructure.Common.Client = CLIENT::CLIENT_2D_PROCESSOR; + } + + static XY_BLOCK_COPY_BLT sInit() { + XY_BLOCK_COPY_BLT state; + state.init(); + return state; + } + + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index < 22); + return TheStructure.RawData[index]; + } + + inline void setNumberofMultisamples(const NUMBER_OF_MULTISAMPLES value) { + TheStructure.Common.NumberofMultisamples = value; + } + + inline NUMBER_OF_MULTISAMPLES getNumberofMultisamples() const { + return static_cast(TheStructure.Common.NumberofMultisamples); + } + + inline void setSpecialModeofOperation(const SPECIAL_MODE_OF_OPERATION value) { + TheStructure.Common.SpecialModeofOperation = value; + } + + inline SPECIAL_MODE_OF_OPERATION getSpecialModeofOperation() const { + return static_cast(TheStructure.Common.SpecialModeofOperation); + } + + inline void setColorDepth(const COLOR_DEPTH value) { + TheStructure.Common.ColorDepth = value; + } + + inline COLOR_DEPTH getColorDepth() const { + return static_cast(TheStructure.Common.ColorDepth); + } + + inline void setInstructionTargetOpcode(const uint32_t value) { + TheStructure.Common.InstructionTarget_Opcode = value; + } + + inline uint32_t getInstructionTargetOpcode() const { + return (TheStructure.Common.InstructionTarget_Opcode); + } + + inline void setClient(const CLIENT value) { + TheStructure.Common.Client = value; + } + + inline CLIENT getClient() const { + return static_cast(TheStructure.Common.Client); + } + + inline void setDestinationPitch(const uint32_t value) { + TheStructure.Common.DestinationPitch = value - 1; + } + + inline uint32_t getDestinationPitch() const { + return (TheStructure.Common.DestinationPitch + 1); + } + + inline void setDestinationAuxiliarysurfacemode(const AUXILIARY_SURFACE_MODE value) { + TheStructure.Common.DestinationAuxiliarysurfacemode = value; + } + + inline AUXILIARY_SURFACE_MODE getDestinationAuxiliarysurfacemode() const { + return static_cast(TheStructure.Common.DestinationAuxiliarysurfacemode); + } + + inline void setDestinationMOCS(const uint32_t value) { + TheStructure.Common.DestinationMOCS = value; + } + + inline uint32_t getDestinationMOCS() const { + return (TheStructure.Common.DestinationMOCS); + } + + inline void setDestinationCompressionType(const COMPRESSION_TYPE value) { + TheStructure.Common.DestinationCompressionType = value; + } + + inline COMPRESSION_TYPE getDestinationCompressionType() const { + return static_cast(TheStructure.Common.DestinationCompressionType); + } + + inline void setDestinationCompressionEnable(const COMPRESSION_ENABLE value) { + TheStructure.Common.DestinationCompressionEnable = value; + } + + inline COMPRESSION_ENABLE getDestinationCompressionEnable() const { + return static_cast(TheStructure.Common.DestinationCompressionEnable); + } + + inline void setDestinationTiling(const TILING value) { + TheStructure.Common.DestinationTiling = value; + } + + inline TILING getDestinationTiling() const { + return static_cast(TheStructure.Common.DestinationTiling); + } + + inline void setDestinationX1CoordinateLeft(const uint32_t value) { + TheStructure.Common.DestinationX1Coordinate_Left = value; + } + + inline uint32_t getDestinationX1CoordinateLeft() const { + return (TheStructure.Common.DestinationX1Coordinate_Left); + } + + inline void setDestinationY1CoordinateTop(const uint32_t value) { + TheStructure.Common.DestinationY1Coordinate_Top = value; + } + + inline uint32_t getDestinationY1CoordinateTop() const { + return (TheStructure.Common.DestinationY1Coordinate_Top); + } + + inline void setDestinationX2CoordinateRight(const uint32_t value) { + TheStructure.Common.DestinationX2Coordinate_Right = value; + } + + inline uint32_t getDestinationX2CoordinateRight() const { + return (TheStructure.Common.DestinationX2Coordinate_Right); + } + + inline void setDestinationY2CoordinateBottom(const uint32_t value) { + TheStructure.Common.DestinationY2Coordinate_Bottom = value; + } + + inline uint32_t getDestinationY2CoordinateBottom() const { + return (TheStructure.Common.DestinationY2Coordinate_Bottom); + } + + inline void setDestinationBaseAddress(const uint64_t value) { + TheStructure.Common.DestinationBaseAddress = value; + } + + inline uint64_t getDestinationBaseAddress() const { + return (TheStructure.Common.DestinationBaseAddress); + } + + inline void setDestinationXoffset(const uint32_t value) { + TheStructure.Common.DestinationXoffset = value; + } + + inline uint32_t getDestinationXoffset() const { + return (TheStructure.Common.DestinationXoffset); + } + + inline void setDestinationYoffset(const uint32_t value) { + TheStructure.Common.DestinationYoffset = value; + } + + inline uint32_t getDestinationYoffset() const { + return (TheStructure.Common.DestinationYoffset); + } + + inline void setDestinationTargetMemory(const TARGET_MEMORY value) { + TheStructure.Common.DestinationTargetMemory = value; + } + + inline TARGET_MEMORY getDestinationTargetMemory() const { + return static_cast(TheStructure.Common.DestinationTargetMemory); + } + + inline void setSourceX1CoordinateLeft(const uint32_t value) { + TheStructure.Common.SourceX1Coordinate_Left = value; + } + + inline uint32_t getSourceX1CoordinateLeft() const { + return (TheStructure.Common.SourceX1Coordinate_Left); + } + + inline void setSourceY1CoordinateTop(const uint32_t value) { + TheStructure.Common.SourceY1Coordinate_Top = value; + } + + inline uint32_t getSourceY1CoordinateTop() const { + return (TheStructure.Common.SourceY1Coordinate_Top); + } + + inline void setSourcePitch(const uint32_t value) { + TheStructure.Common.SourcePitch = value - 1; + } + + inline uint32_t getSourcePitch() const { + return (TheStructure.Common.SourcePitch + 1); + } + + inline void setSourceAuxiliarysurfacemode(const AUXILIARY_SURFACE_MODE value) { + TheStructure.Common.SourceAuxiliarysurfacemode = value; + } + + inline AUXILIARY_SURFACE_MODE getSourceAuxiliarysurfacemode() const { + return static_cast(TheStructure.Common.SourceAuxiliarysurfacemode); + } + + inline void setSourceMOCS(const uint32_t value) { + TheStructure.Common.SourceMOCS = value; + } + + inline uint32_t getSourceMOCS() const { + return (TheStructure.Common.SourceMOCS); + } + + inline void setSourceCompressionType(const COMPRESSION_TYPE value) { + TheStructure.Common.SourceCompressionType = value; + } + + inline COMPRESSION_TYPE getSourceCompressionType() const { + return static_cast(TheStructure.Common.SourceCompressionType); + } + + inline void setSourceCompressionEnable(const COMPRESSION_ENABLE value) { + TheStructure.Common.SourceCompressionEnable = value; + } + + inline COMPRESSION_ENABLE getSourceCompressionEnable() const { + return static_cast(TheStructure.Common.SourceCompressionEnable); + } + + inline void setSourceTiling(const TILING value) { + TheStructure.Common.SourceTiling = value; + } + + inline TILING getSourceTiling() const { + return static_cast(TheStructure.Common.SourceTiling); + } + + inline void setSourceBaseAddress(const uint64_t value) { + TheStructure.Common.SourceBaseAddress = value; + } + + inline uint64_t getSourceBaseAddress() const { + return (TheStructure.Common.SourceBaseAddress); + } + + inline void setSourceXoffset(const uint32_t value) { + TheStructure.Common.SourceXoffset = value; + } + + inline uint32_t getSourceXoffset() const { + return (TheStructure.Common.SourceXoffset); + } + + inline void setSourceYoffset(const uint32_t value) { + TheStructure.Common.SourceYoffset = value; + } + + inline uint32_t getSourceYoffset() const { + return (TheStructure.Common.SourceYoffset); + } + + inline void setSourceTargetMemory(const TARGET_MEMORY value) { + TheStructure.Common.SourceTargetMemory = value; + } + + inline TARGET_MEMORY getSourceTargetMemory() const { + return static_cast(TheStructure.Common.SourceTargetMemory); + } + + inline void setSourceCompressionFormat(const uint32_t value) { + TheStructure.Common.SourceCompressionFormat = value; + } + + inline uint32_t getSourceCompressionFormat() const { + return (TheStructure.Common.SourceCompressionFormat); + } + + inline void setSourceClearValueEnable(const CLEAR_VALUE_ENABLE value) { + TheStructure.Common.SourceClearValueEnable = value; + } + + inline CLEAR_VALUE_ENABLE getSourceClearValueEnable() const { + return static_cast(TheStructure.Common.SourceClearValueEnable); + } + + typedef enum tagCLEARADDRESSLOW { + CLEARADDRESSLOW_BIT_SHIFT = 6, + CLEARADDRESSLOW_ALIGN_SIZE = 64, + } CLEARADDRESSLOW; + + inline void setSourceClearAddressLow(const uint32_t value) { + TheStructure.Common.SourceClearAddressLow = value >> CLEARADDRESSLOW_BIT_SHIFT; + } + + inline uint32_t getSourceClearAddressLow() const { + return (TheStructure.Common.SourceClearAddressLow << CLEARADDRESSLOW_BIT_SHIFT); + } + + inline void setSourceClearAddressHigh(const uint32_t value) { + TheStructure.Common.SourceClearAddressHigh = value; + } + + inline uint32_t getSourceClearAddressHigh() const { + return (TheStructure.Common.SourceClearAddressHigh); + } + + inline void setDestinationCompressionFormat(const uint32_t value) { + TheStructure.Common.DestinationCompressionFormat = value; + } + + inline uint32_t getDestinationCompressionFormat() const { + return (TheStructure.Common.DestinationCompressionFormat); + } + + inline void setDestinationClearValueEnable(const CLEAR_VALUE_ENABLE value) { + TheStructure.Common.DestinationClearValueEnable = value; + } + + inline CLEAR_VALUE_ENABLE getDestinationClearValueEnable() const { + return static_cast(TheStructure.Common.DestinationClearValueEnable); + } + + inline void setDestinationClearAddressLow(const uint32_t value) { + TheStructure.Common.DestinationClearAddressLow = value >> CLEARADDRESSLOW_BIT_SHIFT; + } + + inline uint32_t getDestinationClearAddressLow() const { + return (TheStructure.Common.DestinationClearAddressLow << CLEARADDRESSLOW_BIT_SHIFT); + } + + inline void setDestinationClearAddressHigh(const uint32_t value) { + TheStructure.Common.DestinationClearAddressHigh = value; + } + + inline uint32_t getDestinationClearAddressHigh() const { + return (TheStructure.Common.DestinationClearAddressHigh); + } + + inline void setDestinationSurfaceHeight(const uint32_t value) { + TheStructure.Common.DestinationSurfaceHeight = value - 1; + } + + inline uint32_t getDestinationSurfaceHeight() const { + return (TheStructure.Common.DestinationSurfaceHeight + 1); + } + + inline void setDestinationSurfaceWidth(const uint32_t value) { + TheStructure.Common.DestinationSurfaceWidth = value - 1; + } + + inline uint32_t getDestinationSurfaceWidth() const { + return (TheStructure.Common.DestinationSurfaceWidth + 1); + } + + inline void setDestinationSurfaceType(const SURFACE_TYPE value) { + TheStructure.Common.DestinationSurfaceType = value; + } + + inline SURFACE_TYPE getDestinationSurfaceType() const { + return static_cast(TheStructure.Common.DestinationSurfaceType); + } + + inline void setDestinationLOD(const uint32_t value) { + TheStructure.Common.DestinationLOD = value; + } + + inline uint32_t getDestinationLOD() const { + return (TheStructure.Common.DestinationLOD); + } + + inline void setDestinationSurfaceQpitch(const uint32_t value) { + TheStructure.Common.DestinationSurfaceQpitch = value; + } + + inline uint32_t getDestinationSurfaceQpitch() const { + return (TheStructure.Common.DestinationSurfaceQpitch); + } + + inline void setDestinationSurfaceDepth(const uint32_t value) { + TheStructure.Common.DestinationSurfaceDepth = value; + } + + inline uint32_t getDestinationSurfaceDepth() const { + return (TheStructure.Common.DestinationSurfaceDepth); + } + + inline void setDestinationHorizontalAlign(const uint32_t value) { + TheStructure.Common.DestinationHorizontalAlign = value; + } + + inline uint32_t getDestinationHorizontalAlign() const { + return (TheStructure.Common.DestinationHorizontalAlign); + } + + inline void setDestinationVerticalAlign(const uint32_t value) { + TheStructure.Common.DestinationVerticalAlign = value; + } + + inline uint32_t getDestinationVerticalAlign() const { + return (TheStructure.Common.DestinationVerticalAlign); + } + + inline void setDestinationSSID(const uint32_t value) { + TheStructure.Common.DestinationSSID = value; + } + + inline uint32_t getDestinationSSID() const { + return (TheStructure.Common.DestinationSSID); + } + + inline void setDestinationMipTailStartLOD(const uint32_t value) { + TheStructure.Common.DestinationMipTailStartLOD = value; + } + + inline uint32_t getDestinationMipTailStartLOD() const { + return (TheStructure.Common.DestinationMipTailStartLOD); + } + + inline void setDestinationDepthStencilResource(const uint32_t value) { + TheStructure.Common.DestinationDepthStencilResource = value; + } + + inline uint32_t getDestinationDepthStencilResource() const { + return (TheStructure.Common.DestinationDepthStencilResource); + } + + inline void setDestinationArrayIndex(const uint32_t value) { + TheStructure.Common.DestinationArrayIndex = value - 1; + } + + inline uint32_t getDestinationArrayIndex() const { + return (TheStructure.Common.DestinationArrayIndex + 1); + } + + inline void setSourceSurfaceHeight(const uint32_t value) { + TheStructure.Common.SourceSurfaceHeight = value - 1; + } + + inline uint32_t getSourceSurfaceHeight() const { + return (TheStructure.Common.SourceSurfaceHeight + 1); + } + + inline void setSourceSurfaceWidth(const uint32_t value) { + TheStructure.Common.SourceSurfaceWidth = value - 1; + } + + inline uint32_t getSourceSurfaceWidth() const { + return (TheStructure.Common.SourceSurfaceWidth + 1); + } + + inline void setSourceSurfaceType(const SURFACE_TYPE value) { + TheStructure.Common.SourceSurfaceType = value; + } + + inline SURFACE_TYPE getSourceSurfaceType() const { + return static_cast(TheStructure.Common.SourceSurfaceType); + } + + inline void setSourceLOD(const uint32_t value) { + TheStructure.Common.SourceLOD = value; + } + + inline uint32_t getSourceLOD() const { + return (TheStructure.Common.SourceLOD); + } + + inline void setSourceSurfaceQpitch(const uint32_t value) { + TheStructure.Common.SourceSurfaceQpitch = value; + } + + inline uint32_t getSourceSurfaceQpitch() const { + return (TheStructure.Common.SourceSurfaceQpitch); + } + + inline void setSourceSurfaceDepth(const uint32_t value) { + TheStructure.Common.SourceSurfaceDepth = value - 1; + } + + inline uint32_t getSourceSurfaceDepth() const { + return (TheStructure.Common.SourceSurfaceDepth + 1); + } + + inline void setSourceHorizontalAlign(const uint32_t value) { + TheStructure.Common.SourceHorizontalAlign = value; + } + + inline uint32_t getSourceHorizontalAlign() const { + return (TheStructure.Common.SourceHorizontalAlign); + } + + inline void setSourceVerticalAlign(const uint32_t value) { + TheStructure.Common.SourceVerticalAlign = value; + } + + inline uint32_t getSourceVerticalAlign() const { + return (TheStructure.Common.SourceVerticalAlign); + } + + inline void setSourceSSID(const uint32_t value) { + TheStructure.Common.SourceSSID = value; + } + + inline uint32_t getSourceSSID() const { + return (TheStructure.Common.SourceSSID); + } + + inline void setSourceMipTailStartLOD(const uint32_t value) { + TheStructure.Common.SourceMipTailStartLOD = value; + } + + inline uint32_t getSourceMipTailStartLOD() const { + return (TheStructure.Common.SourceMipTailStartLOD); + } + + inline void setSourceDepthStencilResource(const uint32_t value) { + TheStructure.Common.SourceDepthStencilResource = value; + } + + inline uint32_t getSourceDepthStencilResource() const { + return (TheStructure.Common.SourceDepthStencilResource); + } + + inline void setSourceArrayIndex(const uint32_t value) { + TheStructure.Common.SourceArrayIndex = value - 1; + } + + inline uint32_t getSourceArrayIndex() const { + return (TheStructure.Common.SourceArrayIndex + 1); + } +}; +STATIC_ASSERT(88 == sizeof(XY_BLOCK_COPY_BLT)); + +struct XY_FAST_COLOR_BLT { + union tagTheStructure { + struct tagCommon { + /// DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 8); + uint32_t NumberofMultisamples : BITFIELD_RANGE(9, 11); + uint32_t SpecialModeofOperation : BITFIELD_RANGE(12, 13); + uint32_t Reserved_14 : BITFIELD_RANGE(14, 18); + uint32_t ColorDepth : BITFIELD_RANGE(19, 21); + uint32_t InstructionTarget_Opcode : BITFIELD_RANGE(22, 28); + uint32_t Client : BITFIELD_RANGE(29, 31); + + /// DWORD 1 + uint32_t DestinationPitch : BITFIELD_RANGE(0, 17); + uint32_t DestinationAuxiliarysurfacemode : BITFIELD_RANGE(18, 20); + uint32_t DestinationMOCS : BITFIELD_RANGE(21, 27); + uint32_t DestinationCompressionType : BITFIELD_RANGE(28, 28); + uint32_t DestinationCompressionEnable : BITFIELD_RANGE(29, 29); + uint32_t DestinationTiling : BITFIELD_RANGE(30, 31); + + /// DWORD 2 + uint32_t DestinationX1Coordinate_Left : BITFIELD_RANGE(0, 15); + uint32_t DestinationY1Coordinate_Top : BITFIELD_RANGE(16, 31); + + /// DWORD 3 + uint32_t DestinationX2Coordinate_Right : BITFIELD_RANGE(0, 15); + uint32_t DestinationY2Coordinate_Bottom : BITFIELD_RANGE(16, 31); + + /// DWORD 4..5 + uint64_t DestinationBaseAddress; + + /// DWORD 6 + uint32_t DestinationXoffset : BITFIELD_RANGE(0, 13); + uint32_t Reserved_206 : BITFIELD_RANGE(14, 15); + uint32_t DestinationYoffset : BITFIELD_RANGE(16, 29); + uint32_t Reserved_222 : BITFIELD_RANGE(30, 30); + uint32_t DestinationTargetMemory : BITFIELD_RANGE(31, 31); + + /// DWORD 7 - 10 + uint32_t FillColor[4]; + + // DWORD 11 + uint32_t DestinationCompressionFormat : BITFIELD_RANGE(0, 4); + uint32_t DestinationClearValueEnable : BITFIELD_RANGE(5, 5); + uint32_t DestinationClearAddressLow : BITFIELD_RANGE(6, 31); + + // DWORD 12 + uint32_t DestinationClearAddressHigh : BITFIELD_RANGE(0, 24); + uint32_t Reserved1 : BITFIELD_RANGE(25, 31); + + // DWORD 13 + uint32_t DestinationSurfaceHeight : BITFIELD_RANGE(0, 13); + uint32_t DestinationSurfaceWidth : BITFIELD_RANGE(14, 27); + uint32_t Reserved2 : BITFIELD_RANGE(28, 28); + uint32_t DestinationSurfaceType : BITFIELD_RANGE(29, 31); + + // DWORD 14 + uint32_t DestinationLOD : BITFIELD_RANGE(0, 3); + uint32_t DestinationSurfaceQpitch : BITFIELD_RANGE(4, 18); + uint32_t Reserved3 : BITFIELD_RANGE(19, 20); + uint32_t DestinationSurfaceDepth : BITFIELD_RANGE(21, 31); + + // DWORD 15 + uint32_t DestinationHorizontalAlign : BITFIELD_RANGE(0, 1); + uint32_t Reserved4 : BITFIELD_RANGE(2, 2); + uint32_t DestinationVerticalAlign : BITFIELD_RANGE(3, 4); + uint32_t Reserved5 : BITFIELD_RANGE(5, 7); + uint32_t DestinationMipTailStartLOD : BITFIELD_RANGE(8, 11); + uint32_t Reserved6 : BITFIELD_RANGE(12, 17); + uint32_t DestinationDepthStencilResource : BITFIELD_RANGE(18, 18); + uint32_t Reserved7 : BITFIELD_RANGE(19, 20); + uint32_t DestinationArrayIndex : BITFIELD_RANGE(21, 31); + } Common; + uint32_t RawData[15]; + } TheStructure; + + enum DWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0xE, + }; + + enum NUMBER_OF_MULTISAMPLES { + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_1 = 0, + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_2 = 1, + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_4 = 2, + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_8 = 3, + NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT_16 = 4, + }; + + enum SPECIAL_MODE_OF_OPERATION { + SPECIAL_MODE_OF_OPERATION_NONE = 0, + SPECIAL_MODE_OF_OPERATION_FULL_RESOLVE = 1, + SPECIAL_MODE_OF_OPERATION_PARTIAL_RESOLVE = 2, + }; + + enum COLOR_DEPTH { + COLOR_DEPTH_8_BIT_COLOR = 0, + COLOR_DEPTH_16_BIT_COLOR = 1, + COLOR_DEPTH_32_BIT_COLOR = 2, + COLOR_DEPTH_64_BIT_COLOR = 3, + COLOR_DEPTH_96_BIT_COLOR_ONLY_LINEAR_CASE_IS_SUPPORTED = 4, + COLOR_DEPTH_128_BIT_COLOR = 5, + }; + + enum CLIENT { + CLIENT_2D_PROCESSOR = 2, + }; + + enum DESTINATION_AUXILIARY_SURFACE_MODE { + DESTINATION_AUXILIARY_SURFACE_MODE_AUX_NONE = 0, + DESTINATION_AUXILIARY_SURFACE_MODE_AUX_CCS_E = 5, + }; + + enum DESTINATION_CLEAR_VALUE_ENABLE { + DESTINATION_CLEAR_VALUE_ENABLE_DISABLE = 0, + DESTINATION_CLEAR_VALUE_ENABLE_ENABLE = 1, + }; + + enum DESTINATION_COMPRESSION_TYPE { + DESTINATION_COMPRESSION_TYPE_3D_COMPRESSION = 0, + DESTINATION_COMPRESSION_TYPE_MEDIA_COMPRESSION = 1, + }; + + enum DESTINATION_COMPRESSION_ENABLE { + DESTINATION_COMPRESSION_ENABLE_COMPRESSION_DISABLE = 0, + DESTINATION_COMPRESSION_ENABLE_COMPRESSION_ENABLE = 1, + }; + + enum DESTINATION_TILING { + DESTINATION_TILING_LINEAR = 0, + DESTINATION_TILING_TILE4 = 2, + DESTINATION_TILING_TILE64 = 3, + }; + + enum DESTINATION_TARGET_MEMORY { + DESTINATION_TARGET_MEMORY_LOCAL_MEM = 0, + DESTINATION_TARGET_MEMORY_SYSTEM_MEM = 1, + }; + + enum DESTINATION_SURFACE_TYPE { + DESTINATION_SURFACE_TYPE_1D = 0, + DESTINATION_SURFACE_TYPE_2D = 1, + DESTINATION_SURFACE_TYPE_3D = 2, + DESTINATION_SURFACE_TYPE_CUBE = 3, + }; + enum INSTRUCTIONTARGET_OPCODE { + INSTRUCTIONTARGET_OPCODE_OPCODE = 0x44, + }; + + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH::DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.InstructionTarget_Opcode = INSTRUCTIONTARGET_OPCODE::INSTRUCTIONTARGET_OPCODE_OPCODE; + TheStructure.Common.Client = CLIENT::CLIENT_2D_PROCESSOR; + } + + static XY_FAST_COLOR_BLT sInit() { + XY_FAST_COLOR_BLT state; + state.init(); + return state; + } + + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index < 22); + return TheStructure.RawData[index]; + } + + inline void setNumberofMultisamples(const NUMBER_OF_MULTISAMPLES value) { + TheStructure.Common.NumberofMultisamples = value; + } + + inline NUMBER_OF_MULTISAMPLES getNumberofMultisamples() const { + return static_cast(TheStructure.Common.NumberofMultisamples); + } + + inline void setSpecialModeofOperation(const SPECIAL_MODE_OF_OPERATION value) { + TheStructure.Common.SpecialModeofOperation = value; + } + + inline SPECIAL_MODE_OF_OPERATION getSpecialModeofOperation() const { + return static_cast(TheStructure.Common.SpecialModeofOperation); + } + + inline void setColorDepth(const COLOR_DEPTH value) { + TheStructure.Common.ColorDepth = value; + } + + inline COLOR_DEPTH getColorDepth() const { + return static_cast(TheStructure.Common.ColorDepth); + } + + inline void setInstructionTargetOpcode(const uint32_t value) { + TheStructure.Common.InstructionTarget_Opcode = value; + } + + inline uint32_t getInstructionTargetOpcode() const { + return (TheStructure.Common.InstructionTarget_Opcode); + } + + inline void setClient(const CLIENT value) { + TheStructure.Common.Client = value; + } + + inline CLIENT getClient() const { + return static_cast(TheStructure.Common.Client); + } + + inline void setDestinationPitch(const uint32_t value) { + TheStructure.Common.DestinationPitch = value - 1; + } + + inline uint32_t getDestinationPitch() const { + return (TheStructure.Common.DestinationPitch + 1); + } + + inline void setDestinationAuxiliarysurfacemode(const DESTINATION_AUXILIARY_SURFACE_MODE value) { + TheStructure.Common.DestinationAuxiliarysurfacemode = value; + } + + inline DESTINATION_AUXILIARY_SURFACE_MODE getDestinationAuxiliarysurfacemode() const { + return static_cast(TheStructure.Common.DestinationAuxiliarysurfacemode); + } + + inline void setDestinationMOCS(const uint32_t value) { + TheStructure.Common.DestinationMOCS = value; + } + + inline uint32_t getDestinationMOCS() const { + return (TheStructure.Common.DestinationMOCS); + } + + inline void setDestinationCompressionType(const DESTINATION_COMPRESSION_TYPE value) { + TheStructure.Common.DestinationCompressionType = value; + } + + inline DESTINATION_COMPRESSION_TYPE getDestinationCompressionType() const { + return static_cast(TheStructure.Common.DestinationCompressionType); + } + + inline void setDestinationCompressionEnable(const DESTINATION_COMPRESSION_ENABLE value) { + TheStructure.Common.DestinationCompressionEnable = value; + } + + inline DESTINATION_COMPRESSION_ENABLE getDestinationCompressionEnable() const { + return static_cast(TheStructure.Common.DestinationCompressionEnable); + } + + inline void setDestinationTiling(const DESTINATION_TILING value) { + TheStructure.Common.DestinationTiling = value; + } + + inline DESTINATION_TILING getDestinationTiling() const { + return static_cast(TheStructure.Common.DestinationTiling); + } + + inline void setDestinationX1CoordinateLeft(const uint32_t value) { + TheStructure.Common.DestinationX1Coordinate_Left = value; + } + + inline uint32_t getDestinationX1CoordinateLeft() const { + return (TheStructure.Common.DestinationX1Coordinate_Left); + } + + inline void setDestinationY1CoordinateTop(const uint32_t value) { + TheStructure.Common.DestinationY1Coordinate_Top = value; + } + + inline uint32_t getDestinationY1CoordinateTop() const { + return (TheStructure.Common.DestinationY1Coordinate_Top); + } + + inline void setDestinationX2CoordinateRight(const uint32_t value) { + TheStructure.Common.DestinationX2Coordinate_Right = value; + } + + inline uint32_t getDestinationX2CoordinateRight() const { + return (TheStructure.Common.DestinationX2Coordinate_Right); + } + + inline void setDestinationY2CoordinateBottom(const uint32_t value) { + TheStructure.Common.DestinationY2Coordinate_Bottom = value; + } + + inline uint32_t getDestinationY2CoordinateBottom() const { + return (TheStructure.Common.DestinationY2Coordinate_Bottom); + } + + inline void setDestinationBaseAddress(const uint64_t value) { + TheStructure.Common.DestinationBaseAddress = value; + } + + inline uint64_t getDestinationBaseAddress() const { + return (TheStructure.Common.DestinationBaseAddress); + } + + inline void setDestinationXoffset(const uint32_t value) { + TheStructure.Common.DestinationXoffset = value; + } + + inline uint32_t getDestinationXoffset() const { + return (TheStructure.Common.DestinationXoffset); + } + + inline void setDestinationYoffset(const uint32_t value) { + TheStructure.Common.DestinationYoffset = value; + } + + inline uint32_t getDestinationYoffset() const { + return (TheStructure.Common.DestinationYoffset); + } + + inline void setDestinationTargetMemory(const DESTINATION_TARGET_MEMORY value) { + TheStructure.Common.DestinationTargetMemory = value; + } + + inline DESTINATION_TARGET_MEMORY getDestinationTargetMemory() const { + return static_cast(TheStructure.Common.DestinationTargetMemory); + } + + inline void setFillColor(const uint32_t *value) { + TheStructure.Common.FillColor[0] = value[0]; + TheStructure.Common.FillColor[1] = value[1]; + TheStructure.Common.FillColor[2] = value[2]; + TheStructure.Common.FillColor[3] = value[3]; + } + + inline void setDestinationCompressionFormat(const uint32_t value) { + TheStructure.Common.DestinationCompressionFormat = value; + } + + inline uint32_t getDestinationCompressionFormat() const { + return (TheStructure.Common.DestinationCompressionFormat); + } + + inline void setDestinationClearValueEnable(const DESTINATION_CLEAR_VALUE_ENABLE value) { + TheStructure.Common.DestinationClearValueEnable = value; + } + + inline DESTINATION_CLEAR_VALUE_ENABLE getDestinationClearValueEnable() const { + return static_cast(TheStructure.Common.DestinationClearValueEnable); + } + + typedef enum tagDESTINATIONCLEARADDRESSLOW { + DESTINATIONCLEARADDRESSLOW_BIT_SHIFT = 6, + DESTINATIONCLEARADDRESSLOW_ALIGN_SIZE = 64, + } DESTINATIONCLEARADDRESSLOW; + + inline void setDestinationClearAddressLow(const uint32_t value) { + TheStructure.Common.DestinationClearAddressLow = value >> DESTINATIONCLEARADDRESSLOW_BIT_SHIFT; + } + + inline uint32_t getDestinationClearAddressLow() const { + return (TheStructure.Common.DestinationClearAddressLow << DESTINATIONCLEARADDRESSLOW_BIT_SHIFT); + } + + inline void setDestinationClearAddressHigh(const uint32_t value) { + TheStructure.Common.DestinationClearAddressHigh = value; + } + + inline uint32_t getDestinationClearAddressHigh() const { + return (TheStructure.Common.DestinationClearAddressHigh); + } + + inline void setDestinationSurfaceHeight(const uint32_t value) { + TheStructure.Common.DestinationSurfaceHeight = value - 1; + } + + inline uint32_t getDestinationSurfaceHeight() const { + return (TheStructure.Common.DestinationSurfaceHeight + 1); + } + + inline void setDestinationSurfaceWidth(const uint32_t value) { + TheStructure.Common.DestinationSurfaceWidth = value - 1; + } + + inline uint32_t getDestinationSurfaceWidth() const { + return (TheStructure.Common.DestinationSurfaceWidth + 1); + } + + inline void setDestinationSurfaceType(const DESTINATION_SURFACE_TYPE value) { + TheStructure.Common.DestinationSurfaceType = value; + } + + inline DESTINATION_SURFACE_TYPE getDestinationSurfaceType() const { + return static_cast(TheStructure.Common.DestinationSurfaceType); + } + + inline void setDestinationLOD(const uint32_t value) { + TheStructure.Common.DestinationLOD = value; + } + + inline uint32_t getDestinationLOD() const { + return (TheStructure.Common.DestinationLOD); + } + + inline void setDestinationSurfaceQpitch(const uint32_t value) { + TheStructure.Common.DestinationSurfaceQpitch = value; + } + + inline uint32_t getDestinationSurfaceQpitch() const { + return (TheStructure.Common.DestinationSurfaceQpitch); + } + + inline void setDestinationSurfaceDepth(const uint32_t value) { + TheStructure.Common.DestinationSurfaceDepth = value; + } + + inline uint32_t getDestinationSurfaceDepth() const { + return (TheStructure.Common.DestinationSurfaceDepth); + } + + inline void setDestinationHorizontalAlign(const uint32_t value) { + TheStructure.Common.DestinationHorizontalAlign = value; + } + + inline uint32_t getDestinationHorizontalAlign() const { + return (TheStructure.Common.DestinationHorizontalAlign); + } + + inline void setDestinationVerticalAlign(const uint32_t value) { + TheStructure.Common.DestinationVerticalAlign = value; + } + + inline uint32_t getDestinationVerticalAlign() const { + return (TheStructure.Common.DestinationVerticalAlign); + } + + inline void setDestinationMipTailStartLOD(const uint32_t value) { + TheStructure.Common.DestinationMipTailStartLOD = value; + } + + inline uint32_t getDestinationMipTailStartLOD() const { + return (TheStructure.Common.DestinationMipTailStartLOD); + } + + inline void setDestinationDepthStencilResource(const uint32_t value) { + TheStructure.Common.DestinationDepthStencilResource = value; + } + + inline uint32_t getDestinationDepthStencilResource() const { + return (TheStructure.Common.DestinationDepthStencilResource); + } + + inline void setDestinationArrayIndex(const uint32_t value) { + TheStructure.Common.DestinationArrayIndex = value - 1; + } + + inline uint32_t getDestinationArrayIndex() const { + return (TheStructure.Common.DestinationArrayIndex + 1); + } +}; +STATIC_ASSERT(64 == sizeof(XY_FAST_COLOR_BLT)); + +struct MI_FLUSH_DW { + union tagData { + struct tagCommon { + /// DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 5); + uint32_t Reserved_6 : BITFIELD_RANGE(6, 7); + uint32_t NotifyEnable : BITFIELD_RANGE(8, 8); + uint32_t FlushLlc : BITFIELD_RANGE(9, 9); + uint32_t Reserved_10 : BITFIELD_RANGE(10, 13); + uint32_t PostSyncOperation : BITFIELD_RANGE(14, 15); + uint32_t FlushCcs : BITFIELD_RANGE(16, 16); + uint32_t Reserved_17 : BITFIELD_RANGE(17, 17); + uint32_t TlbInvalidate : BITFIELD_RANGE(18, 18); + uint32_t Reserved_19 : BITFIELD_RANGE(19, 20); + uint32_t StoreDataIndex : BITFIELD_RANGE(21, 21); + uint32_t Reserved_22 : BITFIELD_RANGE(22, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + + /// DWORD 1..2 + uint64_t Reserved_32 : BITFIELD_RANGE(0, 1); + uint64_t DestinationAddress : BITFIELD_RANGE(2, 47); + uint64_t Reserved_80 : BITFIELD_RANGE(48, 63); + + /// DWORD 3..4 + uint64_t ImmediateData; + + } Common; + uint32_t RawData[5]; + } TheStructure; + + enum DWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 3, + }; + + enum POST_SYNC_OPERATION { + POST_SYNC_OPERATION_NO_WRITE = 0, + POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA_QWORD = 1, + POST_SYNC_OPERATION_WRITE_TIMESTAMP_REGISTER = 3, + }; + + enum MI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_FLUSH_DW = 38, + }; + + enum COMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0, + }; + + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH::DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE::MI_COMMAND_OPCODE_MI_FLUSH_DW; + } + + static MI_FLUSH_DW sInit() { + MI_FLUSH_DW state; + state.init(); + return state; + } + + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index < 5); + return TheStructure.RawData[index]; + } + + inline void setNotifyEnable(const uint32_t value) { + TheStructure.Common.NotifyEnable = value; + } + + inline uint32_t getNotifyEnable() const { + return (TheStructure.Common.NotifyEnable); + } + + inline void setFlushLlc(const uint32_t value) { + TheStructure.Common.FlushLlc = value; + } + + inline uint32_t getFlushLlc() const { + return (TheStructure.Common.FlushLlc); + } + + inline void setFlushCcs(const uint32_t value) { + TheStructure.Common.FlushCcs = value; + } + + inline uint32_t getFlushCcs() const { + return (TheStructure.Common.FlushCcs); + } + + inline void setPostSyncOperation(const POST_SYNC_OPERATION value) { + TheStructure.Common.PostSyncOperation = value; + } + + inline POST_SYNC_OPERATION getPostSyncOperation() const { + return static_cast(TheStructure.Common.PostSyncOperation); + } + + inline void setTlbInvalidate(const uint32_t value) { + TheStructure.Common.TlbInvalidate = value; + } + + inline uint32_t getTlbInvalidate() const { + return (TheStructure.Common.TlbInvalidate); + } + + inline void setStoreDataIndex(const uint32_t value) { + TheStructure.Common.StoreDataIndex = value; + } + + inline uint32_t getStoreDataIndex() const { + return (TheStructure.Common.StoreDataIndex); + } + + typedef enum tagDESTINATIONADDRESS { + DESTINATIONADDRESS_BIT_SHIFT = 2, + DESTINATIONADDRESS_ALIGN_SIZE = 4, + } DESTINATIONADDRESS; + + inline void setDestinationAddress(const uint64_t value) { + TheStructure.Common.DestinationAddress = value >> DESTINATIONADDRESS_BIT_SHIFT; + } + + inline uint64_t getDestinationAddress() const { + return (TheStructure.Common.DestinationAddress << DESTINATIONADDRESS_BIT_SHIFT); + } + + inline void setImmediateData(const uint64_t value) { + TheStructure.Common.ImmediateData = value; + } + + inline uint64_t getImmediateData() const { + return (TheStructure.Common.ImmediateData); + } +}; +STATIC_ASSERT(20 == sizeof(MI_FLUSH_DW)); + +typedef struct tag_3DSTATE_BTD_BODY { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DispatchTimeoutCounter : BITFIELD_RANGE(0, 1); + uint32_t Reserved_2 : BITFIELD_RANGE(2, 2); + uint32_t AmfsMode : BITFIELD_RANGE(3, 4); + uint32_t Reserved_5 : BITFIELD_RANGE(5, 31); + // DWORD 1 + uint64_t PerDssMemoryBackedBufferSize : BITFIELD_RANGE(0, 2); + uint64_t Reserved_35 : BITFIELD_RANGE(3, 9); + uint64_t MemoryBackedBufferBasePointer : BITFIELD_RANGE(10, 63); + // DWORD 3 + uint64_t PerThreadScratchSpace : BITFIELD_RANGE(0, 3); + uint64_t Reserved_100 : BITFIELD_RANGE(4, 9); + uint64_t BtdScratchSpaceBasePointer : BITFIELD_RANGE(10, 31); + // DWORD 4 + uint64_t Reserved_128 : BITFIELD_RANGE(32, 63); + } Common; + uint32_t RawData[5]; + } TheStructure; + typedef enum tagAMFS_MODE { + AMFS_MODE_NORMAL_MODE = 0x0, + AMFS_MODE_TOUCH_MODE = 0x1, + AMFS_MODE_BACKFILL_MODE = 0x2, + AMFS_MODE_FALLBACK_MODE = 0x3, + } AMFS_MODE; + typedef enum tagPER_DSS_MEMORY_BACKED_BUFFER_SIZE { + PER_DSS_MEMORY_BACKED_BUFFER_SIZE_2KB = 0x0, + PER_DSS_MEMORY_BACKED_BUFFER_SIZE_4KB = 0x1, + PER_DSS_MEMORY_BACKED_BUFFER_SIZE_8KB = 0x2, + PER_DSS_MEMORY_BACKED_BUFFER_SIZE_16KB = 0x3, + PER_DSS_MEMORY_BACKED_BUFFER_SIZE_32KB = 0x4, + PER_DSS_MEMORY_BACKED_BUFFER_SIZE_64KB = 0x5, + PER_DSS_MEMORY_BACKED_BUFFER_SIZE_128KB = 0x6, + } PER_DSS_MEMORY_BACKED_BUFFER_SIZE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.AmfsMode = AMFS_MODE_NORMAL_MODE; + TheStructure.Common.PerDssMemoryBackedBufferSize = PER_DSS_MEMORY_BACKED_BUFFER_SIZE_128KB; + } + static tag_3DSTATE_BTD_BODY sInit() { + _3DSTATE_BTD_BODY state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 5); + return TheStructure.RawData[index]; + } + inline void setDispatchTimeoutCounter(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3); + TheStructure.Common.DispatchTimeoutCounter = value; + } + inline uint32_t getDispatchTimeoutCounter() const { + return TheStructure.Common.DispatchTimeoutCounter; + } + inline void setAmfsMode(const AMFS_MODE value) { + TheStructure.Common.AmfsMode = value; + } + inline AMFS_MODE getAmfsMode() const { + return static_cast(TheStructure.Common.AmfsMode); + } + inline void setPerDssMemoryBackedBufferSize(const PER_DSS_MEMORY_BACKED_BUFFER_SIZE value) { + TheStructure.Common.PerDssMemoryBackedBufferSize = value; + } + inline PER_DSS_MEMORY_BACKED_BUFFER_SIZE getPerDssMemoryBackedBufferSize() const { + return static_cast(TheStructure.Common.PerDssMemoryBackedBufferSize); + } + typedef enum tagMEMORYBACKEDBUFFERBASEPOINTER { + MEMORYBACKEDBUFFERBASEPOINTER_BIT_SHIFT = 0xa, + MEMORYBACKEDBUFFERBASEPOINTER_ALIGN_SIZE = 0x400, + } MEMORYBACKEDBUFFERBASEPOINTER; + inline void setMemoryBackedBufferBasePointer(const uint64_t value) { + UNRECOVERABLE_IF(value > 0xffffffffffffffffL); + TheStructure.Common.MemoryBackedBufferBasePointer = value >> MEMORYBACKEDBUFFERBASEPOINTER_BIT_SHIFT; + } + inline uint64_t getMemoryBackedBufferBasePointer() const { + return TheStructure.Common.MemoryBackedBufferBasePointer << MEMORYBACKEDBUFFERBASEPOINTER_BIT_SHIFT; + } + inline void setPerThreadScratchSpace(const uint64_t value) { + UNRECOVERABLE_IF(value > 0xfL); + TheStructure.Common.PerThreadScratchSpace = value; + } + inline uint64_t getPerThreadScratchSpace() const { + return TheStructure.Common.PerThreadScratchSpace; + } + typedef enum tagBTDSCRATCHSPACEBASEPOINTER { + BTDSCRATCHSPACEBASEPOINTER_BIT_SHIFT = 0xa, + BTDSCRATCHSPACEBASEPOINTER_ALIGN_SIZE = 0x400, + } BTDSCRATCHSPACEBASEPOINTER; + inline void setBtdScratchSpaceBasePointer(const uint64_t value) { + UNRECOVERABLE_IF(value > 0xffffffffL); + TheStructure.Common.BtdScratchSpaceBasePointer = value >> BTDSCRATCHSPACEBASEPOINTER_BIT_SHIFT; + } + inline uint64_t getBtdScratchSpaceBasePointer() const { + return TheStructure.Common.BtdScratchSpaceBasePointer << BTDSCRATCHSPACEBASEPOINTER_BIT_SHIFT; + } +} _3DSTATE_BTD_BODY; +STATIC_ASSERT(20 == sizeof(_3DSTATE_BTD_BODY)); + +typedef struct tag_3DSTATE_BTD { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 15); + uint32_t _3DCommandSubOpcode : BITFIELD_RANGE(16, 23); + uint32_t _3DCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t CommandSubtype : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + _3DSTATE_BTD_BODY BtdStateBody; + } Common; + uint32_t RawData[6]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_DWORD_COUNT_N = 0x4, + } DWORD_LENGTH; + typedef enum tag_3D_COMMAND_SUB_OPCODE { + _3D_COMMAND_SUB_OPCODE_3DSTATE_BTD = 0x6, + } _3D_COMMAND_SUB_OPCODE; + typedef enum tag_3D_COMMAND_OPCODE { + _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED = 0x1, + } _3D_COMMAND_OPCODE; + typedef enum tagCOMMAND_SUBTYPE { + COMMAND_SUBTYPE_GFXPIPE_COMMON = 0x0, + } COMMAND_SUBTYPE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_DWORD_COUNT_N; + TheStructure.Common._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_3DSTATE_BTD; + TheStructure.Common._3DCommandOpcode = _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED; + TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_COMMON; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + TheStructure.Common.BtdStateBody.init(); + } + static tag_3DSTATE_BTD sInit() { + _3DSTATE_BTD state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 6); + return TheStructure.RawData[index]; + } + inline void setBtdStateBody(const _3DSTATE_BTD_BODY &value) { + TheStructure.Common.BtdStateBody = value; + } + inline _3DSTATE_BTD_BODY &getBtdStateBody() { + return TheStructure.Common.BtdStateBody; + } +} _3DSTATE_BTD; +STATIC_ASSERT(24 == sizeof(_3DSTATE_BTD)); +STATIC_ASSERT(std::is_pod<_3DSTATE_BTD>::value); + +typedef struct tagGRF { + union tagTheStructure { + float fRegs[16]; + uint32_t dwRegs[16]; + uint16_t wRegs[32]; + uint32_t RawData[16]; + } TheStructure; +} GRF; +STATIC_ASSERT(64 == sizeof(GRF)); + +typedef struct tagPOSTSYNC_DATA { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t Operation : BITFIELD_RANGE(0, 1); + uint32_t DataportPipelineFlush : BITFIELD_RANGE(2, 2); + uint32_t Reserved_3 : BITFIELD_RANGE(3, 3); + uint32_t MocsReserved_4 : BITFIELD_RANGE(4, 4); + uint32_t MocsIndexToMocsTables : BITFIELD_RANGE(5, 10); + uint32_t SystemMemoryFenceRequest : BITFIELD_RANGE(11, 11); + uint32_t DataportSubsliceCacheFlush : BITFIELD_RANGE(12, 12); + uint32_t Reserved_13 : BITFIELD_RANGE(13, 31); + // DWORD 1 + uint64_t DestinationAddress; + // DWORD 3 + uint64_t ImmediateData; + } Common; + uint32_t RawData[5]; + } TheStructure; + typedef enum tagOPERATION { + OPERATION_NO_WRITE = 0x0, + OPERATION_WRITE_IMMEDIATE_DATA = 0x1, + OPERATION_WRITE_TIMESTAMP = 0x3, + } OPERATION; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.Operation = OPERATION_NO_WRITE; + } + static tagPOSTSYNC_DATA sInit() { + POSTSYNC_DATA state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 5); + return TheStructure.RawData[index]; + } + inline void setOperation(const OPERATION value) { + TheStructure.Common.Operation = value; + } + inline OPERATION getOperation() const { + return static_cast(TheStructure.Common.Operation); + } + inline void setDataportPipelineFlush(const bool value) { + TheStructure.Common.DataportPipelineFlush = value; + } + inline bool getDataportPipelineFlush() const { + return TheStructure.Common.DataportPipelineFlush; + } + inline void setMocs(const uint32_t value) { // patched + UNRECOVERABLE_IF(value > 0x7f); + TheStructure.Common.MocsReserved_4 = value; + TheStructure.Common.MocsIndexToMocsTables = value >> 1; + } + inline uint32_t getMocs() const { // patched + return (TheStructure.Common.MocsIndexToMocsTables << 1) | TheStructure.Common.MocsReserved_4; + } + inline void setSystemMemoryFenceRequest(const bool value) { + TheStructure.Common.SystemMemoryFenceRequest = value; + } + inline bool getSystemMemoryFenceRequest() const { + return TheStructure.Common.SystemMemoryFenceRequest; + } + inline void setDataportSubsliceCacheFlush(const bool value) { + TheStructure.Common.DataportSubsliceCacheFlush = value; + } + inline bool getDataportSubsliceCacheFlush() const { + return TheStructure.Common.DataportSubsliceCacheFlush; + } + inline void setDestinationAddress(const uint64_t value) { + TheStructure.Common.DestinationAddress = value; + } + inline uint64_t getDestinationAddress() const { + return TheStructure.Common.DestinationAddress; + } + inline void setImmediateData(const uint64_t value) { + TheStructure.Common.ImmediateData = value; + } + inline uint64_t getImmediateData() const { + return TheStructure.Common.ImmediateData; + } +} POSTSYNC_DATA; +STATIC_ASSERT(20 == sizeof(POSTSYNC_DATA)); + +typedef struct tagINTERFACE_DESCRIPTOR_DATA { + union tagTheStructure { + struct tagCommon { + uint32_t Reserved_0_0_5 : BITFIELD_RANGE(0, 5); + uint32_t KernelStartPointer : BITFIELD_RANGE(6, 31); + + uint32_t KernelStartPointerHigh : BITFIELD_RANGE(0, 15); + uint32_t Reserved_1_16_31 : BITFIELD_RANGE(16, 31); + + uint32_t Reserved_2_0_6 : BITFIELD_RANGE(0, 6); + uint32_t SoftwareExceptionEnable : BITFIELD_RANGE(7, 7); + uint32_t RegistersPerThread : BITFIELD_RANGE(8, 10); + uint32_t MaskStackExceptionEnable : BITFIELD_RANGE(11, 11); + uint32_t Reserved_2_12_12 : BITFIELD_RANGE(12, 12); + uint32_t IllegalOpcodeExceptionEnable : BITFIELD_RANGE(13, 13); + uint32_t Reserved_2_14_15 : BITFIELD_RANGE(14, 15); + uint32_t FloatingPointMode : BITFIELD_RANGE(16, 16); + uint32_t Reserved_2_17_17 : BITFIELD_RANGE(17, 17); + uint32_t SingleProgramFlow : BITFIELD_RANGE(18, 18); + uint32_t DenormMode : BITFIELD_RANGE(19, 19); + uint32_t ThreadPreemptionDisable : BITFIELD_RANGE(20, 20); + uint32_t Reserved_2_21_31 : BITFIELD_RANGE(21, 31); + + uint32_t Reserved_3_0_1 : BITFIELD_RANGE(0, 1); + uint32_t SamplerCount : BITFIELD_RANGE(2, 4); + uint32_t SamplerStatePointer : BITFIELD_RANGE(5, 31); + + uint32_t BindingTableEntryCount : BITFIELD_RANGE(0, 4); + uint32_t BindingTablePointer : BITFIELD_RANGE(5, 20); + uint32_t Reserved_4_21_31 : BITFIELD_RANGE(21, 31); + + uint32_t NumberOfThreadsInGpgpuThreadGroup : BITFIELD_RANGE(0, 9); + uint32_t Reserved_5_10_15 : BITFIELD_RANGE(10, 15); + uint32_t SharedLocalMemorySize : BITFIELD_RANGE(16, 20); + uint32_t Reserved_5_21_21 : BITFIELD_RANGE(21, 21); + uint32_t RoundingMode : BITFIELD_RANGE(22, 23); + uint32_t Reserved_5_24_25 : BITFIELD_RANGE(24, 25); + uint32_t ThreadGroupDispatchSize : BITFIELD_RANGE(26, 27); + uint32_t NumberOfBarriers : BITFIELD_RANGE(28, 30); + uint32_t Reserved_5_31_31 : BITFIELD_RANGE(31, 31); + + uint32_t PreferredSlmAllocationSizePerDss : BITFIELD_RANGE(0, 2); + uint32_t PreferredSlmSizeOverride : BITFIELD_RANGE(3, 3); + uint32_t Reserved_6_4_31 : BITFIELD_RANGE(4, 31); + + uint32_t Reserved_7; + } Common; + uint32_t RawData[8]; + } TheStructure; + typedef enum tagFLOATING_POINT_MODE { + FLOATING_POINT_MODE_IEEE_754 = 0x0, + FLOATING_POINT_MODE_ALTERNATE = 0x1, + } FLOATING_POINT_MODE; + typedef enum tagSINGLE_PROGRAM_FLOW { + SINGLE_PROGRAM_FLOW_MULTIPLE = 0x0, + SINGLE_PROGRAM_FLOW_SINGLE = 0x1, + } SINGLE_PROGRAM_FLOW; + typedef enum tagDENORM_MODE { + DENORM_MODE_FTZ = 0x0, + DENORM_MODE_SETBYKERNEL = 0x1, + } DENORM_MODE; + typedef enum tagTHREAD_PREEMPTION_DISABLE { + THREAD_PREEMPTION_DISABLE_DISABLE = 0x0, + THREAD_PREEMPTION_DISABLE_ENABLE = 0x1, + } THREAD_PREEMPTION_DISABLE; + typedef enum tagSAMPLER_COUNT { + SAMPLER_COUNT_NO_SAMPLERS_USED = 0x0, + SAMPLER_COUNT_BETWEEN_1_AND_4_SAMPLERS_USED = 0x1, + SAMPLER_COUNT_BETWEEN_5_AND_8_SAMPLERS_USED = 0x2, + SAMPLER_COUNT_BETWEEN_9_AND_12_SAMPLERS_USED = 0x3, + SAMPLER_COUNT_BETWEEN_13_AND_16_SAMPLERS_USED = 0x4, + } SAMPLER_COUNT; + typedef enum tagSHARED_LOCAL_MEMORY_SIZE { + SHARED_LOCAL_MEMORY_SIZE_ENCODES_0K = 0x0, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_1K = 0x1, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_2K = 0x2, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_4K = 0x3, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_8K = 0x4, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_16K = 0x5, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_24K = 0x8, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_32K = 0x6, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_48K = 0x9, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_64K = 0x7, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_96K = 0xA, + SHARED_LOCAL_MEMORY_SIZE_ENCODES_128K = 0xB, + } SHARED_LOCAL_MEMORY_SIZE; + typedef enum tagROUNDING_MODE { + ROUNDING_MODE_RTNE = 0x0, + ROUNDING_MODE_RU = 0x1, + ROUNDING_MODE_RD = 0x2, + ROUNDING_MODE_RTZ = 0x3, + } ROUNDING_MODE; + typedef enum tagREGISTERS_PER_THREAD { + REGISTERS_PER_THREAD_DEFAULT = 0x0, + REGISTERS_PER_THREAD_64_REGISTERS = 0x1, + REGISTERS_PER_THREAD_96_REGISTERS = 0x2, + REGISTERS_PER_THREAD_128_REGISTERS = 0x3, + REGISTERS_PER_THREAD_160_REGISTERS = 0x4, + REGISTERS_PER_THREAD_192_REGISTERS = 0x5, + REGISTERS_PER_THREAD_256_REGISTERS = 0x6, + } REGISTERS_PER_THREAD; + typedef enum tagPREFERRED_SLM_SIZE_OVERRIDE { + PREFERRED_SLM_SIZE_OVERRIDE_IS_DISABLED = 0x0, + PREFERRED_SLM_SIZE_OVERRIDE_IS_ENABLED = 0x1, + } PREFERRED_SLM_SIZE_OVERRIDE; + typedef enum tagPREFERRED_SLM_ALLOCATION_SIZE_PER_DSS { + PREFERRED_SLM_SIZE_IS_0K = 0x0, + PREFERRED_SLM_SIZE_IS_16K = 0x1, + PREFERRED_SLM_SIZE_IS_32K = 0x2, + PREFERRED_SLM_SIZE_IS_64K = 0x3, + PREFERRED_SLM_SIZE_IS_96K = 0x4, + PREFERRED_SLM_SIZE_IS_128K = 0x5, + } PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS; + + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.FloatingPointMode = FLOATING_POINT_MODE_IEEE_754; + TheStructure.Common.SingleProgramFlow = SINGLE_PROGRAM_FLOW_MULTIPLE; + TheStructure.Common.DenormMode = DENORM_MODE_FTZ; + TheStructure.Common.ThreadPreemptionDisable = + THREAD_PREEMPTION_DISABLE_DISABLE; + TheStructure.Common.SamplerCount = SAMPLER_COUNT_NO_SAMPLERS_USED; + TheStructure.Common.SharedLocalMemorySize = + SHARED_LOCAL_MEMORY_SIZE_ENCODES_0K; + TheStructure.Common.RoundingMode = ROUNDING_MODE_RTNE; + TheStructure.Common.RegistersPerThread = REGISTERS_PER_THREAD_DEFAULT; + TheStructure.Common.PreferredSlmSizeOverride = PREFERRED_SLM_SIZE_OVERRIDE_IS_DISABLED; + TheStructure.Common.PreferredSlmAllocationSizePerDss = PREFERRED_SLM_SIZE_IS_0K; + } + static tagINTERFACE_DESCRIPTOR_DATA sInit() { + INTERFACE_DESCRIPTOR_DATA state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 8); + return TheStructure.RawData[index]; + } + typedef enum tagKERNELSTARTPOINTER { + KERNELSTARTPOINTER_BIT_SHIFT = 0x6, + KERNELSTARTPOINTER_ALIGN_SIZE = 0x40, + } KERNELSTARTPOINTER; + inline void setKernelStartPointer(const uint64_t value) { + DEBUG_BREAK_IF(value >= 0x100000000); + TheStructure.Common.KernelStartPointer = (uint32_t)value >> KERNELSTARTPOINTER_BIT_SHIFT; + } + inline uint32_t getKernelStartPointer() const { + return (TheStructure.Common.KernelStartPointer << KERNELSTARTPOINTER_BIT_SHIFT); + } + inline void setKernelStartPointerHigh(const uint32_t value) { + TheStructure.Common.KernelStartPointerHigh = value; + } + inline uint32_t getKernelStartPointerHigh() const { + return (TheStructure.Common.KernelStartPointerHigh); + } + inline void setSoftwareExceptionEnable(const uint32_t value) { + TheStructure.Common.SoftwareExceptionEnable = value; + } + inline uint32_t getSoftwareExceptionEnable() const { + return (TheStructure.Common.SoftwareExceptionEnable); + } + inline void setMaskStackExceptionEnable(const uint32_t value) { + TheStructure.Common.MaskStackExceptionEnable = value; + } + inline uint32_t getMaskStackExceptionEnable() const { + return (TheStructure.Common.MaskStackExceptionEnable); + } + inline void setIllegalOpcodeExceptionEnable(const uint32_t value) { + TheStructure.Common.IllegalOpcodeExceptionEnable = value; + } + inline uint32_t getIllegalOpcodeExceptionEnable() const { + return (TheStructure.Common.IllegalOpcodeExceptionEnable); + } + inline void setFloatingPointMode(const FLOATING_POINT_MODE value) { + TheStructure.Common.FloatingPointMode = value; + } + inline FLOATING_POINT_MODE getFloatingPointMode() const { + return static_cast(TheStructure.Common.FloatingPointMode); + } + inline void setSingleProgramFlow(const SINGLE_PROGRAM_FLOW value) { + TheStructure.Common.SingleProgramFlow = value; + } + inline SINGLE_PROGRAM_FLOW getSingleProgramFlow() const { + return static_cast(TheStructure.Common.SingleProgramFlow); + } + inline void setDenormMode(const DENORM_MODE value) { + TheStructure.Common.DenormMode = value; + } + inline DENORM_MODE getDenormMode() const { + return static_cast(TheStructure.Common.DenormMode); + } + inline void setThreadPreemptionDisable(const THREAD_PREEMPTION_DISABLE value) { + TheStructure.Common.ThreadPreemptionDisable = value; + } + inline THREAD_PREEMPTION_DISABLE getThreadPreemptionDisable() const { + return static_cast(TheStructure.Common.ThreadPreemptionDisable); + } + inline void setSamplerCount(const SAMPLER_COUNT value) { + TheStructure.Common.SamplerCount = value; + } + inline SAMPLER_COUNT getSamplerCount() const { + return static_cast(TheStructure.Common.SamplerCount); + } + typedef enum tagSAMPLERSTATEPOINTER { + SAMPLERSTATEPOINTER_BIT_SHIFT = 0x5, + SAMPLERSTATEPOINTER_ALIGN_SIZE = 0x20, + } SAMPLERSTATEPOINTER; + inline void setSamplerStatePointer(const uint64_t value) { + DEBUG_BREAK_IF(value >= 0x100000000); + TheStructure.Common.SamplerStatePointer = (uint32_t)value >> SAMPLERSTATEPOINTER_BIT_SHIFT; + } + inline uint32_t getSamplerStatePointer() const { + return (TheStructure.Common.SamplerStatePointer << SAMPLERSTATEPOINTER_BIT_SHIFT); + } + inline void setBindingTableEntryCount(const uint32_t value) { + TheStructure.Common.BindingTableEntryCount = value; + } + inline uint32_t getBindingTableEntryCount() const { + return (TheStructure.Common.BindingTableEntryCount); + } + typedef enum tagBINDINGTABLEPOINTER { + BINDINGTABLEPOINTER_BIT_SHIFT = 0x5, + BINDINGTABLEPOINTER_ALIGN_SIZE = 0x20, + } BINDINGTABLEPOINTER; + inline void setBindingTablePointer(const uint64_t value) { + DEBUG_BREAK_IF(value >= 0x100000000); + TheStructure.Common.BindingTablePointer = (uint32_t)value >> BINDINGTABLEPOINTER_BIT_SHIFT; + } + inline uint32_t getBindingTablePointer() const { + return (TheStructure.Common.BindingTablePointer << BINDINGTABLEPOINTER_BIT_SHIFT); + } + inline void setNumberOfThreadsInGpgpuThreadGroup(const uint32_t value) { + UNRECOVERABLE_IF(value > 128); + TheStructure.Common.NumberOfThreadsInGpgpuThreadGroup = value; + } + inline uint32_t getNumberOfThreadsInGpgpuThreadGroup() const { + return (TheStructure.Common.NumberOfThreadsInGpgpuThreadGroup); + } + inline void setSharedLocalMemorySize(const SHARED_LOCAL_MEMORY_SIZE value) { + TheStructure.Common.SharedLocalMemorySize = value; + } + inline SHARED_LOCAL_MEMORY_SIZE getSharedLocalMemorySize() const { + return static_cast(TheStructure.Common.SharedLocalMemorySize); + } + inline void setNumberOfBarriers(const uint32_t value) { + TheStructure.Common.NumberOfBarriers = value; + } + inline uint32_t getNumberOfBarriers() const { + return TheStructure.Common.NumberOfBarriers; + } + inline void setRoundingMode(const ROUNDING_MODE value) { + TheStructure.Common.RoundingMode = value; + } + inline ROUNDING_MODE getRoundingMode() const { + return static_cast(TheStructure.Common.RoundingMode); + } + inline void setThreadGroupDispatchSize(const uint32_t value) { + TheStructure.Common.ThreadGroupDispatchSize = value; + } + inline uint32_t getThreadGroupDispatchSize() const { + return (TheStructure.Common.ThreadGroupDispatchSize); + } + inline void setRegistersPerThread(const REGISTERS_PER_THREAD value) { + TheStructure.Common.RegistersPerThread = value; + } + inline REGISTERS_PER_THREAD getRegistersPerThread() const { + return static_cast(TheStructure.Common.RegistersPerThread); + } + inline void setPreferredSlmSizeOverride(const PREFERRED_SLM_SIZE_OVERRIDE value) { + TheStructure.Common.PreferredSlmSizeOverride = value; + } + inline PREFERRED_SLM_SIZE_OVERRIDE getPreferredSlmSizeOverride() const { + return static_cast(TheStructure.Common.PreferredSlmSizeOverride); + } + inline void setPreferredSlmAllocationSizePerDss(const PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS value) { + TheStructure.Common.PreferredSlmAllocationSizePerDss = value; + } + inline PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS getPreferredSlmAllocationSizePerDss() const { + return static_cast(TheStructure.Common.PreferredSlmAllocationSizePerDss); + } +} INTERFACE_DESCRIPTOR_DATA; +STATIC_ASSERT(32 == sizeof(INTERFACE_DESCRIPTOR_DATA)); + +typedef struct tagINLINE_DATA { + uint32_t RawData[8]; +} INLINE_DATA; +STATIC_ASSERT(32 == sizeof(INLINE_DATA)); + +typedef struct tagCOMPUTE_WALKER { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t PredicateEnable : BITFIELD_RANGE(8, 8); + uint32_t WorkloadPartitionEnable : BITFIELD_RANGE(9, 9); + uint32_t IndirectParameterEnable : BITFIELD_RANGE(10, 10); + uint32_t UavWaitToProduce : BITFIELD_RANGE(11, 11); + uint32_t UavProducer : BITFIELD_RANGE(12, 12); + uint32_t UavConsumer : BITFIELD_RANGE(13, 13); + uint32_t SystolicModeEnable : BITFIELD_RANGE(14, 14); + uint32_t Reserved_15 : BITFIELD_RANGE(15, 15); + uint32_t CfeSubopcodeVariant : BITFIELD_RANGE(16, 17); + uint32_t CfeSubopcode : BITFIELD_RANGE(18, 23); + uint32_t ComputeCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t Pipeline : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint32_t Reserved_32 : BITFIELD_RANGE(0, 7); + uint32_t Reserved_40 : BITFIELD_RANGE(8, 31); + // DWORD 2 + uint32_t IndirectDataLength : BITFIELD_RANGE(0, 16); + uint32_t L3PrefetchDisable : BITFIELD_RANGE(17, 17); + uint32_t Reserved_82 : BITFIELD_RANGE(18, 29); + uint32_t PartitionType : BITFIELD_RANGE(30, 31); + // DWORD 3 + uint32_t Reserved_96 : BITFIELD_RANGE(0, 5); + uint32_t IndirectDataStartAddress : BITFIELD_RANGE(6, 31); + // DWORD 4 + uint32_t Reserved_128 : BITFIELD_RANGE(0, 16); + uint32_t MessageSimd : BITFIELD_RANGE(17, 18); + uint32_t TileLayout : BITFIELD_RANGE(19, 21); + uint32_t WalkOrder : BITFIELD_RANGE(22, 24); + uint32_t EmitInlineParameter : BITFIELD_RANGE(25, 25); + uint32_t EmitLocalId : BITFIELD_RANGE(26, 28); + uint32_t GenerateLocalId : BITFIELD_RANGE(29, 29); + uint32_t SimdSize : BITFIELD_RANGE(30, 31); + // DWORD 5 + uint32_t ExecutionMask; + // DWORD 6 + uint32_t LocalXMaximum : BITFIELD_RANGE(0, 9); + uint32_t LocalYMaximum : BITFIELD_RANGE(10, 19); + uint32_t LocalZMaximum : BITFIELD_RANGE(20, 29); + uint32_t Reserved_222 : BITFIELD_RANGE(30, 31); + // DWORD 7 + uint32_t ThreadGroupIdXDimension; + // DWORD 8 + uint32_t ThreadGroupIdYDimension; + // DWORD 9 + uint32_t ThreadGroupIdZDimension; + // DWORD 10 + uint32_t ThreadGroupIdStartingX; + // DWORD 11 + uint32_t ThreadGroupIdStartingY; + // DWORD 12 + uint32_t ThreadGroupIdStartingZ; + // DWORD 13 + uint64_t PartitionId : BITFIELD_RANGE(0, 31); + // DWORD 14 + uint64_t PartitionSize : BITFIELD_RANGE(32, 63); + // DWORD 15 + uint32_t PreemptX; + // DWORD 16 + uint32_t PreemptY; + // DWORD 17 + uint32_t PreemptZ; + // DWORD 18 + INTERFACE_DESCRIPTOR_DATA InterfaceDescriptor; + // DWORD 26 + POSTSYNC_DATA PostSync; + // DWORD 31 + INLINE_DATA InlineData; + } Common; + uint32_t RawData[39]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_FIXED_SIZE = 0x25, + } DWORD_LENGTH; + typedef enum tagCFE_SUBOPCODE_VARIANT { + CFE_SUBOPCODE_VARIANT_STANDARD = 0x0, + } CFE_SUBOPCODE_VARIANT; + typedef enum tagCFE_SUBOPCODE { + CFE_SUBOPCODE_COMPUTE_WALKER = 0x2, + } CFE_SUBOPCODE; + typedef enum tagCOMPUTE_COMMAND_OPCODE { + COMPUTE_COMMAND_OPCODE_NEW_CFE_COMMAND = 0x2, + } COMPUTE_COMMAND_OPCODE; + typedef enum tagPIPELINE { + PIPELINE_COMPUTE = 0x2, + } PIPELINE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + typedef enum tagPARTITION_TYPE { + PARTITION_TYPE_DISABLED = 0x0, + PARTITION_TYPE_X = 0x1, + PARTITION_TYPE_Y = 0x2, + PARTITION_TYPE_Z = 0x3, + } PARTITION_TYPE; + typedef enum tagSIMD_SIZE { + SIMD_SIZE_SIMT16 = 0x1, + SIMD_SIZE_SIMT32 = 0x2, + } SIMD_SIZE; + typedef enum tagPARTITION_ID { + PARTITION_ID_SUPPORTED_MIN = 0x0, + PARTITION_ID_SUPPORTED_MAX = 0xf, + } PARTITION_ID; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_FIXED_SIZE; + TheStructure.Common.CfeSubopcodeVariant = CFE_SUBOPCODE_VARIANT_STANDARD; + TheStructure.Common.CfeSubopcode = CFE_SUBOPCODE_COMPUTE_WALKER; + TheStructure.Common.ComputeCommandOpcode = COMPUTE_COMMAND_OPCODE_NEW_CFE_COMMAND; + TheStructure.Common.Pipeline = PIPELINE_COMPUTE; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + TheStructure.Common.PartitionType = PARTITION_TYPE_DISABLED; + TheStructure.Common.InterfaceDescriptor.init(); + TheStructure.Common.PostSync.init(); + } + static tagCOMPUTE_WALKER sInit() { + COMPUTE_WALKER state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 39); + return TheStructure.RawData[index]; + } + inline void setDwordLength(const DWORD_LENGTH value) { + TheStructure.Common.DwordLength = value; + } + inline DWORD_LENGTH getDwordLength() const { + return static_cast(TheStructure.Common.DwordLength); + } + inline void setPredicateEnable(const bool value) { + TheStructure.Common.PredicateEnable = value; + } + inline bool getPredicateEnable() const { + return TheStructure.Common.PredicateEnable; + } + inline void setIndirectParameterEnable(const uint32_t value) { + TheStructure.Common.IndirectParameterEnable = value; + } + inline void setUavWaitToProduce(const bool value) { + TheStructure.Common.UavWaitToProduce = value; + } + inline bool getUavWaitToProduce() const { + return TheStructure.Common.UavWaitToProduce; + } + inline void setUavProducer(const bool value) { + TheStructure.Common.UavProducer = value; + } + inline bool getUavProducer() const { + return TheStructure.Common.UavProducer; + } + inline void setUavConsumer(const bool value) { + TheStructure.Common.UavConsumer = value; + } + inline bool getUavConsumer() const { + return TheStructure.Common.UavConsumer; + } + inline void setWorkloadPartitionEnable(const bool value) { + TheStructure.Common.WorkloadPartitionEnable = value; + } + inline bool getWorkloadPartitionEnable() const { + return TheStructure.Common.WorkloadPartitionEnable; + } + inline void setIndirectParameterEnable(const bool value) { + TheStructure.Common.IndirectParameterEnable = value; + } + inline bool getIndirectParameterEnable() const { + return TheStructure.Common.IndirectParameterEnable; + } + inline void setSystolicModeEnable(const bool value) { + TheStructure.Common.SystolicModeEnable = value; + } + inline bool getSystolicModeEnable() const { + return TheStructure.Common.SystolicModeEnable; + } + inline void setCfeSubopcodeVariant(const CFE_SUBOPCODE_VARIANT value) { + TheStructure.Common.CfeSubopcodeVariant = value; + } + inline CFE_SUBOPCODE_VARIANT getCfeSubopcodeVariant() const { + return static_cast(TheStructure.Common.CfeSubopcodeVariant); + } + inline void setCfeSubopcode(const CFE_SUBOPCODE value) { + TheStructure.Common.CfeSubopcode = value; + } + inline CFE_SUBOPCODE getCfeSubopcode() const { + return static_cast(TheStructure.Common.CfeSubopcode); + } + inline void setComputeCommandOpcode(const COMPUTE_COMMAND_OPCODE value) { + TheStructure.Common.ComputeCommandOpcode = value; + } + inline COMPUTE_COMMAND_OPCODE getComputeCommandOpcode() const { + return static_cast(TheStructure.Common.ComputeCommandOpcode); + } + inline void setIndirectDataLength(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x1ffff); + TheStructure.Common.IndirectDataLength = value; + } + inline uint32_t getIndirectDataLength() const { + return TheStructure.Common.IndirectDataLength; + } + inline void setL3PrefetchDisable(const bool value) { + TheStructure.Common.L3PrefetchDisable = value; + } + inline bool getL3PrefetchDisable() const { + return TheStructure.Common.L3PrefetchDisable; + } + inline void setPartitionType(const PARTITION_TYPE value) { + TheStructure.Common.PartitionType = value; + } + inline PARTITION_TYPE getPartitionType() const { + return static_cast(TheStructure.Common.PartitionType); + } + typedef enum tagINDIRECTDATASTARTADDRESS { + INDIRECTDATASTARTADDRESS_BIT_SHIFT = 0x6, + INDIRECTDATASTARTADDRESS_ALIGN_SIZE = 0x40, + } INDIRECTDATASTARTADDRESS; + inline void setIndirectDataStartAddress(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xffffffc0); + TheStructure.Common.IndirectDataStartAddress = value >> INDIRECTDATASTARTADDRESS_BIT_SHIFT; + } + inline uint32_t getIndirectDataStartAddress() const { + return TheStructure.Common.IndirectDataStartAddress << INDIRECTDATASTARTADDRESS_BIT_SHIFT; + } + inline void setMessageSimd(const uint32_t value) { + TheStructure.Common.MessageSimd = value; + } + inline uint32_t getMessageSimd() const { + return (TheStructure.Common.MessageSimd); + } + inline void setTileLayout(const uint32_t value) { + TheStructure.Common.TileLayout = value; + } + inline uint32_t getTileLayout() const { + return (TheStructure.Common.TileLayout); + } + inline void setWalkOrder(const uint32_t value) { + TheStructure.Common.WalkOrder = value; + } + inline uint32_t getWalkOrder() const { + return (TheStructure.Common.WalkOrder); + } + inline void setEmitInlineParameter(const uint32_t value) { + TheStructure.Common.EmitInlineParameter = value; + } + inline uint32_t getEmitInlineParameter() const { + return (TheStructure.Common.EmitInlineParameter); + } + inline void setEmitLocalId(const uint32_t value) { + TheStructure.Common.EmitLocalId = value; + } + inline uint32_t getEmitLocalId() const { + return (TheStructure.Common.EmitLocalId); + } + inline void setGenerateLocalId(const uint32_t value) { + TheStructure.Common.GenerateLocalId = value; + } + inline uint32_t getGenerateLocalId() const { + return (TheStructure.Common.GenerateLocalId); + } + inline void setSimdSize(const SIMD_SIZE value) { + TheStructure.Common.SimdSize = value; + } + inline SIMD_SIZE getSimdSize() const { + return static_cast(TheStructure.Common.SimdSize); + } + inline void setExecutionMask(const uint32_t value) { + TheStructure.Common.ExecutionMask = value; + } + inline uint32_t getExecutionMask() const { + return TheStructure.Common.ExecutionMask; + } + inline void setLocalXMaximum(const uint32_t value) { + TheStructure.Common.LocalXMaximum = value; + } + inline uint32_t getLocalXMaximum() const { + return (TheStructure.Common.LocalXMaximum); + } + inline void setLocalYMaximum(const uint32_t value) { + TheStructure.Common.LocalYMaximum = value; + } + inline uint32_t getLocalYMaximum() const { + return (TheStructure.Common.LocalYMaximum); + } + inline void setLocalZMaximum(const uint32_t value) { + TheStructure.Common.LocalZMaximum = value; + } + inline uint32_t getLocalZMaximum() const { + return (TheStructure.Common.LocalZMaximum); + } + inline void setThreadGroupIdXDimension(const uint32_t value) { + TheStructure.Common.ThreadGroupIdXDimension = value; + } + inline uint32_t getThreadGroupIdXDimension() const { + return TheStructure.Common.ThreadGroupIdXDimension; + } + inline void setThreadGroupIdYDimension(const uint32_t value) { + TheStructure.Common.ThreadGroupIdYDimension = value; + } + inline uint32_t getThreadGroupIdYDimension() const { + return TheStructure.Common.ThreadGroupIdYDimension; + } + inline void setThreadGroupIdZDimension(const uint32_t value) { + TheStructure.Common.ThreadGroupIdZDimension = value; + } + inline uint32_t getThreadGroupIdZDimension() const { + return TheStructure.Common.ThreadGroupIdZDimension; + } + inline void setThreadGroupIdStartingX(const uint32_t value) { + TheStructure.Common.ThreadGroupIdStartingX = value; + } + inline uint32_t getThreadGroupIdStartingX() const { + return TheStructure.Common.ThreadGroupIdStartingX; + } + inline void setThreadGroupIdStartingY(const uint32_t value) { + TheStructure.Common.ThreadGroupIdStartingY = value; + } + inline uint32_t getThreadGroupIdStartingY() const { + return TheStructure.Common.ThreadGroupIdStartingY; + } + inline void setThreadGroupIdStartingZ(const uint32_t value) { + TheStructure.Common.ThreadGroupIdStartingZ = value; + } + inline uint32_t getThreadGroupIdStartingZ() const { + return TheStructure.Common.ThreadGroupIdStartingZ; + } + inline void setPartitionId(const uint64_t value) { + TheStructure.Common.PartitionId = value; + } + inline uint64_t getPartitionId() const { + return TheStructure.Common.PartitionId; + } + inline void setPartitionSize(const uint64_t value) { + TheStructure.Common.PartitionSize = value; + } + inline uint64_t getPartitionSize() const { + return TheStructure.Common.PartitionSize; + } + inline void setPreemptX(const uint32_t value) { + TheStructure.Common.PreemptX = value; + } + inline uint32_t getPreemptX() const { + return TheStructure.Common.PreemptX; + } + inline void setPreemptY(const uint32_t value) { + TheStructure.Common.PreemptY = value; + } + inline uint32_t getPreemptY() const { + return TheStructure.Common.PreemptY; + } + inline void setPreemptZ(const uint32_t value) { + TheStructure.Common.PreemptZ = value; + } + inline uint32_t getPreemptZ() const { + return TheStructure.Common.PreemptZ; + } + inline void setInterfaceDescriptor(const INTERFACE_DESCRIPTOR_DATA &value) { + TheStructure.Common.InterfaceDescriptor = value; + } + inline INTERFACE_DESCRIPTOR_DATA &getInterfaceDescriptor() { + return TheStructure.Common.InterfaceDescriptor; + } + inline void setPostSync(const POSTSYNC_DATA &value) { + TheStructure.Common.PostSync = value; + } + inline POSTSYNC_DATA &getPostSync() { + return TheStructure.Common.PostSync; + } + inline uint32_t *getInlineDataPointer() { + return reinterpret_cast(&TheStructure.Common.InlineData); + } +} COMPUTE_WALKER; +STATIC_ASSERT(156 == sizeof(COMPUTE_WALKER)); + +typedef struct tagCFE_STATE { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 15); + uint32_t CfeSubopcodeVariant : BITFIELD_RANGE(16, 17); + uint32_t CfeSubopcode : BITFIELD_RANGE(18, 23); + uint32_t ComputeCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t Pipeline : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint64_t Reserved_32 : BITFIELD_RANGE(0, 7); + uint64_t Reserved_40 : BITFIELD_RANGE(8, 9); + uint64_t ScratchSpaceBuffer : BITFIELD_RANGE(10, 31); + // DWORD 2 + uint64_t Reserved_64 : BITFIELD_RANGE(32, 63); + // DWORD 3 + uint32_t Reserved_96 : BITFIELD_RANGE(0, 2); + uint32_t NumberOfWalkers : BITFIELD_RANGE(3, 5); + uint32_t FusedEuDispatch : BITFIELD_RANGE(6, 6); + uint32_t Reserved_103 : BITFIELD_RANGE(7, 9); + uint32_t LargeGRFThreadAdjustDisable : BITFIELD_RANGE(10, 10); + uint32_t ComputeOverdispatchDisable : BITFIELD_RANGE(11, 11); + uint32_t ComputeDispatchAllWalkerEnable : BITFIELD_RANGE(12, 12); + uint32_t SingleSliceDispatchCcsMode : BITFIELD_RANGE(13, 13); + uint32_t OverDispatchControl : BITFIELD_RANGE(14, 15); + uint32_t MaximumNumberOfThreads : BITFIELD_RANGE(16, 31); + // DWORD 4 + uint32_t Reserved_128; + // DWORD 5 + uint32_t Reserved_160 : BITFIELD_RANGE(0, 0); + uint32_t Reserved_161 : BITFIELD_RANGE(1, 10); + uint32_t Reserved_171 : BITFIELD_RANGE(11, 31); + } Common; + uint32_t RawData[6]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_DWORD_COUNT_N = 0x4, + } DWORD_LENGTH; + typedef enum tagCFE_SUBOPCODE_VARIANT { + CFE_SUBOPCODE_VARIANT_STANDARD = 0x0, + } CFE_SUBOPCODE_VARIANT; + typedef enum tagCFE_SUBOPCODE { + CFE_SUBOPCODE_CFE_STATE = 0x0, + } CFE_SUBOPCODE; + typedef enum tagCOMPUTE_COMMAND_OPCODE { + COMPUTE_COMMAND_OPCODE_NEW_CFE_COMMAND = 0x2, + } COMPUTE_COMMAND_OPCODE; + typedef enum tagPIPELINE { + PIPELINE_COMPUTE = 0x2, + } PIPELINE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + typedef enum tagOVER_DISPATCH_CONTROL { + OVER_DISPATCH_CONTROL_NONE = 0x0, + OVER_DISPATCH_CONTROL_LOW = 0x1, + OVER_DISPATCH_CONTROL_NORMAL = 0x2, + OVER_DISPATCH_CONTROL_HIGH = 0x3, + } OVER_DISPATCH_CONTROL; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_DWORD_COUNT_N; + TheStructure.Common.CfeSubopcodeVariant = CFE_SUBOPCODE_VARIANT_STANDARD; + TheStructure.Common.CfeSubopcode = CFE_SUBOPCODE_CFE_STATE; + TheStructure.Common.ComputeCommandOpcode = COMPUTE_COMMAND_OPCODE_NEW_CFE_COMMAND; + TheStructure.Common.Pipeline = PIPELINE_COMPUTE; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + TheStructure.Common.OverDispatchControl = OVER_DISPATCH_CONTROL_NORMAL; + } + static tagCFE_STATE sInit() { + CFE_STATE state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 6); + return TheStructure.RawData[index]; + } + inline void setCfeSubopcodeVariant(const CFE_SUBOPCODE_VARIANT value) { + TheStructure.Common.CfeSubopcodeVariant = value; + } + inline CFE_SUBOPCODE_VARIANT getCfeSubopcodeVariant() const { + return static_cast(TheStructure.Common.CfeSubopcodeVariant); + } + inline void setCfeSubopcode(const CFE_SUBOPCODE value) { + TheStructure.Common.CfeSubopcode = value; + } + inline CFE_SUBOPCODE getCfeSubopcode() const { + return static_cast(TheStructure.Common.CfeSubopcode); + } + inline void setComputeCommandOpcode(const COMPUTE_COMMAND_OPCODE value) { + TheStructure.Common.ComputeCommandOpcode = value; + } + inline COMPUTE_COMMAND_OPCODE getComputeCommandOpcode() const { + return static_cast(TheStructure.Common.ComputeCommandOpcode); + } + typedef enum tagSCRATCHSPACEBUFFER { + SCRATCHSPACEBUFFER_BIT_SHIFT = 0x6, + SCRATCHSPACEBUFFER_ALIGN_SIZE = 0x40, + } SCRATCHSPACEBUFFER; + inline void setScratchSpaceBuffer(const uint64_t value) { + UNRECOVERABLE_IF(value > 0xfffffc00L); + TheStructure.Common.ScratchSpaceBuffer = static_cast(value) >> SCRATCHSPACEBUFFER_BIT_SHIFT; + } + inline uint64_t getScratchSpaceBuffer() const { + return TheStructure.Common.ScratchSpaceBuffer << SCRATCHSPACEBUFFER_BIT_SHIFT; + } + inline void setNumberOfWalkers(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x38); + TheStructure.Common.NumberOfWalkers = value - 1; + } + inline uint32_t getNumberOfWalkers() const { + return TheStructure.Common.NumberOfWalkers + 1; + } + inline void setFusedEuDispatch(const bool value) { + TheStructure.Common.FusedEuDispatch = value; + } + inline bool getFusedEuDispatch() const { + return TheStructure.Common.FusedEuDispatch; + } + inline void setLargeGRFThreadAdjustDisable(const bool value) { + TheStructure.Common.LargeGRFThreadAdjustDisable = value; + } + inline bool getLargeGRFThreadAdjustDisable() const { + return TheStructure.Common.LargeGRFThreadAdjustDisable; + } + inline void setComputeOverdispatchDisable(const bool value) { + TheStructure.Common.ComputeOverdispatchDisable = value; + } + inline bool getComputeOverdispatchDisable() const { + return TheStructure.Common.ComputeOverdispatchDisable; + } + inline void setComputeDispatchAllWalkerEnable(const bool value) { + TheStructure.Common.ComputeDispatchAllWalkerEnable = value; + } + inline bool getComputeDispatchAllWalkerEnable() const { + return TheStructure.Common.ComputeDispatchAllWalkerEnable; + } + inline void setSingleSliceDispatchCcsMode(const bool value) { + TheStructure.Common.SingleSliceDispatchCcsMode = value; + } + inline bool getSingleSliceDispatchCcsMode() const { + return TheStructure.Common.SingleSliceDispatchCcsMode; + } + inline void setOverDispatchControl(const OVER_DISPATCH_CONTROL value) { + TheStructure.Common.OverDispatchControl = value; + } + inline OVER_DISPATCH_CONTROL getOverDispatchControl() const { + return static_cast(TheStructure.Common.OverDispatchControl); + } + inline void setMaximumNumberOfThreads(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xffff0000); + TheStructure.Common.MaximumNumberOfThreads = value; + } + inline uint32_t getMaximumNumberOfThreads() const { + return TheStructure.Common.MaximumNumberOfThreads; + } +} CFE_STATE; +STATIC_ASSERT(24 == sizeof(CFE_STATE)); + +typedef struct tagMI_ARB_CHECK { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t PreParserDisable : BITFIELD_RANGE(0, 0); + uint32_t Reserved_1 : BITFIELD_RANGE(1, 7); + uint32_t MaskBits : BITFIELD_RANGE(8, 15); + uint32_t Reserved_16 : BITFIELD_RANGE(16, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + } Common; + uint32_t RawData[1]; + } TheStructure; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_ARB_CHECK = 0x5, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_ARB_CHECK; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_ARB_CHECK sInit() { + MI_ARB_CHECK state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 1); + return TheStructure.RawData[index]; + } + inline void setPreParserDisable(const bool value) { + TheStructure.Common.PreParserDisable = value; + TheStructure.Common.MaskBits = 1 << 0; //PreParserDisable is at bit0, so set bit0 of mask to 1 + } + inline bool getPreParserDisable() const { + return TheStructure.Common.PreParserDisable; + } + inline void setMaskBits(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xff00); + TheStructure.Common.MaskBits = value; + } + inline uint32_t getMaskBits() const { + return TheStructure.Common.MaskBits; + } +} MI_ARB_CHECK; +STATIC_ASSERT(4 == sizeof(MI_ARB_CHECK)); + +typedef struct tagMI_BATCH_BUFFER_START { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t AddressSpaceIndicator : BITFIELD_RANGE(8, 8); + uint32_t Reserved_9 : BITFIELD_RANGE(9, 9); + uint32_t Reserved_10 : BITFIELD_RANGE(10, 14); + uint32_t PredicationEnable : BITFIELD_RANGE(15, 15); + uint32_t Reserved_16 : BITFIELD_RANGE(16, 18); + uint32_t EnableCommandCache : BITFIELD_RANGE(19, 19); + uint32_t PoshEnable : BITFIELD_RANGE(20, 20); + uint32_t PoshStart : BITFIELD_RANGE(21, 21); + uint32_t Reserved_22 : BITFIELD_RANGE(22, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint64_t Reserved_32 : BITFIELD_RANGE(0, 1); + uint64_t BatchBufferStartAddress : BITFIELD_RANGE(2, 56); + uint64_t BatchBufferStartAddressReserved_89 : BITFIELD_RANGE(57, 63); + } Common; + struct tagMi_Mode_Nestedbatchbufferenableis0 { + // DWORD 0 + uint32_t Reserved_0 : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 8); + uint32_t Reserved_9 : BITFIELD_RANGE(9, 9); + uint32_t Reserved_10 : BITFIELD_RANGE(10, 14); + uint32_t Reserved_15 : BITFIELD_RANGE(15, 15); + uint32_t Reserved_16 : BITFIELD_RANGE(16, 18); + uint32_t Reserved_19 : BITFIELD_RANGE(19, 19); + uint32_t Reserved_20 : BITFIELD_RANGE(20, 20); + uint32_t Reserved_21 : BITFIELD_RANGE(21, 21); + uint32_t SecondLevelBatchBuffer : BITFIELD_RANGE(22, 22); + uint32_t Reserved_23 : BITFIELD_RANGE(23, 28); + uint32_t Reserved_29 : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint64_t Reserved_32 : BITFIELD_RANGE(0, 1); + uint64_t Reserved_34 : BITFIELD_RANGE(2, 56); + uint64_t Reserved_89 : BITFIELD_RANGE(57, 63); + } Mi_Mode_Nestedbatchbufferenableis0; + struct tagMi_Mode_Nestedbatchbufferenableis1 { + // DWORD 0 + uint32_t Reserved_0 : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 8); + uint32_t Reserved_9 : BITFIELD_RANGE(9, 9); + uint32_t Reserved_10 : BITFIELD_RANGE(10, 14); + uint32_t Reserved_15 : BITFIELD_RANGE(15, 15); + uint32_t Reserved_16 : BITFIELD_RANGE(16, 18); + uint32_t Reserved_19 : BITFIELD_RANGE(19, 19); + uint32_t Reserved_20 : BITFIELD_RANGE(20, 20); + uint32_t Reserved_21 : BITFIELD_RANGE(21, 21); + uint32_t NestedLevelBatchBuffer : BITFIELD_RANGE(22, 22); + uint32_t Reserved_23 : BITFIELD_RANGE(23, 28); + uint32_t Reserved_29 : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint64_t Reserved_32 : BITFIELD_RANGE(0, 1); + uint64_t Reserved_34 : BITFIELD_RANGE(2, 56); + uint64_t Reserved_89 : BITFIELD_RANGE(57, 63); + } Mi_Mode_Nestedbatchbufferenableis1; + uint32_t RawData[3]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x1, + } DWORD_LENGTH; + typedef enum tagADDRESS_SPACE_INDICATOR { + ADDRESS_SPACE_INDICATOR_GGTT = 0x0, + ADDRESS_SPACE_INDICATOR_PPGTT = 0x1, + } ADDRESS_SPACE_INDICATOR; + typedef enum tagNESTED_LEVEL_BATCH_BUFFER { + NESTED_LEVEL_BATCH_BUFFER_CHAIN = 0x0, + NESTED_LEVEL_BATCH_BUFFER_NESTED = 0x1, + } NESTED_LEVEL_BATCH_BUFFER; + typedef enum tagSECOND_LEVEL_BATCH_BUFFER { + SECOND_LEVEL_BATCH_BUFFER_FIRST_LEVEL_BATCH = 0x0, + SECOND_LEVEL_BATCH_BUFFER_SECOND_LEVEL_BATCH = 0x1, + } SECOND_LEVEL_BATCH_BUFFER; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_BATCH_BUFFER_START = 0x31, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.AddressSpaceIndicator = ADDRESS_SPACE_INDICATOR_GGTT; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_BATCH_BUFFER_START; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + TheStructure.Mi_Mode_Nestedbatchbufferenableis0.SecondLevelBatchBuffer = SECOND_LEVEL_BATCH_BUFFER_FIRST_LEVEL_BATCH; + TheStructure.Mi_Mode_Nestedbatchbufferenableis1.NestedLevelBatchBuffer = NESTED_LEVEL_BATCH_BUFFER_CHAIN; + } + static tagMI_BATCH_BUFFER_START sInit() { + MI_BATCH_BUFFER_START state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 3); + return TheStructure.RawData[index]; + } + inline void setAddressSpaceIndicator(const ADDRESS_SPACE_INDICATOR value) { + TheStructure.Common.AddressSpaceIndicator = value; + } + inline ADDRESS_SPACE_INDICATOR getAddressSpaceIndicator() const { + return static_cast(TheStructure.Common.AddressSpaceIndicator); + } + inline void setPredicationEnable(const uint32_t value) { + TheStructure.Common.PredicationEnable = value; + } + inline uint32_t getPredicationEnable() const { + return TheStructure.Common.PredicationEnable; + } + inline void setEnableCommandCache(const uint32_t value) { + TheStructure.Common.EnableCommandCache = value; + } + inline uint32_t getEnableCommandCache() const { + return TheStructure.Common.EnableCommandCache; + } + inline void setPoshEnable(const uint32_t value) { + TheStructure.Common.PoshEnable = value; + } + inline uint32_t getPoshEnable() const { + return TheStructure.Common.PoshEnable; + } + inline void setPoshStart(const uint32_t value) { + TheStructure.Common.PoshStart = value; + } + inline uint32_t getPoshStart() const { + return TheStructure.Common.PoshStart; + } + typedef enum tagBATCHBUFFERSTARTADDRESS { + BATCHBUFFERSTARTADDRESS_BIT_SHIFT = 0x2, + BATCHBUFFERSTARTADDRESS_ALIGN_SIZE = 0x4, + } BATCHBUFFERSTARTADDRESS; + inline void setBatchBufferStartAddress(const uint64_t value) { + TheStructure.Common.BatchBufferStartAddress = value >> BATCHBUFFERSTARTADDRESS_BIT_SHIFT; + } + inline uint64_t getBatchBufferStartAddress() const { + return TheStructure.Common.BatchBufferStartAddress << BATCHBUFFERSTARTADDRESS_BIT_SHIFT; + } + inline void setBatchBufferStartAddressGraphicsaddress472(const uint64_t value) { + TheStructure.Common.BatchBufferStartAddress = value >> BATCHBUFFERSTARTADDRESS_BIT_SHIFT; + } + inline uint64_t getBatchBufferStartAddressGraphicsaddress472() const { + return TheStructure.Common.BatchBufferStartAddress << BATCHBUFFERSTARTADDRESS_BIT_SHIFT; + } + inline void setSecondLevelBatchBuffer(const SECOND_LEVEL_BATCH_BUFFER value) { + TheStructure.Mi_Mode_Nestedbatchbufferenableis0.SecondLevelBatchBuffer = value; + } + inline SECOND_LEVEL_BATCH_BUFFER getSecondLevelBatchBuffer() const { + return static_cast(TheStructure.Mi_Mode_Nestedbatchbufferenableis0.SecondLevelBatchBuffer); + } + inline void setNestedLevelBatchBuffer(const NESTED_LEVEL_BATCH_BUFFER value) { + TheStructure.Mi_Mode_Nestedbatchbufferenableis1.NestedLevelBatchBuffer = value; + } + inline NESTED_LEVEL_BATCH_BUFFER getNestedLevelBatchBuffer() const { + return static_cast(TheStructure.Mi_Mode_Nestedbatchbufferenableis1.NestedLevelBatchBuffer); + } +} MI_BATCH_BUFFER_START; +STATIC_ASSERT(12 == sizeof(MI_BATCH_BUFFER_START)); + +typedef struct tagMI_LOAD_REGISTER_MEM { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 15); + uint32_t WorkloadPartitionIdOffsetEnable : BITFIELD_RANGE(16, 16); + uint32_t MmioRemapEnable : BITFIELD_RANGE(17, 17); + uint32_t Reserved_18 : BITFIELD_RANGE(18, 18); + uint32_t AddCsMmioStartOffset : BITFIELD_RANGE(19, 19); + uint32_t Reserved_20 : BITFIELD_RANGE(20, 20); + uint32_t AsyncModeEnable : BITFIELD_RANGE(21, 21); + uint32_t UseGlobalGtt : BITFIELD_RANGE(22, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint32_t Reserved_32 : BITFIELD_RANGE(0, 1); + uint32_t RegisterAddress : BITFIELD_RANGE(2, 22); + uint32_t Reserved_55 : BITFIELD_RANGE(23, 31); + // DWORD 2 + uint64_t Reserved_64 : BITFIELD_RANGE(0, 1); + uint64_t MemoryAddress : BITFIELD_RANGE(2, 63); + } Common; + uint32_t RawData[4]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x2, + } DWORD_LENGTH; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_LOAD_REGISTER_MEM = 0x29, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.MiCommandOpcode = + MI_COMMAND_OPCODE_MI_LOAD_REGISTER_MEM; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_LOAD_REGISTER_MEM sInit() { + MI_LOAD_REGISTER_MEM state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 4); + return TheStructure.RawData[index]; + } + inline void setWorkloadPartitionIdOffsetEnable(const bool value) { + TheStructure.Common.WorkloadPartitionIdOffsetEnable = value; + } + inline bool getWorkloadPartitionIdOffsetEnable() const { + return TheStructure.Common.WorkloadPartitionIdOffsetEnable; + } + inline void setMmioRemapEnable(const bool value) { + TheStructure.Common.MmioRemapEnable = value; + } + inline bool getMmioRemapEnable() const { + return TheStructure.Common.MmioRemapEnable; + } + inline void setAddCsMmioStartOffset(const uint32_t value) { + TheStructure.Common.AddCsMmioStartOffset = value; + } + inline uint32_t getAddCsMmioStartOffset() const { + return TheStructure.Common.AddCsMmioStartOffset; + } + inline void setAsyncModeEnable(const bool value) { + TheStructure.Common.AsyncModeEnable = value; + } + inline bool getAsyncModeEnable() const { + return TheStructure.Common.AsyncModeEnable; + } + inline void setUseGlobalGtt(const bool value) { + TheStructure.Common.UseGlobalGtt = value; + } + inline bool getUseGlobalGtt() const { + return TheStructure.Common.UseGlobalGtt; + } + typedef enum tagREGISTERADDRESS { + REGISTERADDRESS_BIT_SHIFT = 0x2, + REGISTERADDRESS_ALIGN_SIZE = 0x4, + } REGISTERADDRESS; + inline void setRegisterAddress(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x7ffffc); + TheStructure.Common.RegisterAddress = value >> REGISTERADDRESS_BIT_SHIFT; + } + inline uint32_t getRegisterAddress() const { + return TheStructure.Common.RegisterAddress << REGISTERADDRESS_BIT_SHIFT; + } + typedef enum tagMEMORYADDRESS { + MEMORYADDRESS_BIT_SHIFT = 0x2, + MEMORYADDRESS_ALIGN_SIZE = 0x4, + } MEMORYADDRESS; + inline void setMemoryAddress(const uint64_t value) { + DEBUG_BREAK_IF(value > 0xfffffffffffffffcL); + TheStructure.Common.MemoryAddress = value >> MEMORYADDRESS_BIT_SHIFT; + } + inline uint64_t getMemoryAddress() const { + return TheStructure.Common.MemoryAddress << MEMORYADDRESS_BIT_SHIFT; + } +} MI_LOAD_REGISTER_MEM; +STATIC_ASSERT(16 == sizeof(MI_LOAD_REGISTER_MEM)); + +typedef struct tagMI_LOAD_REGISTER_REG { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 15); + uint32_t MmioRemapEnableSource : BITFIELD_RANGE(16, 16); + uint32_t MmioRemapEnableDestination : BITFIELD_RANGE(17, 17); + uint32_t AddCsMmioStartOffsetSource : BITFIELD_RANGE(18, 18); + uint32_t AddCsMmioStartOffsetDestination : BITFIELD_RANGE(19, 19); + uint32_t Reserved_20 : BITFIELD_RANGE(20, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint32_t Reserved_32 : BITFIELD_RANGE(0, 1); + uint32_t SourceRegisterAddress : BITFIELD_RANGE(2, 22); + uint32_t Reserved_55 : BITFIELD_RANGE(23, 31); + // DWORD 2 + uint32_t Reserved_64 : BITFIELD_RANGE(0, 1); + uint32_t DestinationRegisterAddress : BITFIELD_RANGE(2, 22); + uint32_t Reserved_87 : BITFIELD_RANGE(23, 31); + } Common; + uint32_t RawData[3]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x1, + } DWORD_LENGTH; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_LOAD_REGISTER_REG = 0x2a, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_LOAD_REGISTER_REG; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_LOAD_REGISTER_REG sInit() { + MI_LOAD_REGISTER_REG state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + DEBUG_BREAK_IF(index >= 3); + return TheStructure.RawData[index]; + } + inline void setMmioRemapEnableSource(const bool value) { + TheStructure.Common.MmioRemapEnableSource = value; + } + inline bool getMmioRemapEnableSource() const { + return TheStructure.Common.MmioRemapEnableSource; + } + inline void setMmioRemapEnableDestination(const bool value) { + TheStructure.Common.MmioRemapEnableDestination = value; + } + inline bool getMmioRemapEnableDestination() const { + return TheStructure.Common.MmioRemapEnableDestination; + } + inline void setAddCsMmioStartOffsetSource(const uint32_t value) { + TheStructure.Common.AddCsMmioStartOffsetSource = value; + } + inline uint32_t getAddCsMmioStartOffsetSource() const { + return TheStructure.Common.AddCsMmioStartOffsetSource; + } + inline void setAddCsMmioStartOffsetDestination(const uint32_t value) { + TheStructure.Common.AddCsMmioStartOffsetDestination = value; + } + inline uint32_t getAddCsMmioStartOffsetDestination() const { + return TheStructure.Common.AddCsMmioStartOffsetDestination; + } + typedef enum tagSOURCEREGISTERADDRESS { + SOURCEREGISTERADDRESS_BIT_SHIFT = 0x2, + SOURCEREGISTERADDRESS_ALIGN_SIZE = 0x4, + } SOURCEREGISTERADDRESS; + inline void setSourceRegisterAddress(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x7ffffc); + TheStructure.Common.SourceRegisterAddress = value >> SOURCEREGISTERADDRESS_BIT_SHIFT; + } + inline uint32_t getSourceRegisterAddress() const { + return TheStructure.Common.SourceRegisterAddress << SOURCEREGISTERADDRESS_BIT_SHIFT; + } + typedef enum tagDESTINATIONREGISTERADDRESS { + DESTINATIONREGISTERADDRESS_BIT_SHIFT = 0x2, + DESTINATIONREGISTERADDRESS_ALIGN_SIZE = 0x4, + } DESTINATIONREGISTERADDRESS; + inline void setDestinationRegisterAddress(const uint32_t value) { + DEBUG_BREAK_IF(value > 0x7ffffc); + TheStructure.Common.DestinationRegisterAddress = value >> DESTINATIONREGISTERADDRESS_BIT_SHIFT; + } + inline uint32_t getDestinationRegisterAddress() const { + return TheStructure.Common.DestinationRegisterAddress << DESTINATIONREGISTERADDRESS_BIT_SHIFT; + } +} MI_LOAD_REGISTER_REG; +STATIC_ASSERT(12 == sizeof(MI_LOAD_REGISTER_REG)); + +typedef struct tagMI_SEMAPHORE_WAIT { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t SemaphoreWaitContextSwitchMode : BITFIELD_RANGE(8, 9); + uint32_t Reserved_10 : BITFIELD_RANGE(10, 11); + uint32_t CompareOperation : BITFIELD_RANGE(12, 14); + uint32_t WaitMode : BITFIELD_RANGE(15, 15); + uint32_t RegisterPollMode : BITFIELD_RANGE(16, 16); + uint32_t Reserved_17 : BITFIELD_RANGE(17, 17); + uint32_t WorkloadPartitionIdOffsetEnable : BITFIELD_RANGE(18, 18); + uint32_t Reserved_19 : BITFIELD_RANGE(19, 21); + uint32_t MemoryType : BITFIELD_RANGE(22, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint32_t SemaphoreDataDword; + // DWORD 2 + uint64_t Reserved_64 : BITFIELD_RANGE(0, 1); + uint64_t SemaphoreAddress : BITFIELD_RANGE(2, 56); + uint64_t SemaphoreAddressReserved_121 : BITFIELD_RANGE(57, 63); + // DWORD 4 + uint32_t Reserved_128 : BITFIELD_RANGE(0, 1); + uint32_t WaitTokenNumber : BITFIELD_RANGE(2, 9); + uint32_t Reserved_138 : BITFIELD_RANGE(10, 21); + uint32_t ContextSwitchWaitTime : BITFIELD_RANGE(22, 31); + } Common; + uint32_t RawData[5]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x3, + } DWORD_LENGTH; + typedef enum tagSEMAPHORE_WAIT_CONTEXT_SWITCH_MODE { + SEMAPHORE_WAIT_CONTEXT_SWITCH_MODE_LEGACY_MODE = 0x0, + SEMAPHORE_WAIT_CONTEXT_SWITCH_MODE_CONTEXT_SWITCH_ON_UN_SUCCESSFUL_SEMAPHORE_WAIT = 0x1, + SEMAPHORE_WAIT_CONTEXT_SWITCH_MODE_INHIBIT_CONTEXT_SWITCH_ON_UN_SUCCESSFUL_SEMAPHORE_WAIT = 0x2, + SEMAPHORE_WAIT_CONTEXT_SWITCH_MODE_DELAY_CONTEXT_SWITCH_ON_UN_SUCCESSFUL_SEMAPHORE_WAIT = 0x3, + } SEMAPHORE_WAIT_CONTEXT_SWITCH_MODE; + typedef enum tagCOMPARE_OPERATION { + COMPARE_OPERATION_SAD_GREATER_THAN_SDD = 0x0, + COMPARE_OPERATION_SAD_GREATER_THAN_OR_EQUAL_SDD = 0x1, + COMPARE_OPERATION_SAD_LESS_THAN_SDD = 0x2, + COMPARE_OPERATION_SAD_LESS_THAN_OR_EQUAL_SDD = 0x3, + COMPARE_OPERATION_SAD_EQUAL_SDD = 0x4, + COMPARE_OPERATION_SAD_NOT_EQUAL_SDD = 0x5, + } COMPARE_OPERATION; + typedef enum tagWAIT_MODE { + WAIT_MODE_SIGNAL_MODE = 0x0, + WAIT_MODE_POLLING_MODE = 0x1, + } WAIT_MODE; + typedef enum tagREGISTER_POLL_MODE { + REGISTER_POLL_MODE_MEMORY_POLL = 0x0, + REGISTER_POLL_MODE_REGISTER_POLL = 0x1, + } REGISTER_POLL_MODE; + typedef enum tagMEMORY_TYPE { + MEMORY_TYPE_PER_PROCESS_GRAPHICS_ADDRESS = 0x0, + MEMORY_TYPE_GLOBAL_GRAPHICS_ADDRESS = 0x1, + } MEMORY_TYPE; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_SEMAPHORE_WAIT = 0x1c, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.CompareOperation = + COMPARE_OPERATION_SAD_GREATER_THAN_SDD; + TheStructure.Common.WaitMode = WAIT_MODE_SIGNAL_MODE; + TheStructure.Common.RegisterPollMode = REGISTER_POLL_MODE_MEMORY_POLL; + TheStructure.Common.MemoryType = MEMORY_TYPE_PER_PROCESS_GRAPHICS_ADDRESS; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_SEMAPHORE_WAIT; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_SEMAPHORE_WAIT sInit() { + MI_SEMAPHORE_WAIT state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 5); + return TheStructure.RawData[index]; + } + inline void setSemaphoreWaitContextSwitchMode(const SEMAPHORE_WAIT_CONTEXT_SWITCH_MODE value) { + TheStructure.Common.SemaphoreWaitContextSwitchMode = value; + } + inline SEMAPHORE_WAIT_CONTEXT_SWITCH_MODE getSemaphoreWaitContextSwitchMode() const { + return static_cast(TheStructure.Common.SemaphoreWaitContextSwitchMode); + } + inline void setCompareOperation(const COMPARE_OPERATION value) { + TheStructure.Common.CompareOperation = value; + } + inline COMPARE_OPERATION getCompareOperation() const { + return static_cast(TheStructure.Common.CompareOperation); + } + inline void setWaitMode(const WAIT_MODE value) { + TheStructure.Common.WaitMode = value; + } + inline WAIT_MODE getWaitMode() const { + return static_cast(TheStructure.Common.WaitMode); + } + inline void setRegisterPollMode(const REGISTER_POLL_MODE value) { + TheStructure.Common.RegisterPollMode = value; + } + inline REGISTER_POLL_MODE getRegisterPollMode() const { + return static_cast( + TheStructure.Common.RegisterPollMode); + } + inline void setWorkloadPartitionIdOffsetEnable(const bool value) { + TheStructure.Common.WorkloadPartitionIdOffsetEnable = value; + } + inline bool getWorkloadPartitionIdOffsetEnable() const { + return TheStructure.Common.WorkloadPartitionIdOffsetEnable; + } + inline void setMemoryType(const MEMORY_TYPE value) { + TheStructure.Common.MemoryType = value; + } + inline MEMORY_TYPE getMemoryType() const { + return static_cast(TheStructure.Common.MemoryType); + } + inline void setSemaphoreDataDword(const uint32_t value) { + TheStructure.Common.SemaphoreDataDword = value; + } + inline uint32_t getSemaphoreDataDword() const { + return TheStructure.Common.SemaphoreDataDword; + } + typedef enum tagSEMAPHOREADDRESS { + SEMAPHOREADDRESS_BIT_SHIFT = 0x2, + SEMAPHOREADDRESS_ALIGN_SIZE = 0x4, + } SEMAPHOREADDRESS; + inline void setSemaphoreGraphicsAddress(const uint64_t value) { + TheStructure.Common.SemaphoreAddress = value >> SEMAPHOREADDRESS_BIT_SHIFT; + } + inline uint64_t getSemaphoreGraphicsAddress() const { + return TheStructure.Common.SemaphoreAddress << SEMAPHOREADDRESS_BIT_SHIFT; + } + inline void setWaitTokenNumber(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3fc); + TheStructure.Common.WaitTokenNumber = value; + } + inline uint32_t getWaitTokenNumber() const { + return TheStructure.Common.WaitTokenNumber; + } + inline void setContextSwitchWaitTime(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xffc00000); + TheStructure.Common.ContextSwitchWaitTime = value; + } + inline uint32_t getContextSwitchWaitTime() const { + return TheStructure.Common.ContextSwitchWaitTime; + } +} MI_SEMAPHORE_WAIT; +STATIC_ASSERT(20 == sizeof(MI_SEMAPHORE_WAIT)); + +typedef struct tagMI_STORE_DATA_IMM { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 9); + uint32_t Reserved_10 : BITFIELD_RANGE(10, 10); + uint32_t WorkloadPartitionIdOffsetEnable : BITFIELD_RANGE(11, 11); + uint32_t Reserved_12 : BITFIELD_RANGE(12, 12); + uint32_t Reserved_13 : BITFIELD_RANGE(13, 20); + uint32_t StoreQword : BITFIELD_RANGE(21, 21); + uint32_t UseGlobalGtt : BITFIELD_RANGE(22, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint64_t CoreModeEnable : BITFIELD_RANGE(0, 0); + uint64_t Reserved_33 : BITFIELD_RANGE(1, 1); + uint64_t Address : BITFIELD_RANGE(2, 56); + uint64_t AddressReserved_89 : BITFIELD_RANGE(57, 63); + // DWORD 3 + uint32_t DataDword0; + // DWORD 4 + uint32_t DataDword1; + } Common; + uint32_t RawData[5]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_STORE_DWORD = 0x2, + DWORD_LENGTH_STORE_QWORD = 0x3, + } DWORD_LENGTH; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_STORE_DATA_IMM = 0x20, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_STORE_DWORD; + TheStructure.Common.MiCommandOpcode = MI_COMMAND_OPCODE_MI_STORE_DATA_IMM; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_STORE_DATA_IMM sInit() { + MI_STORE_DATA_IMM state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 5); + return TheStructure.RawData[index]; + } + inline void setDwordLength(const DWORD_LENGTH value) { + TheStructure.Common.DwordLength = value; + } + inline DWORD_LENGTH getDwordLength() const { + return static_cast(TheStructure.Common.DwordLength); + } + inline void setWorkloadPartitionIdOffsetEnable(const bool value) { + TheStructure.Common.WorkloadPartitionIdOffsetEnable = value; + } + inline bool getWorkloadPartitionIdOffsetEnable() const { + return TheStructure.Common.WorkloadPartitionIdOffsetEnable; + } + inline void setStoreQword(const bool value) { + TheStructure.Common.StoreQword = value; + } + inline bool getStoreQword() const { + return TheStructure.Common.StoreQword; + } + inline void setUseGlobalGtt(const bool value) { + TheStructure.Common.UseGlobalGtt = value; + } + inline bool getUseGlobalGtt() const { + return TheStructure.Common.UseGlobalGtt; + } + inline void setCoreModeEnable(const uint64_t value) { + TheStructure.Common.CoreModeEnable = value; + } + inline uint64_t getCoreModeEnable() const { + return TheStructure.Common.CoreModeEnable; + } + typedef enum tagADDRESS { + ADDRESS_BIT_SHIFT = 0x2, + ADDRESS_ALIGN_SIZE = 0x4, + } ADDRESS; + inline void setAddress(const uint64_t value) { + UNRECOVERABLE_IF(value > 0x1fffffffffffffcL); + TheStructure.Common.Address = value >> ADDRESS_BIT_SHIFT; + } + inline uint64_t getAddress() const { + return TheStructure.Common.Address << ADDRESS_BIT_SHIFT; + } + inline void setDataDword0(const uint32_t value) { + TheStructure.Common.DataDword0 = value; + } + inline uint32_t getDataDword0() const { + return TheStructure.Common.DataDword0; + } + inline void setDataDword1(const uint32_t value) { + TheStructure.Common.DataDword1 = value; + } + inline uint32_t getDataDword1() const { + return TheStructure.Common.DataDword1; + } +} MI_STORE_DATA_IMM; +STATIC_ASSERT(20 == sizeof(MI_STORE_DATA_IMM)); + +typedef struct tagMI_STORE_REGISTER_MEM { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 15); + uint32_t WorkloadPartitionIdOffsetEnable : BITFIELD_RANGE(16, 16); + uint32_t MmioRemapEnable : BITFIELD_RANGE(17, 17); + uint32_t Reserved_18 : BITFIELD_RANGE(18, 18); + uint32_t AddCsMmioStartOffset : BITFIELD_RANGE(19, 19); + uint32_t Reserved_20 : BITFIELD_RANGE(20, 20); + uint32_t PredicateEnable : BITFIELD_RANGE(21, 21); + uint32_t UseGlobalGtt : BITFIELD_RANGE(22, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint32_t Reserved_32 : BITFIELD_RANGE(0, 1); + uint32_t RegisterAddress : BITFIELD_RANGE(2, 22); + uint32_t Reserved_55 : BITFIELD_RANGE(23, 31); + // DWORD 2 + uint64_t Reserved_64 : BITFIELD_RANGE(0, 1); + uint64_t MemoryAddress : BITFIELD_RANGE(2, 63); + } Common; + uint32_t RawData[4]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x2, + } DWORD_LENGTH; + typedef enum tagMI_COMMAND_OPCODE { + MI_COMMAND_OPCODE_MI_STORE_REGISTER_MEM = 0x24, + } MI_COMMAND_OPCODE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_MI_COMMAND = 0x0, + } COMMAND_TYPE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.MiCommandOpcode = + MI_COMMAND_OPCODE_MI_STORE_REGISTER_MEM; + TheStructure.Common.CommandType = COMMAND_TYPE_MI_COMMAND; + } + static tagMI_STORE_REGISTER_MEM sInit() { + MI_STORE_REGISTER_MEM state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 4); + return TheStructure.RawData[index]; + } + inline void setWorkloadPartitionIdOffsetEnable(const bool value) { + TheStructure.Common.WorkloadPartitionIdOffsetEnable = value; + } + inline bool getWorkloadPartitionIdOffsetEnable() const { + return TheStructure.Common.WorkloadPartitionIdOffsetEnable; + } + inline void setMmioRemapEnable(const bool value) { + TheStructure.Common.MmioRemapEnable = value; + } + inline bool getMmioRemapEnable() const { + return TheStructure.Common.MmioRemapEnable; + } + inline void setAddCsMmioStartOffset(const uint32_t value) { + TheStructure.Common.AddCsMmioStartOffset = value; + } + inline uint32_t getAddCsMmioStartOffset() const { + return TheStructure.Common.AddCsMmioStartOffset; + } + inline void setPredicateEnable(const bool value) { + TheStructure.Common.PredicateEnable = value; + } + inline bool getPredicateEnable() const { + return TheStructure.Common.PredicateEnable; + } + inline void setUseGlobalGtt(const bool value) { + TheStructure.Common.UseGlobalGtt = value; + } + inline bool getUseGlobalGtt() const { + return TheStructure.Common.UseGlobalGtt; + } + typedef enum tagREGISTERADDRESS { + REGISTERADDRESS_BIT_SHIFT = 0x2, + REGISTERADDRESS_ALIGN_SIZE = 0x4, + } REGISTERADDRESS; + inline void setRegisterAddress(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x7ffffc); + TheStructure.Common.RegisterAddress = value >> REGISTERADDRESS_BIT_SHIFT; + } + inline uint32_t getRegisterAddress() const { + return TheStructure.Common.RegisterAddress << REGISTERADDRESS_BIT_SHIFT; + } + typedef enum tagMEMORYADDRESS { + MEMORYADDRESS_BIT_SHIFT = 0x2, + MEMORYADDRESS_ALIGN_SIZE = 0x4, + } MEMORYADDRESS; + inline void setMemoryAddress(const uint64_t value) { + UNRECOVERABLE_IF(value > 0xfffffffffffffffcL); + TheStructure.Common.MemoryAddress = value >> MEMORYADDRESS_BIT_SHIFT; + } + inline uint64_t getMemoryAddress() const { + return TheStructure.Common.MemoryAddress << MEMORYADDRESS_BIT_SHIFT; + } +} MI_STORE_REGISTER_MEM; +STATIC_ASSERT(16 == sizeof(MI_STORE_REGISTER_MEM)); + +typedef struct tagPIPELINE_SELECT { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t PipelineSelection : BITFIELD_RANGE(0, 1); + uint32_t RenderSliceCommonPowerGateEnable : BITFIELD_RANGE(2, 2); + uint32_t RenderSamplerPowerGateEnable : BITFIELD_RANGE(3, 3); + uint32_t MediaSamplerDopClockGateEnable : BITFIELD_RANGE(4, 4); + uint32_t Reserved_5 : BITFIELD_RANGE(5, 5); + uint32_t MediaSamplerPowerClockGateDisable : BITFIELD_RANGE(6, 6); + uint32_t SystolicModeEnable : BITFIELD_RANGE(7, 7); + uint32_t MaskBits : BITFIELD_RANGE(8, 15); + uint32_t _3DCommandSubOpcode : BITFIELD_RANGE(16, 23); + uint32_t _3DCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t CommandSubtype : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + } Common; + uint32_t RawData[1]; + } TheStructure; + typedef enum tagPIPELINE_SELECTION { + PIPELINE_SELECTION_3D = 0x0, + PIPELINE_SELECTION_GPGPU = 0x2, + } PIPELINE_SELECTION; + typedef enum tag_3D_COMMAND_SUB_OPCODE { + _3D_COMMAND_SUB_OPCODE_PIPELINE_SELECT = 0x4, + } _3D_COMMAND_SUB_OPCODE; + typedef enum tag_3D_COMMAND_OPCODE { + _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED = 0x1, + } _3D_COMMAND_OPCODE; + typedef enum tagCOMMAND_SUBTYPE { + COMMAND_SUBTYPE_GFXPIPE_SINGLE_DW = 0x1, + } COMMAND_SUBTYPE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.PipelineSelection = PIPELINE_SELECTION_3D; + TheStructure.Common._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_PIPELINE_SELECT; + TheStructure.Common._3DCommandOpcode = _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED; + TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_SINGLE_DW; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + } + static tagPIPELINE_SELECT sInit() { + PIPELINE_SELECT state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 1); + return TheStructure.RawData[index]; + } + inline void setPipelineSelection(const PIPELINE_SELECTION value) { + TheStructure.Common.PipelineSelection = value; + } + inline PIPELINE_SELECTION getPipelineSelection() const { + return static_cast(TheStructure.Common.PipelineSelection); + } + inline void setRenderSliceCommonPowerGateEnable(const bool value) { + TheStructure.Common.RenderSliceCommonPowerGateEnable = value; + } + inline bool getRenderSliceCommonPowerGateEnable() const { + return TheStructure.Common.RenderSliceCommonPowerGateEnable; + } + inline void setRenderSamplerPowerGateEnable(const bool value) { + TheStructure.Common.RenderSamplerPowerGateEnable = value; + } + inline bool getRenderSamplerPowerGateEnable() const { + return TheStructure.Common.RenderSamplerPowerGateEnable; + } + inline void setMediaSamplerDopClockGateEnable(const bool value) { + TheStructure.Common.MediaSamplerDopClockGateEnable = value; + } + inline bool getMediaSamplerDopClockGateEnable() const { + return TheStructure.Common.MediaSamplerDopClockGateEnable; + } + inline void setMediaSamplerPowerClockGateDisable(const bool value) { + TheStructure.Common.MediaSamplerPowerClockGateDisable = value; + } + inline bool getMediaSamplerPowerClockGateDisable() const { + return TheStructure.Common.MediaSamplerPowerClockGateDisable; + } + inline void setSystolicModeEnable(const bool value) { + TheStructure.Common.SystolicModeEnable = value; + } + inline bool getSystolicModeEnable() const { + return TheStructure.Common.SystolicModeEnable; + } + inline void setMaskBits(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xff00); + TheStructure.Common.MaskBits = value; + } + inline uint32_t getMaskBits() const { + return TheStructure.Common.MaskBits; + } +} PIPELINE_SELECT; +STATIC_ASSERT(4 == sizeof(PIPELINE_SELECT)); + +typedef struct tagSTATE_COMPUTE_MODE { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 15); + uint32_t _3DCommandSubOpcode : BITFIELD_RANGE(16, 23); + uint32_t _3DCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t CommandSubtype : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint32_t Reserved_32 : BITFIELD_RANGE(0, 2); + uint32_t ForceNonCoherent : BITFIELD_RANGE(3, 4); + uint32_t FastClearDisabledOnCompressedSurface : BITFIELD_RANGE(5, 5); + uint32_t DisableSlmReadMergeOptimization : BITFIELD_RANGE(6, 6); + uint32_t Reserved_39 : BITFIELD_RANGE(7, 10); + uint32_t DisableAtomicOnClearData : BITFIELD_RANGE(11, 11); + uint32_t Reserved_44 : BITFIELD_RANGE(12, 12); + uint32_t EuThreadSchedulingModeOverride : BITFIELD_RANGE(13, 14); + uint32_t LargeGrfMode : BITFIELD_RANGE(15, 15); + uint32_t Mask : BITFIELD_RANGE(16, 31); + } Common; + uint32_t RawData[2]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x0, + } DWORD_LENGTH; + typedef enum tag_3D_COMMAND_SUB_OPCODE { + _3D_COMMAND_SUB_OPCODE_STATE_COMPUTE_MODE = 0x5, + } _3D_COMMAND_SUB_OPCODE; + typedef enum tag_3D_COMMAND_OPCODE { + _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED = 0x1, + } _3D_COMMAND_OPCODE; + typedef enum tagCOMMAND_SUBTYPE { + COMMAND_SUBTYPE_GFXPIPE_COMMON = 0x0, + } COMMAND_SUBTYPE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + typedef enum tagFORCE_NON_COHERENT { + FORCE_NON_COHERENT_FORCE_DISABLED = 0x0, + FORCE_NON_COHERENT_FORCE_CPU_NON_COHERENT = 0x1, + FORCE_NON_COHERENT_FORCE_GPU_NON_COHERENT = 0x2, + } FORCE_NON_COHERENT; + typedef enum tagFAST_CLEAR_DISABLED_ON_COMPRESSED_SURFACE { + FAST_CLEAR_DISABLED_ON_COMPRESSED_SURFACE_ENABLED = 0x0, + FAST_CLEAR_DISABLED_ON_COMPRESSED_SURFACE_DISABLED = 0x1, + } FAST_CLEAR_DISABLED_ON_COMPRESSED_SURFACE; + typedef enum tagDISABLE_SLM_READ_MERGE_OPTIMIZATION { + DISABLE_SLM_READ_MERGE_OPTIMIZATION_ENABLED = 0x0, + DISABLE_SLM_READ_MERGE_OPTIMIZATION_DISABLED = 0x1, + } DISABLE_SLM_READ_MERGE_OPTIMIZATION; + typedef enum tagDISABLE_ATOMIC_ON_CLEAR_DATA { + DISABLE_ATOMIC_ON_CLEAR_DATA_ENABLE = 0x0, + DISABLE_ATOMIC_ON_CLEAR_DATA_DISABLE = 0x1, + } DISABLE_ATOMIC_ON_CLEAR_DATA; + typedef enum tagEU_THREAD_SCHEDULING_MODE_OVERRIDE { + EU_THREAD_SCHEDULING_MODE_OVERRIDE_HW_DEFAULT = 0x0, + EU_THREAD_SCHEDULING_MODE_OVERRIDE_OLDEST_FIRST = 0x1, + EU_THREAD_SCHEDULING_MODE_OVERRIDE_ROUND_ROBIN = 0x2, + EU_THREAD_SCHEDULING_MODE_OVERRIDE_STALL_BASED_ROUND_ROBIN = 0x3, + } EU_THREAD_SCHEDULING_MODE_OVERRIDE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_STATE_COMPUTE_MODE; + TheStructure.Common._3DCommandOpcode = _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED; + TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_COMMON; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + TheStructure.Common.ForceNonCoherent = FORCE_NON_COHERENT_FORCE_DISABLED; + TheStructure.Common.FastClearDisabledOnCompressedSurface = FAST_CLEAR_DISABLED_ON_COMPRESSED_SURFACE_ENABLED; + TheStructure.Common.DisableSlmReadMergeOptimization = DISABLE_SLM_READ_MERGE_OPTIMIZATION_ENABLED; + TheStructure.Common.DisableAtomicOnClearData = DISABLE_ATOMIC_ON_CLEAR_DATA_ENABLE; + TheStructure.Common.EuThreadSchedulingModeOverride = EU_THREAD_SCHEDULING_MODE_OVERRIDE_HW_DEFAULT; + } + static tagSTATE_COMPUTE_MODE sInit() { + STATE_COMPUTE_MODE state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 2); + return TheStructure.RawData[index]; + } + inline void setForceNonCoherent(const FORCE_NON_COHERENT value) { + TheStructure.Common.ForceNonCoherent = value; + } + inline FORCE_NON_COHERENT getForceNonCoherent() const { + return static_cast(TheStructure.Common.ForceNonCoherent); + } + inline void setFastClearDisabledOnCompressedSurface(const FAST_CLEAR_DISABLED_ON_COMPRESSED_SURFACE value) { + TheStructure.Common.FastClearDisabledOnCompressedSurface = value; + } + inline FAST_CLEAR_DISABLED_ON_COMPRESSED_SURFACE getFastClearDisabledOnCompressedSurface() const { + return static_cast(TheStructure.Common.FastClearDisabledOnCompressedSurface); + } + inline void setDisableSlmReadMergeOptimization(const DISABLE_SLM_READ_MERGE_OPTIMIZATION value) { + TheStructure.Common.DisableSlmReadMergeOptimization = value; + } + inline DISABLE_SLM_READ_MERGE_OPTIMIZATION getDisableSlmReadMergeOptimization() const { + return static_cast(TheStructure.Common.DisableSlmReadMergeOptimization); + } + inline void setDisableAtomicOnClearData(const DISABLE_ATOMIC_ON_CLEAR_DATA value) { + TheStructure.Common.DisableAtomicOnClearData = value; + } + inline DISABLE_ATOMIC_ON_CLEAR_DATA getDisableAtomicOnClearData() const { + return static_cast(TheStructure.Common.DisableAtomicOnClearData); + } + inline void setEuThreadSchedulingModeOverride(const EU_THREAD_SCHEDULING_MODE_OVERRIDE value) { + TheStructure.Common.EuThreadSchedulingModeOverride = value; + } + inline EU_THREAD_SCHEDULING_MODE_OVERRIDE getEuThreadSchedulingModeOverride() const { + return static_cast(TheStructure.Common.EuThreadSchedulingModeOverride); + } + inline void setLargeGrfMode(const bool value) { + TheStructure.Common.LargeGrfMode = value; + } + inline bool getLargeGrfMode() const { + return TheStructure.Common.LargeGrfMode; + } + inline void setMaskBits(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xffff); + TheStructure.Common.Mask = value; + } + inline uint32_t getMaskBits() const { + return TheStructure.Common.Mask; + } +} STATE_COMPUTE_MODE; +STATIC_ASSERT(8 == sizeof(STATE_COMPUTE_MODE)); + +typedef struct tag_3DSTATE_BINDING_TABLE_POOL_ALLOC { + union tagTheStructure { + struct tagCommon { + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 15); + uint32_t _3DCommandSubOpcode : BITFIELD_RANGE(16, 23); + uint32_t _3DCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t CommandSubtype : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + uint64_t SurfaceObjectControlStateEncryptedData : BITFIELD_RANGE(0, 0); + uint64_t SurfaceObjectControlStateIndexToMocsTables : BITFIELD_RANGE(1, 6); + uint64_t Reserved_39 : BITFIELD_RANGE(7, 9); + uint64_t Reserved_42 : BITFIELD_RANGE(10, 10); + uint64_t Reserved_43 : BITFIELD_RANGE(11, 11); + uint64_t BindingTablePoolBaseAddress : BITFIELD_RANGE(12, 47); + uint64_t BindingTablePoolBaseAddressReserved_80 : BITFIELD_RANGE(48, 63); + uint32_t Reserved_96 : BITFIELD_RANGE(0, 11); + uint32_t BindingTablePoolBufferSize : BITFIELD_RANGE(12, 31); + } Common; + uint32_t RawData[4]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_DWORD_COUNT_N = 0x2, + } DWORD_LENGTH; + typedef enum tag_3D_COMMAND_SUB_OPCODE { + _3D_COMMAND_SUB_OPCODE_3DSTATE_BINDING_TABLE_POOL_ALLOC = 0x19, + } _3D_COMMAND_SUB_OPCODE; + typedef enum tag_3D_COMMAND_OPCODE { + _3D_COMMAND_OPCODE_3DSTATE_NONPIPELINED = 0x1, + } _3D_COMMAND_OPCODE; + typedef enum tagCOMMAND_SUBTYPE { + COMMAND_SUBTYPE_GFXPIPE_3D = 0x3, + } COMMAND_SUBTYPE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_DWORD_COUNT_N; + TheStructure.Common._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_3DSTATE_BINDING_TABLE_POOL_ALLOC; + TheStructure.Common._3DCommandOpcode = _3D_COMMAND_OPCODE_3DSTATE_NONPIPELINED; + TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_3D; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + TheStructure.Common.BindingTablePoolBufferSize = 0; + } + static tag_3DSTATE_BINDING_TABLE_POOL_ALLOC sInit() { + _3DSTATE_BINDING_TABLE_POOL_ALLOC state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 4); + return TheStructure.RawData[index]; + } + inline void setSurfaceObjectControlStateEncryptedData(const bool value) { + TheStructure.Common.SurfaceObjectControlStateEncryptedData = value; + } + inline bool getSurfaceObjectControlStateEncryptedData() const { + return TheStructure.Common.SurfaceObjectControlStateEncryptedData; + } + inline void setSurfaceObjectControlStateIndexToMocsTables(const uint64_t value) { + UNRECOVERABLE_IF(value > 0x7eL); + TheStructure.Common.SurfaceObjectControlStateIndexToMocsTables = value >> 1; + } + inline uint64_t getSurfaceObjectControlStateIndexToMocsTables() const { + return (TheStructure.Common.SurfaceObjectControlStateIndexToMocsTables << 1); + } + typedef enum tagBINDINGTABLEPOOLBASEADDRESS { + BINDINGTABLEPOOLBASEADDRESS_BIT_SHIFT = 0xc, + BINDINGTABLEPOOLBASEADDRESS_ALIGN_SIZE = 0x1000, + } BINDINGTABLEPOOLBASEADDRESS; + inline void setBindingTablePoolBaseAddress(const uint64_t value) { + TheStructure.Common.BindingTablePoolBaseAddress = value >> BINDINGTABLEPOOLBASEADDRESS_BIT_SHIFT; + } + inline uint64_t getBindingTablePoolBaseAddress() const { + return TheStructure.Common.BindingTablePoolBaseAddress << BINDINGTABLEPOOLBASEADDRESS_BIT_SHIFT; + } + inline void setBindingTablePoolBufferSize(const uint32_t value) { TheStructure.Common.BindingTablePoolBufferSize = value; } + inline uint32_t getBindingTablePoolBufferSize() const { return TheStructure.Common.BindingTablePoolBufferSize; } +} _3DSTATE_BINDING_TABLE_POOL_ALLOC; +STATIC_ASSERT(16 == sizeof(_3DSTATE_BINDING_TABLE_POOL_ALLOC)); + +struct MI_MEM_FENCE { + union tagTheStructure { + struct tagCommon { + uint32_t FenceType : BITFIELD_RANGE(0, 0); + uint32_t Reserved_116 : BITFIELD_RANGE(1, 16); + uint32_t MiCommandSubOpcode : BITFIELD_RANGE(17, 22); + uint32_t MiCommandOpcode : BITFIELD_RANGE(23, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + } Common; + uint32_t RawData[1]; + } TheStructure; + + typedef enum tagFENCE_TYPE { + FENCE_TYPE_RELEASE = 0x0, + FENCE_TYPE_ACQUIRE = 0x1, + } FENCE_TYPE; + + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.MiCommandOpcode = 0x9; + TheStructure.Common.FenceType = FENCE_TYPE::FENCE_TYPE_RELEASE; + } + + static MI_MEM_FENCE sInit() { + MI_MEM_FENCE memFence; + memFence.init(); + return memFence; + } + + inline void setFenceType(const FENCE_TYPE value) { + TheStructure.Common.FenceType = value; + } + inline FENCE_TYPE getAFenceType() const { + return static_cast(TheStructure.Common.FenceType); + } +}; +STATIC_ASSERT(4 == sizeof(MI_MEM_FENCE)); + +struct STATE_SYSTEM_MEM_FENCE_ADDRESS { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved814 : BITFIELD_RANGE(8, 14); + uint32_t ContextRestoreInvalid : BITFIELD_RANGE(15, 15); + uint32_t _3DCommandSubOpcode : BITFIELD_RANGE(16, 23); + uint32_t _3DCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t CommandSubType : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1-2 + uint64_t Reserved011 : BITFIELD_RANGE(0, 11); + uint64_t SystemMemoryFenceAddress : BITFIELD_RANGE(12, 63); + } Common; + uint32_t RawData[3]; + } TheStructure; + + typedef enum tagSYSTEM_MEMORY_FENCE_ADDRESS { + SYSTEM_MEMORY_FENCE_ADDRESS_BIT_SHIFT = 0xc, + } SYSTEM_MEMORY_FENCE_ADDRESS; + + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = 0x1; + TheStructure.Common._3DCommandSubOpcode = 0x9; + TheStructure.Common._3DCommandOpcode = 0x1; + TheStructure.Common.CommandType = 0x3; + } + + static STATE_SYSTEM_MEM_FENCE_ADDRESS sInit() { + STATE_SYSTEM_MEM_FENCE_ADDRESS state; + state.init(); + return state; + } + + inline void setContextRestoreInvalid(const bool value) { + TheStructure.Common.ContextRestoreInvalid = value; + } + inline bool getContextRestoreInvalid() const { + return TheStructure.Common.ContextRestoreInvalid; + } + + inline void setSystemMemoryFenceAddress(const uint64_t value) { + TheStructure.Common.SystemMemoryFenceAddress = (value >> SYSTEM_MEMORY_FENCE_ADDRESS_BIT_SHIFT); + } + inline uint64_t getSystemMemoryFenceAddress() const { + return (TheStructure.Common.SystemMemoryFenceAddress << SYSTEM_MEMORY_FENCE_ADDRESS_BIT_SHIFT); + } +}; +STATIC_ASSERT(12 == sizeof(STATE_SYSTEM_MEM_FENCE_ADDRESS)); + +struct STATE_PREFETCH { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved814 : BITFIELD_RANGE(8, 15); + uint32_t _3dCommandSubOpcode : BITFIELD_RANGE(16, 23); + uint32_t _3dCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t CommandSubType : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint32_t PrefetchSize : BITFIELD_RANGE(0, 9); + uint32_t Reserved1015 : BITFIELD_RANGE(10, 15); + uint32_t KernelInstructionPrefetch : BITFIELD_RANGE(16, 16); + uint32_t Reserved1719 : BITFIELD_RANGE(17, 19); + uint32_t ParserStall : BITFIELD_RANGE(20, 20); + uint32_t Reserved2123 : BITFIELD_RANGE(21, 23); + uint32_t MemoryObjectControlState : BITFIELD_RANGE(24, 30); + uint32_t Reserved31 : BITFIELD_RANGE(31, 31); + // DWORD 2-3 + uint64_t Reserved05 : BITFIELD_RANGE(0, 5); + uint64_t Address : BITFIELD_RANGE(6, 63); + } Common; + uint32_t RawData[4]; + } TheStructure; + + typedef enum tagADDRESS { + ADDRESS_BIT_SHIFT = 0x6, + } ADDRESS; + + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = 0x2; + TheStructure.Common._3dCommandSubOpcode = 0x3; + TheStructure.Common.CommandType = 0x3; + } + + static STATE_PREFETCH sInit() { + STATE_PREFETCH state; + state.init(); + return state; + } + + inline void setPrefetchSize(const uint32_t value) { + TheStructure.Common.PrefetchSize = value; + } + inline uint32_t getPrefetchSize() const { + return TheStructure.Common.PrefetchSize; + } + + inline void setKernelInstructionPrefetch(const bool value) { + TheStructure.Common.KernelInstructionPrefetch = value; + } + inline bool getKernelInstructionPrefetch() const { + return TheStructure.Common.KernelInstructionPrefetch; + } + + inline void setParserStall(const bool value) { + TheStructure.Common.ParserStall = value; + } + inline bool getParserStall() const { + return TheStructure.Common.ParserStall; + } + + inline void setMemoryObjectControlState(const uint32_t value) { + TheStructure.Common.MemoryObjectControlState = value; + } + inline uint32_t getMemoryObjectControlState() const { + return TheStructure.Common.MemoryObjectControlState; + } + + inline void setAddress(const uint64_t value) { + TheStructure.Common.Address = (value >> ADDRESS_BIT_SHIFT); + } + inline uint64_t getAddress() const { + return (TheStructure.Common.Address << ADDRESS_BIT_SHIFT); + } +}; +STATIC_ASSERT(16 == sizeof(STATE_PREFETCH)); + +typedef struct tagMEM_SET { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t CompressionFormat40 : BITFIELD_RANGE(8, 12); + uint32_t DestinationCompressionEnable : BITFIELD_RANGE(13, 13); + uint32_t Reserved_14 : BITFIELD_RANGE(14, 14); + uint32_t DestinationCompressible : BITFIELD_RANGE(15, 15); + uint32_t Reserved_16 : BITFIELD_RANGE(16, 16); + uint32_t FillType : BITFIELD_RANGE(17, 18); + uint32_t Reserved_19 : BITFIELD_RANGE(19, 21); + uint32_t InstructionTarget_Opcode : BITFIELD_RANGE(22, 28); + uint32_t Client : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint32_t FillWidth : BITFIELD_RANGE(0, 17); + uint32_t Reserved_50 : BITFIELD_RANGE(18, 31); + // DWORD 2 + uint32_t FillHeight : BITFIELD_RANGE(0, 17); + uint32_t Reserved_82 : BITFIELD_RANGE(18, 31); + // DWORD 3 + uint32_t DestinationPitch : BITFIELD_RANGE(0, 17); + uint32_t Reserved_114 : BITFIELD_RANGE(18, 31); + // DWORD 4 + uint64_t DestinationStartAddress; + // DWORD 6 + uint32_t DestinationMOCS : BITFIELD_RANGE(0, 6); + uint32_t Reserved_199 : BITFIELD_RANGE(7, 23); + uint32_t FillData : BITFIELD_RANGE(24, 31); + } Common; + uint32_t RawData[7]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_EXCLUDES_DWORD_0_1 = 0x5, + } DWORD_LENGTH; + typedef enum tagDESTINATION_COMPRESSION_ENABLE { + DESTINATION_COMPRESSION_ENABLE_DISABLE = 0x0, + DESTINATION_COMPRESSION_ENABLE_ENABLE = 0x1, + } DESTINATION_COMPRESSION_ENABLE; + typedef enum tagDESTINATION_COMPRESSIBLE { + DESTINATION_COMPRESSIBLE_NOT_COMPRESSIBLE = 0x0, + DESTINATION_COMPRESSIBLE_COMPRESSIBLE = 0x1, + } DESTINATION_COMPRESSIBLE; + typedef enum tagFILL_TYPE { + FILL_TYPE_LINEAR_FILL = 0x0, + FILL_TYPE_MATRIX_FILL = 0x1, + } FILL_TYPE; + typedef enum tagCLIENT { + CLIENT_2D_PROCESSOR = 0x2, + } CLIENT; + typedef enum tagINSTRUCTIONTARGET_OPCODE { + INSTRUCTIONTARGET_OPCODE_OPCODE = 0x5B, + } INSTRUCTIONTARGET_OPCODE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_EXCLUDES_DWORD_0_1; + TheStructure.Common.DestinationCompressionEnable = DESTINATION_COMPRESSION_ENABLE_DISABLE; + TheStructure.Common.DestinationCompressible = DESTINATION_COMPRESSIBLE_NOT_COMPRESSIBLE; + TheStructure.Common.FillType = FILL_TYPE_LINEAR_FILL; + TheStructure.Common.Client = CLIENT_2D_PROCESSOR; + TheStructure.Common.InstructionTarget_Opcode = INSTRUCTIONTARGET_OPCODE::INSTRUCTIONTARGET_OPCODE_OPCODE; + } + static tagMEM_SET sInit() { + MEM_SET state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 7); + return TheStructure.RawData[index]; + } + inline void setCompressionFormat40(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x1f); + TheStructure.Common.CompressionFormat40 = value; + } + inline uint32_t getCompressionFormat40() const { + return TheStructure.Common.CompressionFormat40; + } + inline void setDestinationCompressionEnable(const DESTINATION_COMPRESSION_ENABLE value) { + TheStructure.Common.DestinationCompressionEnable = value; + } + inline DESTINATION_COMPRESSION_ENABLE getDestinationCompressionEnable() const { + return static_cast(TheStructure.Common.DestinationCompressionEnable); + } + inline void setDestinationCompressible(const DESTINATION_COMPRESSIBLE value) { + TheStructure.Common.DestinationCompressible = value; + } + inline DESTINATION_COMPRESSIBLE getDestinationCompressible() const { + return static_cast(TheStructure.Common.DestinationCompressible); + } + inline void setFillType(const FILL_TYPE value) { + TheStructure.Common.FillType = value; + } + inline FILL_TYPE getFillType() const { + return static_cast(TheStructure.Common.FillType); + } + inline void setInstructionTargetOpcode(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x7f); + TheStructure.Common.InstructionTarget_Opcode = value; + } + inline uint32_t getInstructionTargetOpcode() const { + return TheStructure.Common.InstructionTarget_Opcode; + } + inline void setClient(const CLIENT value) { + TheStructure.Common.Client = value; + } + inline CLIENT getClient() const { + return static_cast(TheStructure.Common.Client); + } + inline void setFillWidth(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3ffff); + TheStructure.Common.FillWidth = value - 1; + } + inline uint32_t getFillWidth() const { + return TheStructure.Common.FillWidth + 1; + } + inline void setFillHeight(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3ffff); + TheStructure.Common.FillHeight = value - 1; + } + inline uint32_t getFillHeight() const { + return TheStructure.Common.FillHeight + 1; + } + inline void setDestinationPitch(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x3ffff); + TheStructure.Common.DestinationPitch = value - 1; + } + inline uint32_t getDestinationPitch() const { + return TheStructure.Common.DestinationPitch + 1; + } + inline void setDestinationStartAddress(const uint64_t value) { + TheStructure.Common.DestinationStartAddress = value; + } + inline uint64_t getDestinationStartAddress() const { + return TheStructure.Common.DestinationStartAddress; + } + inline void setDestinationMOCS(const uint32_t value) { + UNRECOVERABLE_IF(value > 0x7f); + TheStructure.Common.DestinationMOCS = value; + } + inline uint32_t getDestinationMOCS() const { + return TheStructure.Common.DestinationMOCS; + } + inline void setFillData(const uint32_t value) { + UNRECOVERABLE_IF(value > 0xff); + TheStructure.Common.FillData = value; + } + inline uint32_t getFillData() const { + return TheStructure.Common.FillData; + } +} MEM_SET; +STATIC_ASSERT(28 == sizeof(MEM_SET)); + +typedef struct tagSTATE_SIP { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + uint32_t DwordLength : BITFIELD_RANGE(0, 7); + uint32_t Reserved_8 : BITFIELD_RANGE(8, 15); + uint32_t _3DCommandSubOpcode : BITFIELD_RANGE(16, 23); + uint32_t _3DCommandOpcode : BITFIELD_RANGE(24, 26); + uint32_t CommandSubtype : BITFIELD_RANGE(27, 28); + uint32_t CommandType : BITFIELD_RANGE(29, 31); + // DWORD 1 + uint64_t Reserved_32 : BITFIELD_RANGE(0, 3); + uint64_t SystemInstructionPointer : BITFIELD_RANGE(4, 63); + } Common; + uint32_t RawData[3]; + } TheStructure; + typedef enum tagDWORD_LENGTH { + DWORD_LENGTH_DWORD_COUNT_N = 0x1, + } DWORD_LENGTH; + typedef enum tag_3D_COMMAND_SUB_OPCODE { + _3D_COMMAND_SUB_OPCODE_STATE_SIP = 0x2, + } _3D_COMMAND_SUB_OPCODE; + typedef enum tag_3D_COMMAND_OPCODE { + _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED = 0x1, + } _3D_COMMAND_OPCODE; + typedef enum tagCOMMAND_SUBTYPE { + COMMAND_SUBTYPE_GFXPIPE_COMMON = 0x0, + } COMMAND_SUBTYPE; + typedef enum tagCOMMAND_TYPE { + COMMAND_TYPE_GFXPIPE = 0x3, + } COMMAND_TYPE; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.DwordLength = DWORD_LENGTH_DWORD_COUNT_N; + TheStructure.Common._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_STATE_SIP; + TheStructure.Common._3DCommandOpcode = _3D_COMMAND_OPCODE_GFXPIPE_NONPIPELINED; + TheStructure.Common.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE_COMMON; + TheStructure.Common.CommandType = COMMAND_TYPE_GFXPIPE; + } + static tagSTATE_SIP sInit() { + STATE_SIP state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 3); + return TheStructure.RawData[index]; + } + typedef enum tagSYSTEMINSTRUCTIONPOINTER { + SYSTEMINSTRUCTIONPOINTER_BIT_SHIFT = 0x4, + SYSTEMINSTRUCTIONPOINTER_ALIGN_SIZE = 0x10, + } SYSTEMINSTRUCTIONPOINTER; + inline void setSystemInstructionPointer(const uint64_t value) { + UNRECOVERABLE_IF(value > 0xffffffffffffffffL); + TheStructure.Common.SystemInstructionPointer = value >> SYSTEMINSTRUCTIONPOINTER_BIT_SHIFT; + } + inline uint64_t getSystemInstructionPointer() const { + return TheStructure.Common.SystemInstructionPointer << SYSTEMINSTRUCTIONPOINTER_BIT_SHIFT; + } +} STATE_SIP; +STATIC_ASSERT(12 == sizeof(STATE_SIP)); + +typedef struct tagSAMPLER_BORDER_COLOR_STATE { + union tagTheStructure { + struct tagCommon { + // DWORD 0 + float BorderColorRed; + // DWORD 1 + float BorderColorGreen; + // DWORD 2 + float BorderColorBlue; + // DWORD 3 + float BorderColorAlpha; + } Common; + uint32_t RawData[4]; + } TheStructure; + inline void init() { + memset(&TheStructure, 0, sizeof(TheStructure)); + TheStructure.Common.BorderColorRed = 0.0; + TheStructure.Common.BorderColorGreen = 0.0; + TheStructure.Common.BorderColorBlue = 0.0; + TheStructure.Common.BorderColorAlpha = 0.0; + } + static tagSAMPLER_BORDER_COLOR_STATE sInit() { + SAMPLER_BORDER_COLOR_STATE state; + state.init(); + return state; + } + inline uint32_t &getRawData(const uint32_t index) { + UNRECOVERABLE_IF(index >= 4); + return TheStructure.RawData[index]; + } + inline void setBorderColorRed(const float value) { + TheStructure.Common.BorderColorRed = value; + } + inline float getBorderColorRed() const { + return TheStructure.Common.BorderColorRed; + } + inline void setBorderColorGreen(const float value) { + TheStructure.Common.BorderColorGreen = value; + } + inline float getBorderColorGreen() const { + return TheStructure.Common.BorderColorGreen; + } + inline void setBorderColorBlue(const float value) { + TheStructure.Common.BorderColorBlue = value; + } + inline float getBorderColorBlue() const { + return TheStructure.Common.BorderColorBlue; + } + inline void setBorderColorAlpha(const float value) { + TheStructure.Common.BorderColorAlpha = value; + } + inline float getBorderColorAlpha() const { + return TheStructure.Common.BorderColorAlpha; + } +} SAMPLER_BORDER_COLOR_STATE; +STATIC_ASSERT(16 == sizeof(SAMPLER_BORDER_COLOR_STATE)); + +#pragma pack() diff --git a/shared/source/helpers/CMakeLists.txt b/shared/source/helpers/CMakeLists.txt index 2b85fc01b8..db926d5f4f 100644 --- a/shared/source/helpers/CMakeLists.txt +++ b/shared/source/helpers/CMakeLists.txt @@ -150,6 +150,12 @@ if(SUPPORT_DG2_AND_LATER) ) endif() +if(SUPPORT_PVC_AND_LATER) + list(APPEND NEO_CORE_HELPERS + ${CMAKE_CURRENT_SOURCE_DIR}/hw_helper_pvc_and_later.inl + ) +endif() + set(NEO_CORE_HELPERS_GMM_CALLBACKS_WINDOWS ${CMAKE_CURRENT_SOURCE_DIR}/windows/gmm_callbacks.cpp ${CMAKE_CURRENT_SOURCE_DIR}/windows/gmm_callbacks.h diff --git a/shared/source/helpers/definitions/hw_cmds.h b/shared/source/helpers/definitions/hw_cmds.h index 1d6df4ea14..3fa087102d 100644 --- a/shared/source/helpers/definitions/hw_cmds.h +++ b/shared/source/helpers/definitions/hw_cmds.h @@ -23,4 +23,7 @@ #endif #ifdef SUPPORT_XE_HPG_CORE #include "shared/source/xe_hpg_core/hw_cmds.h" -#endif \ No newline at end of file +#endif +#ifdef SUPPORT_XE_HPC_CORE +#include "shared/source/xe_hpc_core/hw_cmds.h" +#endif diff --git a/shared/source/helpers/hw_helper_pvc_and_later.inl b/shared/source/helpers/hw_helper_pvc_and_later.inl new file mode 100644 index 0000000000..a51c1690e2 --- /dev/null +++ b/shared/source/helpers/hw_helper_pvc_and_later.inl @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/helpers/hw_helper.h" +#include "shared/source/helpers/hw_info.h" + +namespace NEO { + +template <> +bool HwHelperHw::isCpuImageTransferPreferred(const HardwareInfo &hwInfo) const { + return !hwInfo.capabilityTable.supportsImages; +} + +template <> +bool HwHelperHw::isRcsAvailable(const HardwareInfo &hwInfo) const { + auto defaultEngine = getChosenEngineType(hwInfo); + return (defaultEngine == aub_stream::EngineType::ENGINE_RCS) || + (defaultEngine == aub_stream::EngineType::ENGINE_CCCS) || hwInfo.featureTable.flags.ftrRcsNode; +} + +template <> +bool HwHelperHw::isCooperativeDispatchSupported(const EngineGroupType engineGroupType, const HardwareInfo &hwInfo) const { + if (isCooperativeEngineSupported(hwInfo)) { + if (engineGroupType == EngineGroupType::RenderCompute) { + return false; + } + + bool isExclusiveContextUsed = (engineGroupType == EngineGroupType::CooperativeCompute); + return !isRcsAvailable(hwInfo) || isExclusiveContextUsed; + } + + return true; +} + +template <> +uint32_t HwHelperHw::adjustMaxWorkGroupCount(uint32_t maxWorkGroupCount, const EngineGroupType engineGroupType, + const HardwareInfo &hwInfo, bool isEngineInstanced) const { + if (!isCooperativeDispatchSupported(engineGroupType, hwInfo)) { + return 1u; + } + + bool requiresLimitation = this->isCooperativeEngineSupported(hwInfo) && + (engineGroupType != EngineGroupType::CooperativeCompute) && + (!isEngineInstanced) && + (DebugManager.flags.OverrideMaxWorkGroupCount.get() == -1); + if (requiresLimitation) { + auto ccsCount = hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled; + UNRECOVERABLE_IF(ccsCount == 0); + return maxWorkGroupCount / ccsCount; + } + return maxWorkGroupCount; +} + +template <> +bool HwHelperHw::isEngineTypeRemappingToHwSpecificRequired() const { + return true; +} + +} // namespace NEO diff --git a/shared/source/xe_hpc_core/CMakeLists.txt b/shared/source/xe_hpc_core/CMakeLists.txt new file mode 100644 index 0000000000..bdd5ce5ea5 --- /dev/null +++ b/shared/source/xe_hpc_core/CMakeLists.txt @@ -0,0 +1,15 @@ +# +# Copyright (C) 2021 Intel Corporation +# +# SPDX-License-Identifier: MIT +# + +if(SUPPORT_XE_HPC_CORE) + set(HW_DEFINITIONS_XE_HPC_CORE + ${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt + ${CMAKE_CURRENT_SOURCE_DIR}/definitions${BRANCH_DIR_SUFFIX}hw_cmds_pvc.inl + ) + set_property(GLOBAL APPEND PROPERTY CORE_SRCS_GENX_ALL_BASE ${HW_DEFINITIONS_XE_HPC_CORE}) + + add_subdirectories() +endif() diff --git a/shared/source/xe_hpc_core/aub_command_stream_receiver_xe_hpc_core.cpp b/shared/source/xe_hpc_core/aub_command_stream_receiver_xe_hpc_core.cpp new file mode 100644 index 0000000000..8e0c1bbd0f --- /dev/null +++ b/shared/source/xe_hpc_core/aub_command_stream_receiver_xe_hpc_core.cpp @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/command_stream/aub_command_stream_receiver_hw_xehp_and_later.inl" +#include "shared/source/helpers/array_count.h" +#include "shared/source/helpers/populate_factory.h" + +namespace NEO { + +using Family = XE_HPC_COREFamily; +static auto gfxCore = IGFX_XE_HPC_CORE; + +template <> +void populateFactoryTable>() { + extern AubCommandStreamReceiverCreateFunc aubCommandStreamReceiverFactory[IGFX_MAX_CORE]; + UNRECOVERABLE_IF(!isInRange(gfxCore, aubCommandStreamReceiverFactory)); + aubCommandStreamReceiverFactory[gfxCore] = AUBCommandStreamReceiverHw::create; +} + +template class AUBCommandStreamReceiverHw; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/aub_mapper.h b/shared/source/xe_hpc_core/aub_mapper.h new file mode 100644 index 0000000000..bd9893f69a --- /dev/null +++ b/shared/source/xe_hpc_core/aub_mapper.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include "shared/source/aub/aub_mapper_base.h" +#include "shared/source/helpers/constants.h" + +#include "engine_node.h" + +namespace NEO { +struct XE_HPC_COREFamily; + +template <> +struct AUBFamilyMapper { + enum { device = AubMemDump::DeviceValues::Pvc }; + + using AubTraits = AubMemDump::Traits; + + static const AubMemDump::LrcaHelper *const csTraits[aub_stream::NUM_ENGINES]; + + static const MMIOList globalMMIO; + static const MMIOList *perEngineMMIO[aub_stream::NUM_ENGINES]; + + using AUB = AubMemDump::AubDump; +}; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/aub_mem_dump_xe_hpc_core.cpp b/shared/source/xe_hpc_core/aub_mem_dump_xe_hpc_core.cpp new file mode 100644 index 0000000000..195721ac1d --- /dev/null +++ b/shared/source/xe_hpc_core/aub_mem_dump_xe_hpc_core.cpp @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/aub/aub_helper_xehp_and_later.inl" + +#include "aub_mem_dump.h" + +namespace NEO { +struct XE_HPC_COREFamily; +using Family = NEO::XE_HPC_COREFamily; +constexpr static auto deviceValue = AubMemDump::DeviceValues::Pvc; + +template class AubHelperHw; +} // namespace NEO + +#include "shared/source/aub_mem_dump/aub_mem_dump_pvc_and_later.inl" diff --git a/shared/source/xe_hpc_core/command_encoder_xe_hpc_core.cpp b/shared/source/xe_hpc_core/command_encoder_xe_hpc_core.cpp new file mode 100644 index 0000000000..85b6ade0e1 --- /dev/null +++ b/shared/source/xe_hpc_core/command_encoder_xe_hpc_core.cpp @@ -0,0 +1,268 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/command_container/command_encoder.h" +#include "shared/source/command_container/command_encoder.inl" +#include "shared/source/command_container/command_encoder_xehp_and_later.inl" +#include "shared/source/command_container/encode_compute_mode_tgllp_and_later.inl" +#include "shared/source/command_stream/stream_properties.h" +#include "shared/source/helpers/constants.h" +#include "shared/source/kernel/grf_config.h" +#include "shared/source/xe_hpc_core/hw_cmds_base.h" + +namespace NEO { + +using Family = XE_HPC_COREFamily; +} + +#include "shared/source/command_container/command_encoder_xe_hpg_core_and_later.inl" +#include "shared/source/command_container/image_surface_state/compression_params_tgllp_and_later.inl" +#include "shared/source/command_container/image_surface_state/compression_params_xehp_and_later.inl" + +namespace NEO { + +template <> +void EncodeDispatchKernel::adjustTimestampPacket(WALKER_TYPE &walkerCmd, const HardwareInfo &hwInfo) { + walkerCmd.getPostSync().setDataportSubsliceCacheFlush(true); +} + +template <> +void EncodeDispatchKernel::adjustInterfaceDescriptorData(INTERFACE_DESCRIPTOR_DATA &interfaceDescriptor, const HardwareInfo &hwInfo) { + const auto &hwInfoConfig = *HwInfoConfig::get(hwInfo.platform.eProductFamily); + if (hwInfoConfig.isDisableOverdispatchAvailable(hwInfo)) { + interfaceDescriptor.setThreadGroupDispatchSize(3u); + } + + if (DebugManager.flags.ForceThreadGroupDispatchSize.get() != -1) { + interfaceDescriptor.setThreadGroupDispatchSize(DebugManager.flags.ForceThreadGroupDispatchSize.get()); + } +} + +template <> +inline void EncodeAtomic::setMiAtomicAddress(MI_ATOMIC &atomic, uint64_t writeAddress) { + atomic.setMemoryAddress(writeAddress); +} + +template <> +void EncodeComputeMode::adjustComputeMode(LinearStream &csr, void *const stateComputeModePtr, StateComputeModeProperties &properties, const HardwareInfo &hwInfo) { + using STATE_COMPUTE_MODE = typename Family::STATE_COMPUTE_MODE; + using FORCE_NON_COHERENT = typename STATE_COMPUTE_MODE::FORCE_NON_COHERENT; + + STATE_COMPUTE_MODE stateComputeMode = (stateComputeModePtr != nullptr) ? *(static_cast(stateComputeModePtr)) : Family::cmdInitStateComputeMode; + auto maskBits = stateComputeMode.getMaskBits(); + + if (properties.isCoherencyRequired.isDirty) { + FORCE_NON_COHERENT coherencyValue = !properties.isCoherencyRequired.value ? FORCE_NON_COHERENT::FORCE_NON_COHERENT_FORCE_GPU_NON_COHERENT + : FORCE_NON_COHERENT::FORCE_NON_COHERENT_FORCE_DISABLED; + stateComputeMode.setForceNonCoherent(coherencyValue); + maskBits |= Family::stateComputeModeForceNonCoherentMask; + } + + if (properties.threadArbitrationPolicy.isDirty) { + switch (properties.threadArbitrationPolicy.value) { + case ThreadArbitrationPolicy::RoundRobin: + stateComputeMode.setEuThreadSchedulingModeOverride(STATE_COMPUTE_MODE::EU_THREAD_SCHEDULING_MODE_OVERRIDE::EU_THREAD_SCHEDULING_MODE_OVERRIDE_ROUND_ROBIN); + break; + case ThreadArbitrationPolicy::AgeBased: + stateComputeMode.setEuThreadSchedulingModeOverride(STATE_COMPUTE_MODE::EU_THREAD_SCHEDULING_MODE_OVERRIDE::EU_THREAD_SCHEDULING_MODE_OVERRIDE_OLDEST_FIRST); + break; + case ThreadArbitrationPolicy::RoundRobinAfterDependency: + stateComputeMode.setEuThreadSchedulingModeOverride(STATE_COMPUTE_MODE::EU_THREAD_SCHEDULING_MODE_OVERRIDE::EU_THREAD_SCHEDULING_MODE_OVERRIDE_STALL_BASED_ROUND_ROBIN); + break; + default: + stateComputeMode.setEuThreadSchedulingModeOverride(STATE_COMPUTE_MODE::EU_THREAD_SCHEDULING_MODE_OVERRIDE::EU_THREAD_SCHEDULING_MODE_OVERRIDE_HW_DEFAULT); + } + maskBits |= Family::stateComputeModeEuThreadSchedulingModeOverrideMask; + } + + if (properties.largeGrfMode.isDirty) { + stateComputeMode.setLargeGrfMode(properties.largeGrfMode.value); + maskBits |= Family::stateComputeModeLargeGrfModeMask; + } + + stateComputeMode.setMaskBits(maskBits); + + auto buffer = csr.getSpaceForCmd(); + *buffer = stateComputeMode; +} + +template <> +void EncodeMemoryPrefetch::programMemoryPrefetch(LinearStream &commandStream, const GraphicsAllocation &graphicsAllocation, uint32_t size, size_t offset, const HardwareInfo &hwInfo) { + using STATE_PREFETCH = typename Family::STATE_PREFETCH; + constexpr uint32_t mocsIndexForL3 = (2 << 1); + + bool isBaseDieA0 = (hwInfo.platform.usRevId & Family::pvcBaseDieRevMask) == Family::pvcBaseDieA0Masked; + + bool prefetch = !isBaseDieA0; + if (DebugManager.flags.EnableMemoryPrefetch.get() != -1) { + prefetch = !!DebugManager.flags.EnableMemoryPrefetch.get(); + } + + if (!prefetch) { + return; + } + + uint64_t gpuVa = graphicsAllocation.getGpuAddress() + offset; + + while (size > 0) { + uint32_t sizeInBytsToPrefetch = std::min(alignUp(size, MemoryConstants::cacheLineSize), + static_cast(MemoryConstants::pageSize64k)); + + // zero based cacheline count (0 == 1 cacheline) + uint32_t prefetchSize = (sizeInBytsToPrefetch / MemoryConstants::cacheLineSize) - 1; + + auto statePrefetch = commandStream.getSpaceForCmd(); + STATE_PREFETCH cmd = Family::cmdInitStatePrefetch; + + cmd.setAddress(gpuVa); + cmd.setPrefetchSize(prefetchSize); + cmd.setMemoryObjectControlState(mocsIndexForL3); + cmd.setKernelInstructionPrefetch(GraphicsAllocation::isIsaAllocationType(graphicsAllocation.getAllocationType())); + + if (DebugManager.flags.ForceCsStallForStatePrefetch.get() == 1) { + cmd.setParserStall(true); + } + + *statePrefetch = cmd; + + if (sizeInBytsToPrefetch > size) { + break; + } + + gpuVa += sizeInBytsToPrefetch; + size -= sizeInBytsToPrefetch; + } +} + +template <> +size_t EncodeMemoryPrefetch::getSizeForMemoryPrefetch(size_t size) { + if (DebugManager.flags.EnableMemoryPrefetch.get() == 0) { + return 0; + } + + size = alignUp(size, MemoryConstants::pageSize64k); + + size_t count = size / MemoryConstants::pageSize64k; + + return (count * sizeof(typename Family::STATE_PREFETCH)); +} + +template <> +inline void EncodeMiFlushDW::appendMiFlushDw(MI_FLUSH_DW *miFlushDwCmd) { + miFlushDwCmd->setFlushLlc(1); +} + +template <> +inline void EncodeMiFlushDW::programMiFlushDwWA(LinearStream &commandStream) { +} + +template <> +size_t EncodeMiFlushDW::getMiFlushDwWaSize() { + return 0; +} + +template <> +void EncodeDispatchKernel::programBarrierEnable(INTERFACE_DESCRIPTOR_DATA &interfaceDescriptor, + uint32_t value, + const HardwareInfo &hwInfo) { + interfaceDescriptor.setNumberOfBarriers(value); +} + +template <> +void EncodeDispatchKernel::encodeAdditionalWalkerFields(const HardwareInfo &hwInfo, WALKER_TYPE &walkerCmd) { + auto programGlobalFenceAsPostSyncOperationInComputeWalker = !Family::isXlA0(hwInfo); + if (DebugManager.flags.ProgramGlobalFenceAsPostSyncOperationInComputeWalker.get() != -1) { + programGlobalFenceAsPostSyncOperationInComputeWalker = !!DebugManager.flags.ProgramGlobalFenceAsPostSyncOperationInComputeWalker.get(); + } + if (programGlobalFenceAsPostSyncOperationInComputeWalker) { + auto &postSyncData = walkerCmd.getPostSync(); + postSyncData.setSystemMemoryFenceRequest(true); + } + + if (DebugManager.flags.ForceL3PrefetchForComputeWalker.get() != -1) { + walkerCmd.setL3PrefetchDisable(!DebugManager.flags.ForceL3PrefetchForComputeWalker.get()); + } +} + +template <> +void EncodeDispatchKernel::appendAdditionalIDDFields(INTERFACE_DESCRIPTOR_DATA *pInterfaceDescriptor, const HardwareInfo &hwInfo, const uint32_t threadsPerThreadGroup, uint32_t slmTotalSize, SlmPolicy slmPolicy) { + using PREFERRED_SLM_SIZE_OVERRIDE = typename Family::INTERFACE_DESCRIPTOR_DATA::PREFERRED_SLM_SIZE_OVERRIDE; + using PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS = typename Family::INTERFACE_DESCRIPTOR_DATA::PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS; + + const uint32_t threadsPerDssCount = hwInfo.gtSystemInfo.ThreadCount / hwInfo.gtSystemInfo.DualSubSliceCount; + const uint32_t workGroupCountPerDss = static_cast(Math::divideAndRoundUp(threadsPerDssCount, threadsPerThreadGroup)); + const uint32_t workgroupSlmSize = HwHelperHw::get().alignSlmSize(slmTotalSize); + + uint32_t slmSize = 0u; + + switch (slmPolicy) { + case SlmPolicy::SlmPolicyLargeData: + slmSize = workgroupSlmSize; + break; + case SlmPolicy::SlmPolicyLargeSlm: + default: + slmSize = workgroupSlmSize * workGroupCountPerDss; + break; + } + + struct SizeToPreferredSlmValue { + uint32_t upperLimit; + PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS valueToProgram; + }; + const std::array ranges = {{ + // upper limit, retVal + {0, PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_0K}, + {16 * KB, PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_16K}, + {32 * KB, PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_32K}, + {64 * KB, PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_64K}, + {96 * KB, PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_96K}, + }}; + + auto programmableIdPreferredSlmSize = PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_128K; + for (auto &range : ranges) { + if (slmSize <= range.upperLimit) { + programmableIdPreferredSlmSize = range.valueToProgram; + break; + } + } + + if ((slmSize == 0) && (Family::isXlA0(hwInfo))) { + programmableIdPreferredSlmSize = PREFERRED_SLM_ALLOCATION_SIZE_PER_DSS::PREFERRED_SLM_SIZE_IS_16K; + } + + pInterfaceDescriptor->setPreferredSlmSizeOverride(PREFERRED_SLM_SIZE_OVERRIDE::PREFERRED_SLM_SIZE_OVERRIDE_IS_ENABLED); + pInterfaceDescriptor->setPreferredSlmAllocationSizePerDss(programmableIdPreferredSlmSize); + + if (DebugManager.flags.OverridePreferredSlmAllocationSizePerDss.get() != -1) { + auto toProgram = + static_cast(DebugManager.flags.OverridePreferredSlmAllocationSizePerDss.get()); + pInterfaceDescriptor->setPreferredSlmAllocationSizePerDss(toProgram); + } +} + +template struct EncodeDispatchKernel; +template struct EncodeStates; +template struct EncodeMath; +template struct EncodeMathMMIO; +template struct EncodeIndirectParams; +template struct EncodeSetMMIO; +template struct EncodeMediaInterfaceDescriptorLoad; +template struct EncodeStateBaseAddress; +template struct EncodeStoreMMIO; +template struct EncodeSurfaceState; +template struct EncodeComputeMode; +template struct EncodeAtomic; +template struct EncodeSempahore; +template struct EncodeBatchBufferStartOrEnd; +template struct EncodeMiFlushDW; +template struct EncodeMemoryPrefetch; +template struct EncodeMiArbCheck; +template struct EncodeWA; +template struct EncodeEnableRayTracing; +template struct EncodeNoop; +template struct EncodeStoreMemory; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/command_stream_receiver_hw_xe_hpc_core.cpp b/shared/source/xe_hpc_core/command_stream_receiver_hw_xe_hpc_core.cpp new file mode 100644 index 0000000000..351ca08ed8 --- /dev/null +++ b/shared/source/xe_hpc_core/command_stream_receiver_hw_xe_hpc_core.cpp @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/command_container/memory_fence_encoder.h" +#include "shared/source/xe_hpc_core/hw_cmds.h" +#include "shared/source/xe_hpc_core/hw_info.h" + +using Family = NEO::XE_HPC_COREFamily; + +#include "shared/source/command_stream/command_stream_receiver_hw_dg2_and_later.inl" +#include "shared/source/command_stream/command_stream_receiver_hw_tgllp_and_later.inl" +#include "shared/source/command_stream/command_stream_receiver_hw_xehp_and_later.inl" +#include "shared/source/helpers/blit_commands_helper_xehp_and_later.inl" +#include "shared/source/helpers/populate_factory.h" +#include "shared/source/helpers/state_compute_mode_helper.h" + +namespace NEO { +static auto gfxCore = IGFX_XE_HPC_CORE; + +template <> +bool ImplicitFlushSettings::defaultSettingForNewResource = false; +template <> +bool ImplicitFlushSettings::defaultSettingForGpuIdle = false; +template class ImplicitFlushSettings; + +template <> +void populateFactoryTable>() { + extern CommandStreamReceiverCreateFunc commandStreamReceiverFactory[2 * IGFX_MAX_CORE]; + commandStreamReceiverFactory[gfxCore] = DeviceCommandStreamReceiver::create; +} + +template <> +void CommandStreamReceiverHw::programEnginePrologue(LinearStream &csr) { + if (!this->isEnginePrologueSent) { + if (globalFenceAllocation) { + EncodeMemoryFence::encodeSystemMemoryFence(csr, globalFenceAllocation); + } + this->isEnginePrologueSent = true; + } +} + +template <> +size_t CommandStreamReceiverHw::getCmdSizeForPrologue() const { + if (!this->isEnginePrologueSent) { + if (globalFenceAllocation) { + return sizeof(Family::STATE_SYSTEM_MEM_FENCE_ADDRESS); + } + } + return 0u; +} + +template <> +void BlitCommandsHelper::appendBlitCommandsForBuffer(const BlitProperties &blitProperites, typename Family::XY_COPY_BLT &blitCmd, + const RootDeviceEnvironment &rootDeviceEnvironment) { + using MEM_COPY = typename Family::MEM_COPY; + + auto dstAllocation = blitProperites.dstAllocation; + auto srcAllocation = blitProperites.srcAllocation; + + if (blitCmd.getDestinationY2CoordinateBottom() > 1) { + blitCmd.setCopyType(MEM_COPY::COPY_TYPE::COPY_TYPE_MATRIX_COPY); + } else { + blitCmd.setCopyType(MEM_COPY::COPY_TYPE::COPY_TYPE_LINEAR_COPY); + } + + auto mocsL3enabled = rootDeviceEnvironment.getGmmHelper()->getMOCS(GMM_RESOURCE_USAGE_OCL_BUFFER); + blitCmd.setDestinationMOCS(mocsL3enabled); + blitCmd.setSourceMOCS(mocsL3enabled); + if (DebugManager.flags.OverrideBlitterMocs.get() != -1) { + blitCmd.setDestinationMOCS(DebugManager.flags.OverrideBlitterMocs.get()); + blitCmd.setSourceMOCS(DebugManager.flags.OverrideBlitterMocs.get()); + } + + if (dstAllocation->isCompressionEnabled()) { + auto resourceFormat = dstAllocation->getDefaultGmm()->gmmResourceInfo->getResourceFormat(); + auto compressionFormat = rootDeviceEnvironment.getGmmClientContext()->getSurfaceStateCompressionFormat(resourceFormat); + blitCmd.setDestinationCompressible(MEM_COPY::DESTINATION_COMPRESSIBLE::DESTINATION_COMPRESSIBLE_COMPRESSIBLE); + blitCmd.setCompressionFormat(compressionFormat); + } + if (srcAllocation->isCompressionEnabled()) { + auto resourceFormat = srcAllocation->getDefaultGmm()->gmmResourceInfo->getResourceFormat(); + auto compressionFormat = rootDeviceEnvironment.getGmmClientContext()->getSurfaceStateCompressionFormat(resourceFormat); + blitCmd.setSourceCompressible(MEM_COPY::SOURCE_COMPRESSIBLE::SOURCE_COMPRESSIBLE_COMPRESSIBLE); + blitCmd.setCompressionFormat(compressionFormat); + } + + if (DebugManager.flags.EnableStatelessCompressionWithUnifiedMemory.get()) { + if (!MemoryPool::isSystemMemoryPool(srcAllocation->getMemoryPool())) { + blitCmd.setSourceCompressible(MEM_COPY::SOURCE_COMPRESSIBLE::SOURCE_COMPRESSIBLE_COMPRESSIBLE); + blitCmd.setCompressionFormat(DebugManager.flags.FormatForStatelessCompressionWithUnifiedMemory.get()); + } + if (!MemoryPool::isSystemMemoryPool(dstAllocation->getMemoryPool())) { + blitCmd.setDestinationCompressible(MEM_COPY::DESTINATION_COMPRESSIBLE::DESTINATION_COMPRESSIBLE_COMPRESSIBLE); + blitCmd.setCompressionFormat(DebugManager.flags.FormatForStatelessCompressionWithUnifiedMemory.get()); + } + } + + if (blitCmd.getDestinationCompressible() == MEM_COPY::DESTINATION_COMPRESSIBLE::DESTINATION_COMPRESSIBLE_COMPRESSIBLE && + AuxTranslationDirection::AuxToNonAux != blitProperites.auxTranslationDirection) { + blitCmd.setDestinationCompressionEnable(MEM_COPY::DESTINATION_COMPRESSION_ENABLE::DESTINATION_COMPRESSION_ENABLE_ENABLE); + } else { + blitCmd.setDestinationCompressionEnable(MEM_COPY::DESTINATION_COMPRESSION_ENABLE::DESTINATION_COMPRESSION_ENABLE_DISABLE); + } + + DEBUG_BREAK_IF((AuxTranslationDirection::None != blitProperites.auxTranslationDirection) && + (dstAllocation != srcAllocation || !dstAllocation->isCompressionEnabled())); +} + +template <> +template <> +void BlitCommandsHelper::dispatchBlitMemoryFill<1>(NEO::GraphicsAllocation *dstAlloc, uint64_t offset, uint32_t *pattern, LinearStream &linearStream, size_t size, const RootDeviceEnvironment &rootDeviceEnvironment, COLOR_DEPTH depth) { + using MEM_SET = typename Family::MEM_SET; + auto blitCmd = Family::cmdInitMemSet; + + auto mocsL3enabled = rootDeviceEnvironment.getGmmHelper()->getMOCS(GMM_RESOURCE_USAGE_OCL_BUFFER); + blitCmd.setDestinationMOCS(mocsL3enabled); + if (DebugManager.flags.OverrideBlitterMocs.get() != -1) { + blitCmd.setDestinationMOCS(DebugManager.flags.OverrideBlitterMocs.get()); + } + + if (dstAlloc->isCompressionEnabled()) { + auto resourceFormat = dstAlloc->getDefaultGmm()->gmmResourceInfo->getResourceFormat(); + auto compressionFormat = rootDeviceEnvironment.getGmmClientContext()->getSurfaceStateCompressionFormat(resourceFormat); + blitCmd.setDestinationCompressible(MEM_SET::DESTINATION_COMPRESSIBLE::DESTINATION_COMPRESSIBLE_COMPRESSIBLE); + blitCmd.setCompressionFormat40(compressionFormat); + } + if (DebugManager.flags.EnableStatelessCompressionWithUnifiedMemory.get()) { + if (!MemoryPool::isSystemMemoryPool(dstAlloc->getMemoryPool())) { + blitCmd.setDestinationCompressible(MEM_SET::DESTINATION_COMPRESSIBLE::DESTINATION_COMPRESSIBLE_COMPRESSIBLE); + blitCmd.setCompressionFormat40(DebugManager.flags.FormatForStatelessCompressionWithUnifiedMemory.get()); + } + } + + if (blitCmd.getDestinationCompressible() == MEM_SET::DESTINATION_COMPRESSIBLE::DESTINATION_COMPRESSIBLE_COMPRESSIBLE) { + blitCmd.setDestinationCompressionEnable(MEM_SET::DESTINATION_COMPRESSION_ENABLE::DESTINATION_COMPRESSION_ENABLE_ENABLE); + } else { + blitCmd.setDestinationCompressionEnable(MEM_SET::DESTINATION_COMPRESSION_ENABLE::DESTINATION_COMPRESSION_ENABLE_DISABLE); + } + blitCmd.setFillData(*pattern); + + auto sizeToFill = size; + while (sizeToFill != 0) { + auto tmpCmd = blitCmd; + tmpCmd.setDestinationStartAddress(ptrOffset(dstAlloc->getGpuAddress(), static_cast(offset))); + size_t height = 0; + size_t width = 0; + if (sizeToFill <= BlitterConstants::maxBlitSetWidth) { + width = sizeToFill; + height = 1; + } else { + width = BlitterConstants::maxBlitSetWidth; + height = std::min((sizeToFill / width), BlitterConstants::maxBlitSetHeight); + if (height > 1) { + tmpCmd.setFillType(MEM_SET::FILL_TYPE::FILL_TYPE_MATRIX_FILL); + } + } + tmpCmd.setFillWidth(static_cast(width)); + tmpCmd.setFillHeight(static_cast(height)); + tmpCmd.setDestinationPitch(static_cast(width)); + + auto cmd = linearStream.getSpaceForCmd(); + *cmd = tmpCmd; + + auto blitSize = width * height; + offset += blitSize; + sizeToFill -= blitSize; + } +} + +template <> +void BlitCommandsHelper::dispatchBlitCommandsRegion(const BlitProperties &blitProperties, LinearStream &linearStream, const RootDeviceEnvironment &rootDeviceEnvironment) {} + +template <> +void BlitCommandsHelper::appendBlitCommandsForImages(const BlitProperties &blitProperties, typename Family::XY_COPY_BLT &blitCmd, const RootDeviceEnvironment &rootDeviceEnvironment, uint32_t &srcSlicePitch, uint32_t &dstSlicePitch) {} + +template <> +void BlitCommandsHelper::appendTilingType(const GMM_TILE_TYPE srcTilingType, const GMM_TILE_TYPE dstTilingType, typename Family::XY_COPY_BLT &blitCmd) {} + +template <> +void BlitCommandsHelper::appendSliceOffsets(const BlitProperties &blitProperties, typename Family::XY_COPY_BLT &blitCmd, uint32_t sliceIndex, const RootDeviceEnvironment &rootDeviceEnvironment, uint32_t srcSlicePitch, uint32_t dstSlicePitch) {} + +template <> +void BlitCommandsHelper::appendSurfaceType(const BlitProperties &blitProperties, typename Family::XY_COPY_BLT &blitCmd) { +} + +template <> +void BlitCommandsHelper::appendColorDepth(const BlitProperties &blitProperites, typename Family::XY_COPY_BLT &blitCmd) {} + +template <> +bool BlitCommandsHelper::useOneBlitCopyCommand(const Vec3 ©Size, uint32_t bytesPerPixel) { + return false; +} + +template class CommandStreamReceiverHw; +template struct BlitCommandsHelper; + +const Family::COMPUTE_WALKER Family::cmdInitGpgpuWalker = Family::COMPUTE_WALKER::sInit(); +const Family::CFE_STATE Family::cmdInitCfeState = Family::CFE_STATE::sInit(); +const Family::INTERFACE_DESCRIPTOR_DATA Family::cmdInitInterfaceDescriptorData = Family::INTERFACE_DESCRIPTOR_DATA::sInit(); +const Family::MI_BATCH_BUFFER_START Family::cmdInitBatchBufferStart = Family::MI_BATCH_BUFFER_START::sInit(); +const Family::MI_BATCH_BUFFER_END Family::cmdInitBatchBufferEnd = Family::MI_BATCH_BUFFER_END::sInit(); +const Family::PIPE_CONTROL Family::cmdInitPipeControl = Family::PIPE_CONTROL::sInit(); +const Family::STATE_COMPUTE_MODE Family::cmdInitStateComputeMode = Family::STATE_COMPUTE_MODE::sInit(); +const Family::_3DSTATE_BINDING_TABLE_POOL_ALLOC Family::cmdInitStateBindingTablePoolAlloc = + Family::_3DSTATE_BINDING_TABLE_POOL_ALLOC::sInit(); +const Family::MI_SEMAPHORE_WAIT Family::cmdInitMiSemaphoreWait = Family::MI_SEMAPHORE_WAIT::sInit(); +const Family::RENDER_SURFACE_STATE Family::cmdInitRenderSurfaceState = Family::RENDER_SURFACE_STATE::sInit(); +const Family::POSTSYNC_DATA Family::cmdInitPostSyncData = Family::POSTSYNC_DATA::sInit(); +const Family::MI_SET_PREDICATE Family::cmdInitSetPredicate = Family::MI_SET_PREDICATE::sInit(); +const Family::MI_LOAD_REGISTER_IMM Family::cmdInitLoadRegisterImm = Family::MI_LOAD_REGISTER_IMM::sInit(); +const Family::MI_LOAD_REGISTER_REG Family::cmdInitLoadRegisterReg = Family::MI_LOAD_REGISTER_REG::sInit(); +const Family::MI_LOAD_REGISTER_MEM Family::cmdInitLoadRegisterMem = Family::MI_LOAD_REGISTER_MEM::sInit(); +const Family::MI_STORE_DATA_IMM Family::cmdInitStoreDataImm = Family::MI_STORE_DATA_IMM::sInit(); +const Family::MI_STORE_REGISTER_MEM Family::cmdInitStoreRegisterMem = Family::MI_STORE_REGISTER_MEM::sInit(); +const Family::MI_NOOP Family::cmdInitNoop = Family::MI_NOOP::sInit(); +const Family::MI_REPORT_PERF_COUNT Family::cmdInitReportPerfCount = Family::MI_REPORT_PERF_COUNT::sInit(); +const Family::MI_ATOMIC Family::cmdInitAtomic = Family::MI_ATOMIC::sInit(); +const Family::PIPELINE_SELECT Family::cmdInitPipelineSelect = Family::PIPELINE_SELECT::sInit(); +const Family::MI_ARB_CHECK Family::cmdInitArbCheck = Family::MI_ARB_CHECK::sInit(); +const Family::STATE_BASE_ADDRESS Family::cmdInitStateBaseAddress = Family::STATE_BASE_ADDRESS::sInit(); +const Family::MEDIA_SURFACE_STATE Family::cmdInitMediaSurfaceState = Family::MEDIA_SURFACE_STATE::sInit(); +const Family::SAMPLER_STATE Family::cmdInitSamplerState = Family::SAMPLER_STATE::sInit(); +const Family::BINDING_TABLE_STATE Family::cmdInitBindingTableState = Family::BINDING_TABLE_STATE::sInit(); +const Family::MI_USER_INTERRUPT Family::cmdInitUserInterrupt = Family::MI_USER_INTERRUPT::sInit(); +const Family::MI_CONDITIONAL_BATCH_BUFFER_END cmdInitConditionalBatchBufferEnd = Family::MI_CONDITIONAL_BATCH_BUFFER_END::sInit(); +const Family::MI_FLUSH_DW Family::cmdInitMiFlushDw = Family::MI_FLUSH_DW::sInit(); +const Family::MEM_COPY Family::cmdInitXyCopyBlt = Family::MEM_COPY::sInit(); +const Family::XY_FAST_COLOR_BLT Family::cmdInitXyColorBlt = Family::XY_FAST_COLOR_BLT::sInit(); +const Family::STATE_PREFETCH Family::cmdInitStatePrefetch = Family::STATE_PREFETCH::sInit(); +const Family::_3DSTATE_BTD Family::cmd3dStateBtd = Family::_3DSTATE_BTD::sInit(); +const Family::_3DSTATE_BTD_BODY Family::cmd3dStateBtdBody = Family::_3DSTATE_BTD_BODY::sInit(); +const Family::MI_MEM_FENCE Family::cmdInitMemFence = Family::MI_MEM_FENCE::sInit(); +const Family::MEM_SET Family::cmdInitMemSet = Family::MEM_SET::sInit(); +const Family::STATE_SIP Family::cmdInitStateSip = Family::STATE_SIP::sInit(); +const Family::STATE_SYSTEM_MEM_FENCE_ADDRESS Family::cmdInitStateSystemMemFenceAddress = Family::STATE_SYSTEM_MEM_FENCE_ADDRESS::sInit(); +} // namespace NEO diff --git a/shared/source/xe_hpc_core/command_stream_receiver_simulated_common_hw_xe_hpc_core.cpp b/shared/source/xe_hpc_core/command_stream_receiver_simulated_common_hw_xe_hpc_core.cpp new file mode 100644 index 0000000000..5e79e5856d --- /dev/null +++ b/shared/source/xe_hpc_core/command_stream_receiver_simulated_common_hw_xe_hpc_core.cpp @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/command_stream/command_stream_receiver_simulated_common_hw_xehp_and_later.inl" + +namespace NEO { +using Family = XE_HPC_COREFamily; + +template <> +bool CommandStreamReceiverSimulatedCommonHw::expectMemoryCompressed(void *gfxAddress, const void *srcAddress, size_t length) { + auto format = static_cast(DebugManager.flags.FormatForStatelessCompressionWithUnifiedMemory.get()); + UNRECOVERABLE_IF(format > 0x1F); + + uint32_t value = (format << 3); // [3:7] compression_format + value |= 0; // [0] disable + this->writeMMIO(0x519C, value); + this->writeMMIO(0xB0F0, value); + this->writeMMIO(0xE4C0, value); + + bool ret = this->expectMemory(gfxAddress, srcAddress, length, + AubMemDump::CmdServicesMemTraceMemoryCompare::CompareOperationValues::CompareNotEqual); + + value |= 1; // [0] enable + this->writeMMIO(0x519C, value); + this->writeMMIO(0xB0F0, value); + this->writeMMIO(0xE4C0, value); + + return ret; +} + +template class CommandStreamReceiverSimulatedCommonHw; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/compiler_hw_info_config_pvc.inl b/shared/source/xe_hpc_core/compiler_hw_info_config_pvc.inl new file mode 100644 index 0000000000..50abb46d6d --- /dev/null +++ b/shared/source/xe_hpc_core/compiler_hw_info_config_pvc.inl @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +template <> +bool CompilerHwInfoConfigHw::isForceToStatelessRequired() const { + return true; +} diff --git a/shared/source/xe_hpc_core/create_device_command_stream_receiver_xe_hpc_core.cpp b/shared/source/xe_hpc_core/create_device_command_stream_receiver_xe_hpc_core.cpp new file mode 100644 index 0000000000..2068c0c0da --- /dev/null +++ b/shared/source/xe_hpc_core/create_device_command_stream_receiver_xe_hpc_core.cpp @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/command_stream/device_command_stream.h" + +#include "create_command_stream_receiver.inl" + +namespace NEO { + +template <> +CommandStreamReceiver *createDeviceCommandStreamReceiver(bool withAubDump, + ExecutionEnvironment &executionEnvironment, + uint32_t rootDeviceIndex, + const DeviceBitfield deviceBitfield) { + return createCommandStreamReceiver(withAubDump, executionEnvironment, rootDeviceIndex, deviceBitfield); +} + +} // namespace NEO diff --git a/shared/source/xe_hpc_core/definitions/hw_cmds_pvc.inl b/shared/source/xe_hpc_core/definitions/hw_cmds_pvc.inl new file mode 100644 index 0000000000..af3c51cc00 --- /dev/null +++ b/shared/source/xe_hpc_core/definitions/hw_cmds_pvc.inl @@ -0,0 +1,6 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ diff --git a/shared/source/xe_hpc_core/definitions/hw_info_setup_pvc.inl b/shared/source/xe_hpc_core/definitions/hw_info_setup_pvc.inl new file mode 100644 index 0000000000..5a3b15cfb6 --- /dev/null +++ b/shared/source/xe_hpc_core/definitions/hw_info_setup_pvc.inl @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +const HardwareInfo PVC::hwInfo = PVC_CONFIG::hwInfo; +const uint64_t PVC::defaultHardwareInfoConfig = 0; + +void setupPVCHardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig) { + if (hwInfoConfig == 0x0) { + // Default config + PVC_CONFIG::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable); + } else { + UNRECOVERABLE_IF(true); + } +} + +void (*PVC::setupHardwareInfo)(HardwareInfo *, bool, const uint64_t) = setupPVCHardwareInfoImpl; \ No newline at end of file diff --git a/shared/source/xe_hpc_core/enable_family_full_core_xe_hpc_core.cpp b/shared/source/xe_hpc_core/enable_family_full_core_xe_hpc_core.cpp new file mode 100644 index 0000000000..3cfcb9ae2f --- /dev/null +++ b/shared/source/xe_hpc_core/enable_family_full_core_xe_hpc_core.cpp @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/helpers/hw_helper.h" +#include "shared/source/xe_hpc_core/hw_cmds.h" + +namespace NEO { + +extern HwHelper *hwHelperFactory[IGFX_MAX_CORE]; + +using Family = XE_HPC_COREFamily; +static auto gfxFamily = IGFX_XE_HPC_CORE; + +struct EnableCoreXeHpcCore { + EnableCoreXeHpcCore() { + hwHelperFactory[gfxFamily] = &HwHelperHw::get(); + } +}; + +static EnableCoreXeHpcCore enable; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/enable_hw_info_config_pvc.cpp b/shared/source/xe_hpc_core/enable_hw_info_config_pvc.cpp new file mode 100644 index 0000000000..e97ad9af49 --- /dev/null +++ b/shared/source/xe_hpc_core/enable_hw_info_config_pvc.cpp @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/os_interface/hw_info_config.h" +#include "shared/source/xe_hpc_core/hw_cmds.h" + +namespace NEO { + +static EnableProductHwInfoConfig enablePVC; + +} // namespace NEO diff --git a/shared/source/xe_hpc_core/enable_xe_hpc_core.cpp b/shared/source/xe_hpc_core/enable_xe_hpc_core.cpp new file mode 100644 index 0000000000..5b954d921f --- /dev/null +++ b/shared/source/xe_hpc_core/enable_xe_hpc_core.cpp @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/helpers/compiler_hw_info_config_base.inl" +#include "shared/source/helpers/compiler_hw_info_config_bdw_and_later.inl" +#include "shared/source/helpers/enable_product.inl" +#include "shared/source/os_interface/hw_info_config.h" +#include "shared/source/xe_hpc_core/hw_cmds.h" + +namespace NEO { + +#ifdef SUPPORT_PVC +static EnableGfxProductHw enableGfxProductHwPVC; +static EnableCompilerHwInfoConfig enableCompilerHwInfoConfigPVC; +#endif + +} // namespace NEO diff --git a/shared/source/xe_hpc_core/experimental_command_buffer_xe_hpc_core.cpp b/shared/source/xe_hpc_core/experimental_command_buffer_xe_hpc_core.cpp new file mode 100644 index 0000000000..9b0824feeb --- /dev/null +++ b/shared/source/xe_hpc_core/experimental_command_buffer_xe_hpc_core.cpp @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/command_stream/experimental_command_buffer.inl" + +namespace NEO { +using GfxFamily = XE_HPC_COREFamily; + +template void ExperimentalCommandBuffer::injectBufferStart(LinearStream &parentStream, size_t cmdBufferOffset); +template size_t ExperimentalCommandBuffer::getRequiredInjectionSize() noexcept; + +template size_t ExperimentalCommandBuffer::programExperimentalCommandBuffer(); +template size_t ExperimentalCommandBuffer::getTotalExperimentalSize() noexcept; + +template void ExperimentalCommandBuffer::addTimeStampPipeControl(); +template size_t ExperimentalCommandBuffer::getTimeStampPipeControlSize() noexcept; + +template void ExperimentalCommandBuffer::addExperimentalCommands(); +template size_t ExperimentalCommandBuffer::getExperimentalCommandsSize() noexcept; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/hw_cmds.h b/shared/source/xe_hpc_core/hw_cmds.h new file mode 100644 index 0000000000..413c6207a4 --- /dev/null +++ b/shared/source/xe_hpc_core/hw_cmds.h @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#ifdef SUPPORT_PVC +#include "hw_cmds_pvc.h" +#endif diff --git a/shared/source/xe_hpc_core/hw_cmds_base.h b/shared/source/xe_hpc_core/hw_cmds_base.h new file mode 100644 index 0000000000..a28539692b --- /dev/null +++ b/shared/source/xe_hpc_core/hw_cmds_base.h @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include "shared/source/commands/bxml_generator_glue.h" +#include "shared/source/helpers/debug_helpers.h" +#include "shared/source/xe_hpc_core/hw_info.h" + +#include "igfxfmid.h" + +#include +#include + +template +struct CmdParse; +namespace NEO { + +struct XE_HPC_CORE { +#include "shared/source/generated/xe_hpc_core/hw_cmds_generated_xe_hpc_core.inl" + + static constexpr uint32_t stateComputeModeForceNonCoherentMask = (0b11u << 3); + static constexpr uint32_t stateComputeModeEuThreadSchedulingModeOverrideMask = (0b11u << 13); + static constexpr uint32_t stateComputeModeLargeGrfModeMask = (1u << 15); + + static constexpr uint8_t pvcBaseDieRevMask = 0b111000; // [3:5] + static constexpr uint8_t pvcBaseDieA0Masked = 0; // [3:5] == 0 + static constexpr uint32_t pvcSteppingBits = 0b111; + static constexpr uint32_t pvcXlDeviceId = 0x0BD0; + static constexpr uint32_t pvcXtDeviceIds[5] = {0x0BD5, 0x0BD6, 0x0BD7, 0x0BD8, 0x0BE1}; + static constexpr uint32_t pvcXtTemporaryDeviceId = 0x0BE5; + + static constexpr bool isUsingL3Control = false; + + static bool isXlA0(const HardwareInfo &hwInfo) { + auto revId = hwInfo.platform.usRevId & pvcSteppingBits; + return (revId < 0x3) && !isXtTemporary(hwInfo); + } + + static bool isAtMostXtA0(const HardwareInfo &hwInfo) { + auto revId = hwInfo.platform.usRevId & pvcSteppingBits; + return (revId <= 0x3) && !isXtTemporary(hwInfo); + } + + static bool isXtTemporary(const HardwareInfo &hwInfo) { + return hwInfo.platform.usDeviceID == pvcXtTemporaryDeviceId; + } + + struct DataPortBindlessSurfaceExtendedMessageDescriptor { + union { + struct { + uint32_t bindlessSurfaceOffset : 25; + uint32_t reserved : 6; + }; + uint32_t packed; + }; + + DataPortBindlessSurfaceExtendedMessageDescriptor() { + packed = 0; + } + + void setBindlessSurfaceOffset(uint32_t offsetInBindlessSurfaceHeapInBytes) { + bindlessSurfaceOffset = offsetInBindlessSurfaceHeapInBytes >> 6; + } + + uint32_t getBindlessSurfaceOffsetToPatch() { + return bindlessSurfaceOffset << 6; + } + }; + + static_assert(sizeof(DataPortBindlessSurfaceExtendedMessageDescriptor) == sizeof(DataPortBindlessSurfaceExtendedMessageDescriptor::packed), ""); +}; + +struct XE_HPC_COREFamily : public XE_HPC_CORE { + using PARSE = CmdParse; + using GfxFamily = XE_HPC_COREFamily; + using WALKER_TYPE = COMPUTE_WALKER; + using VFE_STATE_TYPE = CFE_STATE; + using XY_COPY_BLT = typename GfxFamily::MEM_COPY; + using XY_COLOR_BLT = typename GfxFamily::XY_FAST_COLOR_BLT; + using MI_STORE_REGISTER_MEM_CMD = typename GfxFamily::MI_STORE_REGISTER_MEM; + using TimestampPacketType = uint32_t; + static const COMPUTE_WALKER cmdInitGpgpuWalker; + static const CFE_STATE cmdInitCfeState; + static const INTERFACE_DESCRIPTOR_DATA cmdInitInterfaceDescriptorData; + static const MI_BATCH_BUFFER_END cmdInitBatchBufferEnd; + static const MI_BATCH_BUFFER_START cmdInitBatchBufferStart; + static const PIPE_CONTROL cmdInitPipeControl; + static const STATE_COMPUTE_MODE cmdInitStateComputeMode; + static const _3DSTATE_BINDING_TABLE_POOL_ALLOC cmdInitStateBindingTablePoolAlloc; + static const MI_SEMAPHORE_WAIT cmdInitMiSemaphoreWait; + static const RENDER_SURFACE_STATE cmdInitRenderSurfaceState; + static const POSTSYNC_DATA cmdInitPostSyncData; + static const MI_SET_PREDICATE cmdInitSetPredicate; + static const MI_LOAD_REGISTER_IMM cmdInitLoadRegisterImm; + static const MI_LOAD_REGISTER_REG cmdInitLoadRegisterReg; + static const MI_LOAD_REGISTER_MEM cmdInitLoadRegisterMem; + static const MI_STORE_DATA_IMM cmdInitStoreDataImm; + static const MI_STORE_REGISTER_MEM cmdInitStoreRegisterMem; + static const MI_NOOP cmdInitNoop; + static const MI_REPORT_PERF_COUNT cmdInitReportPerfCount; + static const MI_ATOMIC cmdInitAtomic; + static const PIPELINE_SELECT cmdInitPipelineSelect; + static const MI_ARB_CHECK cmdInitArbCheck; + static const STATE_BASE_ADDRESS cmdInitStateBaseAddress; + static const MEDIA_SURFACE_STATE cmdInitMediaSurfaceState; + static const SAMPLER_STATE cmdInitSamplerState; + static const BINDING_TABLE_STATE cmdInitBindingTableState; + static const MI_USER_INTERRUPT cmdInitUserInterrupt; + static const MI_CONDITIONAL_BATCH_BUFFER_END cmdInitConditionalBatchBufferEnd; + static const MI_FLUSH_DW cmdInitMiFlushDw; + static const MEM_COPY cmdInitXyCopyBlt; + static const XY_FAST_COLOR_BLT cmdInitXyColorBlt; + static const STATE_PREFETCH cmdInitStatePrefetch; + static const _3DSTATE_BTD cmd3dStateBtd; + static const _3DSTATE_BTD_BODY cmd3dStateBtdBody; + static const MI_MEM_FENCE cmdInitMemFence; + static const MEM_SET cmdInitMemSet; + static const STATE_SIP cmdInitStateSip; + static const STATE_SYSTEM_MEM_FENCE_ADDRESS cmdInitStateSystemMemFenceAddress; + + static constexpr bool supportsCmdSet(GFXCORE_FAMILY cmdSetBaseFamily) { + return cmdSetBaseFamily == IGFX_XE_HP_CORE; + } +}; + +} // namespace NEO diff --git a/shared/source/xe_hpc_core/hw_cmds_pvc.h b/shared/source/xe_hpc_core/hw_cmds_pvc.h new file mode 100644 index 0000000000..d61bc1bb70 --- /dev/null +++ b/shared/source/xe_hpc_core/hw_cmds_pvc.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include "shared/source/xe_hpc_core/hw_cmds_base.h" +namespace NEO { + +struct PVC : public XE_HPC_COREFamily { + static const PLATFORM platform; + static const HardwareInfo hwInfo; + static const uint64_t defaultHardwareInfoConfig; + static FeatureTable featureTable; + static WorkaroundTable workaroundTable; + // Initial non-zero values for unit tests + static const uint32_t threadsPerEu = 8; + static const uint32_t maxEuPerSubslice = 8; + static const uint32_t maxSlicesSupported = 8; + static const uint32_t maxSubslicesSupported = 64; + static const uint32_t maxDualSubslicesSupported = 64; + static const RuntimeCapabilityTable capabilityTable; + static void (*setupHardwareInfo)(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig); + static void setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo); + static void setupHardwareInfoBase(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, bool setupMultiTile); + static void adjustHardwareInfo(HardwareInfo *hwInfo); +}; + +class PVC_CONFIG : public PVC { + public: + static void setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable); + static void setupHardwareInfoMultiTile(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, bool setupMultiTile); + static const HardwareInfo hwInfo; + + private: + static GT_SYSTEM_INFO gtSystemInfo; +}; + +#include "hw_cmds_pvc.inl" +} // namespace NEO diff --git a/shared/source/xe_hpc_core/hw_helper_xe_hpc_core.cpp b/shared/source/xe_hpc_core/hw_helper_xe_hpc_core.cpp new file mode 100644 index 0000000000..1534f63385 --- /dev/null +++ b/shared/source/xe_hpc_core/hw_helper_xe_hpc_core.cpp @@ -0,0 +1,434 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/xe_hpc_core/aub_mapper.h" +#include "shared/source/xe_hpc_core/hw_cmds.h" + +using Family = NEO::XE_HPC_COREFamily; + +#include "shared/source/command_container/command_encoder.h" +#include "shared/source/debug_settings/debug_settings_manager.h" +#include "shared/source/helpers/flat_batch_buffer_helper_hw.inl" +#include "shared/source/helpers/hw_helper_base.inl" +#include "shared/source/helpers/hw_helper_dg2_and_later.inl" +#include "shared/source/helpers/hw_helper_tgllp_and_later.inl" +#include "shared/source/helpers/hw_helper_xehp_and_later.inl" + +namespace NEO { + +template <> +const AuxTranslationMode HwHelperHw::defaultAuxTranslationMode = AuxTranslationMode::Blit; + +template <> +bool HwHelperHw::isCooperativeEngineSupported(const HardwareInfo &hwInfo) const { + return (HwInfoConfig::get(hwInfo.platform.eProductFamily)->getSteppingFromHwRevId(hwInfo) >= REVISION_B); +} + +template <> +const EngineInstancesContainer HwHelperHw::getGpgpuEngineInstances(const HardwareInfo &hwInfo) const { + auto defaultEngine = getChosenEngineType(hwInfo); + + EngineInstancesContainer engines; + + if (hwInfo.featureTable.flags.ftrCCSNode) { + for (uint32_t i = 0; i < hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled; i++) { + engines.push_back({static_cast(i + aub_stream::ENGINE_CCS), EngineUsage::Regular}); + if (isCooperativeEngineSupported(hwInfo)) { + engines.push_back({static_cast(i + aub_stream::ENGINE_CCS), EngineUsage::Cooperative}); + } + } + } + + if ((DebugManager.flags.NodeOrdinal.get() == static_cast(aub_stream::EngineType::ENGINE_CCCS)) || + hwInfo.featureTable.flags.ftrRcsNode) { + engines.push_back({aub_stream::ENGINE_CCCS, EngineUsage::Regular}); + } + + engines.push_back({defaultEngine, EngineUsage::LowPriority}); + engines.push_back({defaultEngine, EngineUsage::Internal}); + + if (hwInfo.capabilityTable.blitterOperationsSupported) { + if (hwInfo.featureTable.ftrBcsInfo.test(0)) { + engines.push_back({aub_stream::EngineType::ENGINE_BCS, EngineUsage::Regular}); // Main copy engine + engines.push_back({aub_stream::EngineType::ENGINE_BCS, EngineUsage::Internal}); // internal usage + } + + for (uint32_t i = 1; i < hwInfo.featureTable.ftrBcsInfo.size(); i++) { + if (hwInfo.featureTable.ftrBcsInfo.test(i)) { + auto engineType = static_cast((i - 1) + aub_stream::ENGINE_BCS1); // Link copy engine + engines.push_back({engineType, EngineUsage::Regular}); + } + } + } + + return engines; +}; + +template <> +EngineGroupType HwHelperHw::getEngineGroupType(aub_stream::EngineType engineType, EngineUsage engineUsage, const HardwareInfo &hwInfo) const { + if (engineType == aub_stream::ENGINE_CCCS) { + return EngineGroupType::RenderCompute; + } + if (engineType >= aub_stream::ENGINE_CCS && engineType < (aub_stream::ENGINE_CCS + hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled)) { + if (engineUsage == EngineUsage::Cooperative) { + return EngineGroupType::CooperativeCompute; + } + return EngineGroupType::Compute; + } + if (engineType == aub_stream::ENGINE_BCS) { + return EngineGroupType::Copy; + } + if (engineType >= aub_stream::ENGINE_BCS1 && engineType < aub_stream::ENGINE_BCS1 + hwInfo.featureTable.ftrBcsInfo.size() - 1) { + return EngineGroupType::LinkedCopy; + } + UNRECOVERABLE_IF(true); +} + +template <> +void HwHelperHw::adjustDefaultEngineType(HardwareInfo *pHwInfo) { + if (!pHwInfo->featureTable.flags.ftrCCSNode) { + pHwInfo->capabilityTable.defaultEngineType = aub_stream::EngineType::ENGINE_CCCS; + } +} + +template <> +bool HwHelperHw::tilingAllowed(bool isSharedContext, bool isImage1d, bool forceLinearStorage) { + return false; +} + +template <> +uint32_t HwHelperHw::getBarriersCountFromHasBarriers(uint32_t hasBarriers) { + static constexpr uint32_t possibleBarriersCounts[] = { + 0u, // 0 + 1u, // 1 + 2u, // 2 + 4u, // 3 + 8u, // 4 + 16u, // 5 + 24u, // 6 + 32u, // 7 + }; + return possibleBarriersCounts[hasBarriers]; +} + +template <> +uint32_t HwHelperHw::calculateAvailableThreadCount(PRODUCT_FAMILY family, uint32_t grfCount, uint32_t euCount, + uint32_t threadsPerEu) { + auto maxThreadsPerEuCount = 1024u / grfCount; + return maxThreadsPerEuCount * euCount; +} + +template <> +uint32_t HwHelperHw::getMetricsLibraryGenId() const { + return static_cast(MetricsLibraryApi::ClientGen::XeHPC); +} + +template <> +uint32_t HwHelperHw::getMinimalSIMDSize() { + return 16u; +} + +template <> +bool HwHelperHw::isFenceAllocationRequired(const HardwareInfo &hwInfo) const { + if ((DebugManager.flags.ProgramGlobalFenceAsMiMemFenceCommandInCommandStream.get() == 0) && + (DebugManager.flags.ProgramGlobalFenceAsPostSyncOperationInComputeWalker.get() == 0) && + (DebugManager.flags.ProgramGlobalFenceAsKernelInstructionInEUKernel.get() == 0)) { + return false; + } + return true; +} + +template <> +uint32_t HwHelperHw::getMocsIndex(const GmmHelper &gmmHelper, bool l3enabled, bool l1enabled) const { + if (l3enabled) { + return gmmHelper.getMOCS(GMM_RESOURCE_USAGE_OCL_BUFFER) >> 1; + } + return gmmHelper.getMOCS(GMM_RESOURCE_USAGE_OCL_BUFFER_CACHELINE_MISALIGNED) >> 1; +} + +template <> +const StackVec HwHelperHw::getDeviceSubGroupSizes() const { + return {16, 32}; +} + +template <> +const StackVec HwHelperHw::getThreadsPerEUConfigs() const { + return {4, 8}; +} + +template <> +uint32_t HwHelperHw::getMaxNumSamplers() const { + return 0; +} + +template <> +size_t HwHelperHw::getPaddingForISAAllocation() const { + return 3584; +} + +template <> +size_t MemorySynchronizationCommands::getSizeForSingleAdditionalSynchronization(const HardwareInfo &hwInfo) { + auto programGlobalFenceAsMiMemFenceCommandInCommandStream = !Family::isXlA0(hwInfo); + if (DebugManager.flags.ProgramGlobalFenceAsMiMemFenceCommandInCommandStream.get() != -1) { + programGlobalFenceAsMiMemFenceCommandInCommandStream = !!DebugManager.flags.ProgramGlobalFenceAsMiMemFenceCommandInCommandStream.get(); + } + + if (programGlobalFenceAsMiMemFenceCommandInCommandStream) { + return sizeof(Family::MI_MEM_FENCE); + } else { + return EncodeSempahore::getSizeMiSemaphoreWait(); + } +} + +template <> +void MemorySynchronizationCommands::setAdditionalSynchronization(void *&commandsBuffer, uint64_t gpuAddress, const HardwareInfo &hwInfo) { + using MI_MEM_FENCE = typename Family::MI_MEM_FENCE; + using MI_SEMAPHORE_WAIT = typename Family::MI_SEMAPHORE_WAIT; + auto programGlobalFenceAsMiMemFenceCommandInCommandStream = !Family::isXlA0(hwInfo); + if (DebugManager.flags.ProgramGlobalFenceAsMiMemFenceCommandInCommandStream.get() != -1) { + programGlobalFenceAsMiMemFenceCommandInCommandStream = !!DebugManager.flags.ProgramGlobalFenceAsMiMemFenceCommandInCommandStream.get(); + } + if (programGlobalFenceAsMiMemFenceCommandInCommandStream) { + MI_MEM_FENCE miMemFence = Family::cmdInitMemFence; + miMemFence.setFenceType(Family::MI_MEM_FENCE::FENCE_TYPE::FENCE_TYPE_RELEASE); + *reinterpret_cast(commandsBuffer) = miMemFence; + commandsBuffer = ptrOffset(commandsBuffer, sizeof(MI_MEM_FENCE)); + } else { + EncodeSempahore::programMiSemaphoreWait(reinterpret_cast(commandsBuffer), + gpuAddress, + EncodeSempahore::invalidHardwareTag, + MI_SEMAPHORE_WAIT::COMPARE_OPERATION::COMPARE_OPERATION_SAD_NOT_EQUAL_SDD, + false); + commandsBuffer = ptrOffset(commandsBuffer, EncodeSempahore::getSizeMiSemaphoreWait()); + } +} + +template <> +bool MemorySynchronizationCommands::isPipeControlWArequired(const HardwareInfo &hwInfo) { + if (DebugManager.flags.DisablePipeControlPrecedingPostSyncCommand.get() == 1) { + return true; + } + return false; +} + +template <> +bool MemorySynchronizationCommands::isDcFlushAllowed() { + return false; +} + +template <> +size_t MemorySynchronizationCommands::getSizeForAdditonalSynchronization(const HardwareInfo &hwInfo) { + return (DebugManager.flags.DisablePipeControlPrecedingPostSyncCommand.get() == 1 ? 2 : 1) * getSizeForSingleAdditionalSynchronization(hwInfo); +} + +template <> +void HwHelperHw::setL1CachePolicy(bool useL1Cache, typename Family::RENDER_SURFACE_STATE *surfaceState, const HardwareInfo *hwInfo) { + if (useL1Cache) { + surfaceState->setL1CachePolicyL1CacheControl(Family::RENDER_SURFACE_STATE::L1_CACHE_POLICY_WB); + if (DebugManager.flags.OverrideL1CacheControlInSurfaceStateForScratchSpace.get() != -1) { + surfaceState->setL1CachePolicyL1CacheControl(static_cast(DebugManager.flags.OverrideL1CacheControlInSurfaceStateForScratchSpace.get())); + } + } +} + +template <> +void HwHelperHw::setExtraAllocationData(AllocationData &allocationData, const AllocationProperties &properties, const HardwareInfo &hwInfo) const { + if (properties.allocationType == GraphicsAllocation::AllocationType::TIMESTAMP_PACKET_TAG_BUFFER || properties.allocationType == GraphicsAllocation::AllocationType::COMMAND_BUFFER) { + allocationData.flags.useSystemMemory = false; + } + if (properties.allocationType == GraphicsAllocation::AllocationType::COMMAND_BUFFER && properties.subDevicesBitfield.count() == 1) { + allocationData.flags.useSystemMemory = true; + } + allocationData.cacheRegion = properties.cacheRegion; + + if (allocationData.flags.requiresCpuAccess && !allocationData.flags.useSystemMemory && + (allocationData.storageInfo.getMemoryBanks() > 1)) { + + bool bdA0 = ((hwInfo.platform.usRevId & Family::pvcBaseDieRevMask) == Family::pvcBaseDieA0Masked); + bool applyWa = ((DebugManager.flags.ForceTile0PlacementForTile1ResourcesWaActive.get() == 1) || bdA0); + applyWa &= (DebugManager.flags.ForceTile0PlacementForTile1ResourcesWaActive.get() != 0); + + if (applyWa) { + allocationData.storageInfo.memoryBanks = 1; // force Tile0 + } + } +} + +template <> +uint32_t HwHelperHw::getNumCacheRegions() const { + if (DebugManager.flags.ClosEnabled.get() == 0) { + return 0; + } + + constexpr uint32_t numSharedCacheRegions = 1; + constexpr uint32_t numReservedCacheRegions = 2; + constexpr uint32_t numTotalCacheRegions = numSharedCacheRegions + numReservedCacheRegions; + return numTotalCacheRegions; +} + +template <> +std::string HwHelperHw::getExtensions() const { + std::string extensions; + + extensions += "cl_intel_create_buffer_with_properties "; + extensions += "cl_intel_dot_accumulate "; + extensions += "cl_intel_global_float_atomics "; + extensions += "cl_intel_subgroup_local_block_io "; + extensions += "cl_intel_subgroup_matrix_multiply_accumulate_for_PVC "; + extensions += "cl_khr_subgroup_named_barrier "; + extensions += "cl_intel_subgroup_extended_block_read "; + + return extensions; +} + +template <> +uint32_t HwHelperHw::alignSlmSize(uint32_t slmSize) { + const uint32_t alignedSlmSizes[] = { + 0u, + 1u * KB, + 2u * KB, + 4u * KB, + 8u * KB, + 16u * KB, + 24u * KB, + 32u * KB, + 48u * KB, + 64u * KB, + 96u * KB, + 128u * KB, + }; + + for (auto &alignedSlmSize : alignedSlmSizes) { + if (slmSize <= alignedSlmSize) { + return alignedSlmSize; + } + } + + UNRECOVERABLE_IF(true); + return 0; +} + +template <> +uint32_t HwHelperHw::computeSlmValues(const HardwareInfo &hwInfo, uint32_t slmSize) { + using SHARED_LOCAL_MEMORY_SIZE = typename Family::INTERFACE_DESCRIPTOR_DATA::SHARED_LOCAL_MEMORY_SIZE; + if (slmSize == 0u) { + return SHARED_LOCAL_MEMORY_SIZE::SHARED_LOCAL_MEMORY_SIZE_ENCODES_0K; + } + + UNRECOVERABLE_IF(slmSize > 128u * KB); + + if (slmSize > 96u * KB) { + return SHARED_LOCAL_MEMORY_SIZE::SHARED_LOCAL_MEMORY_SIZE_ENCODES_128K; + } + if (slmSize > 64u * KB) { + return SHARED_LOCAL_MEMORY_SIZE::SHARED_LOCAL_MEMORY_SIZE_ENCODES_96K; + } + if (slmSize > 48u * KB) { + return SHARED_LOCAL_MEMORY_SIZE::SHARED_LOCAL_MEMORY_SIZE_ENCODES_64K; + } + if (slmSize > 32u * KB) { + return SHARED_LOCAL_MEMORY_SIZE::SHARED_LOCAL_MEMORY_SIZE_ENCODES_48K; + } + if (slmSize > 24u * KB) { + return SHARED_LOCAL_MEMORY_SIZE::SHARED_LOCAL_MEMORY_SIZE_ENCODES_32K; + } + if (slmSize > 16u * KB) { + return SHARED_LOCAL_MEMORY_SIZE::SHARED_LOCAL_MEMORY_SIZE_ENCODES_24K; + } + if (slmSize > 8u * KB) { + return SHARED_LOCAL_MEMORY_SIZE::SHARED_LOCAL_MEMORY_SIZE_ENCODES_16K; + } + if (slmSize > 4u * KB) { + return SHARED_LOCAL_MEMORY_SIZE::SHARED_LOCAL_MEMORY_SIZE_ENCODES_8K; + } + if (slmSize > 2u * KB) { + return SHARED_LOCAL_MEMORY_SIZE::SHARED_LOCAL_MEMORY_SIZE_ENCODES_4K; + } + if (slmSize > 1u * KB) { + return SHARED_LOCAL_MEMORY_SIZE::SHARED_LOCAL_MEMORY_SIZE_ENCODES_2K; + } + return SHARED_LOCAL_MEMORY_SIZE::SHARED_LOCAL_MEMORY_SIZE_ENCODES_1K; +} + +template <> +uint32_t HwHelperHw::getDefaultThreadArbitrationPolicy() const { + return ThreadArbitrationPolicy::RoundRobin; +} + +template <> +bool HwHelperHw::isCopyOnlyEngineType(EngineGroupType type) const { + return (EngineGroupType::Copy == type || EngineGroupType::LinkedCopy == type); +} + +template <> +bool HwHelperHw::isSubDeviceEngineSupported(const HardwareInfo &hwInfo, const DeviceBitfield &deviceBitfield, aub_stream::EngineType engineType) const { + constexpr uint64_t tile1Bitfield = 0b10; + + bool isBaseDieA0 = (hwInfo.platform.usRevId & Family::pvcBaseDieRevMask) == Family::pvcBaseDieA0Masked; + bool affectedEngine = (deviceBitfield.to_ulong() == tile1Bitfield) && + (aub_stream::ENGINE_BCS == engineType || + aub_stream::ENGINE_BCS1 == engineType || + aub_stream::ENGINE_BCS3 == engineType); + + if (affectedEngine) { + if (DebugManager.flags.DoNotReportTile1BscWaActive.get() != -1) { + return !DebugManager.flags.DoNotReportTile1BscWaActive.get(); + } + + return !isBaseDieA0; + } + + return true; +} + +template <> +inline bool HwHelperHw::isBlitCopyRequiredForLocalMemory(const HardwareInfo &hwInfo, const GraphicsAllocation &allocation) const { + if (!allocation.isAllocatedInLocalMemoryPool()) { + return false; + } + + if (HwInfoConfig::get(hwInfo.platform.eProductFamily)->getLocalMemoryAccessMode(hwInfo) == LocalMemoryAccessMode::CpuAccessDisallowed) { + // Regular L3 WA + return true; + } + + if (!allocation.isAllocationLockable()) { + return true; + } + + bool isBaseDieA0 = (hwInfo.platform.usRevId & Family::pvcBaseDieRevMask) == Family::pvcBaseDieA0Masked; + bool isOtherTileThan0Accessed = allocation.storageInfo.memoryBanks.to_ulong() > 1u; + if (isBaseDieA0 && isOtherTileThan0Accessed) { + // Tile1 CPU access + return true; + } + + return false; +} + +template <> +uint32_t HwHelperHw::getComputeUnitsUsedForScratch(const HardwareInfo *pHwInfo) const { + if (DebugManager.flags.OverrideNumComputeUnitsForScratch.get() != -1) { + return static_cast(DebugManager.flags.OverrideNumComputeUnitsForScratch.get()); + } + + auto revId = pHwInfo->platform.usRevId & Family::pvcSteppingBits; + uint32_t threadEuRatio = ((0x3 <= revId) && (revId <= 0x6) && !Family::isXtTemporary(*pHwInfo)) ? 16 : 8; + + return pHwInfo->gtSystemInfo.MaxSubSlicesSupported * pHwInfo->gtSystemInfo.MaxEuPerSubSlice * threadEuRatio; +} + +} // namespace NEO + +#include "shared/source/helpers/hw_helper_pvc_and_later.inl" + +namespace NEO { +template class HwHelperHw; +template class FlatBatchBufferHelperHw; +template struct MemorySynchronizationCommands; +template struct LriHelper; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/hw_info.h b/shared/source/xe_hpc_core/hw_info.h new file mode 100644 index 0000000000..0aaa470592 --- /dev/null +++ b/shared/source/xe_hpc_core/hw_info.h @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#ifdef SUPPORT_PVC +#include "hw_info_pvc.h" +#endif diff --git a/shared/source/xe_hpc_core/hw_info_pvc.cpp b/shared/source/xe_hpc_core/hw_info_pvc.cpp new file mode 100644 index 0000000000..f4e59d1aa2 --- /dev/null +++ b/shared/source/xe_hpc_core/hw_info_pvc.cpp @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/aub_mem_dump/definitions/aub_services.h" +#include "shared/source/debug_settings/debug_settings_manager.h" +#include "shared/source/helpers/constants.h" +#include "shared/source/unified_memory/usm_memory_support.h" +#include "shared/source/xe_hpc_core/hw_cmds.h" + +#include "engine_node.h" + +namespace NEO { + +const char *HwMapper::abbreviation = "pvc"; + +bool isSimulationPVC(unsigned short deviceId) { + return false; +}; + +const PLATFORM PVC::platform = { + IGFX_PVC, + PCH_UNKNOWN, + IGFX_XE_HPC_CORE, + IGFX_XE_HPC_CORE, + PLATFORM_NONE, // default init + 0, // usDeviceID + 0, // usRevId. 0 sets the stepping to A0 + 0, // usDeviceID_PCH + 0, // usRevId_PCH + GTTYPE_UNDEFINED}; + +const RuntimeCapabilityTable PVC::capabilityTable{ + EngineDirectSubmissionInitVec{ + {aub_stream::ENGINE_CCS, {true, false, false, true}}, + {aub_stream::ENGINE_CCS1, {true, false, true, true}}, + {aub_stream::ENGINE_CCS2, {true, false, true, true}}, + {aub_stream::ENGINE_CCS3, {true, false, true, true}}, + {aub_stream::ENGINE_BCS1, {true, false, true, true}}, + {aub_stream::ENGINE_BCS2, {true, false, true, true}}, + {aub_stream::ENGINE_BCS3, {true, false, true, true}}, + {aub_stream::ENGINE_BCS4, {true, false, true, true}}, + {aub_stream::ENGINE_BCS5, {true, false, true, true}}, + {aub_stream::ENGINE_BCS6, {true, false, true, true}}, + {aub_stream::ENGINE_BCS7, {true, false, true, true}}, + {aub_stream::ENGINE_BCS8, {true, false, true, true}}}, // directSubmissionEngines + {0, 0, 0, false, false, false}, // kmdNotifyProperties + maxNBitValue(57), // gpuAddressSpace + 0, // sharedSystemMemCapabilities + 83.333, // defaultProfilingTimerResolution + MemoryConstants::pageSize, // requiredPreemptionSurfaceSize + &isSimulationPVC, // isSimulation + PreemptionMode::ThreadGroup, // defaultPreemptionMode + aub_stream::ENGINE_CCS, // defaultEngineType + 0, // maxRenderFrequency + 30, // clVersionSupport + CmdServicesMemTraceVersion::DeviceValues::Pvc, // aubDeviceId + 0, // extraQuantityThreadsPerEU + 128, // slmSize + sizeof(PVC::GRF), // grfSize + 36u, // timestampValidBits + 32u, // kernelTimestampValidBits + false, // blitterOperationsSupported + true, // ftrSupportsInteger64BitAtomics + true, // ftrSupportsFP64 + true, // ftrSupports64BitMath + true, // ftrSvm + false, // ftrSupportsCoherency + false, // ftrSupportsVmeAvcTextureSampler + false, // ftrSupportsVmeAvcPreemption + false, // ftrRenderCompressedBuffers + false, // ftrRenderCompressedImages + true, // ftr64KBpages + true, // instrumentationEnabled + "core", // platformType + "", // deviceName + false, // sourceLevelDebuggerSupported + false, // supportsVme + false, // supportCacheFlushAfterWalker + false, // supportsImages + false, // supportsDeviceEnqueue + false, // supportsPipes + true, // supportsOcl21Features + true, // supportsOnDemandPageFaults + true, // supportsIndependentForwardProgress + false, // hostPtrTrackingEnabled + true, // levelZeroSupported + false, // isIntegratedDevice + false, // supportsMediaBlock + false // fusedEuEnabled +}; + +void PVC::setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo) { + FeatureTable *featureTable = &hwInfo->featureTable; + WorkaroundTable *workaroundTable = &hwInfo->workaroundTable; + + featureTable->flags.ftrL3IACoherency = true; + featureTable->flags.ftrLocalMemory = true; + featureTable->flags.ftrLinearCCS = true; + featureTable->flags.ftrFlatPhysCCS = true; + featureTable->flags.ftrE2ECompression = false; + featureTable->flags.ftrCCSNode = true; + featureTable->flags.ftrCCSRing = true; + featureTable->flags.ftrMultiTileArch = true; + featureTable->flags.ftrCCSMultiInstance = true; + + featureTable->flags.ftrPPGTT = true; + featureTable->flags.ftrSVM = true; + featureTable->flags.ftrL3IACoherency = true; + featureTable->flags.ftrIA32eGfxPTEs = true; + featureTable->flags.ftrStandardMipTailFormat = true; + featureTable->flags.ftrTranslationTable = true; + featureTable->flags.ftrUserModeTranslationTable = true; + featureTable->flags.ftrTileMappedResource = true; + featureTable->flags.ftrEnableGuC = true; + featureTable->flags.ftrFbc = true; + featureTable->flags.ftrFbc2AddressTranslation = true; + featureTable->flags.ftrFbcBlitterTracking = true; + featureTable->flags.ftrAstcHdr2D = true; + featureTable->flags.ftrAstcLdr2D = true; + + featureTable->flags.ftr3dMidBatchPreempt = true; + featureTable->flags.ftrGpGpuMidBatchPreempt = true; + featureTable->flags.ftrGpGpuThreadGroupLevelPreempt = true; + featureTable->flags.ftrPerCtxtPreemptionGranularityControl = true; + + featureTable->flags.ftrTileY = false; + featureTable->ftrBcsInfo = maxNBitValue(9); + workaroundTable->flags.wa4kAlignUVOffsetNV12LinearSurface = true; + workaroundTable->flags.waEnablePreemptionGranularityControlByUMD = true; +} + +void PVC::adjustHardwareInfo(HardwareInfo *hwInfo) { + hwInfo->capabilityTable.sharedSystemMemCapabilities = (UNIFIED_SHARED_MEMORY_ACCESS | UNIFIED_SHARED_MEMORY_CONCURRENT_ACCESS | UNIFIED_SHARED_MEMORY_CONCURRENT_ATOMIC_ACCESS); +} +void PVC::setupHardwareInfoBase(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, bool setupMultiTile) { + GT_SYSTEM_INFO *gtSysInfo = &hwInfo->gtSystemInfo; + gtSysInfo->ThreadCount = gtSysInfo->EUCount * PVC::threadsPerEu; + gtSysInfo->MaxFillRate = 128; + gtSysInfo->TotalVsThreads = 336; + gtSysInfo->TotalHsThreads = 336; + gtSysInfo->TotalDsThreads = 336; + gtSysInfo->TotalGsThreads = 336; + gtSysInfo->TotalPsThreadsWindowerRange = 64; + gtSysInfo->CsrSizeInMb = 8; + gtSysInfo->MaxEuPerSubSlice = PVC::maxEuPerSubslice; + gtSysInfo->MaxSlicesSupported = PVC::maxSlicesSupported; + gtSysInfo->MaxSubSlicesSupported = PVC::maxSubslicesSupported; + gtSysInfo->MaxDualSubSlicesSupported = PVC::maxDualSubslicesSupported; + gtSysInfo->IsL3HashModeEnabled = false; + gtSysInfo->IsDynamicallyPopulated = false; + + gtSysInfo->MultiTileArchInfo.IsValid = setupMultiTile; + gtSysInfo->MultiTileArchInfo.TileCount = 1; + if (DebugManager.flags.CreateMultipleSubDevices.get() > 0) { + gtSysInfo->MultiTileArchInfo.TileCount = DebugManager.flags.CreateMultipleSubDevices.get(); + } + gtSysInfo->MultiTileArchInfo.TileMask = static_cast(maxNBitValue(gtSysInfo->MultiTileArchInfo.TileCount)); + + PVC::adjustHardwareInfo(hwInfo); +} + +FeatureTable PVC::featureTable; +WorkaroundTable PVC::workaroundTable; + +const HardwareInfo PVC_CONFIG::hwInfo = { + &PVC::platform, + &PVC::featureTable, + &PVC::workaroundTable, + &PVC_CONFIG::gtSystemInfo, + PVC::capabilityTable, +}; + +GT_SYSTEM_INFO PVC_CONFIG::gtSystemInfo = {0}; +void PVC_CONFIG::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable) { + PVC_CONFIG::setupHardwareInfoMultiTile(hwInfo, setupFeatureTableAndWorkaroundTable, false); +} +void PVC_CONFIG::setupHardwareInfoMultiTile(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, bool setupMultiTile) { + GT_SYSTEM_INFO *gtSysInfo = &hwInfo->gtSystemInfo; + gtSysInfo->CsrSizeInMb = 8; + gtSysInfo->IsL3HashModeEnabled = false; + gtSysInfo->IsDynamicallyPopulated = false; + + if (setupFeatureTableAndWorkaroundTable) { + PVC::setupFeatureAndWorkaroundTable(hwInfo); + } +}; + +#include "hw_info_setup_pvc.inl" +} // namespace NEO diff --git a/shared/source/xe_hpc_core/hw_info_pvc.h b/shared/source/xe_hpc_core/hw_info_pvc.h new file mode 100644 index 0000000000..369445bdde --- /dev/null +++ b/shared/source/xe_hpc_core/hw_info_pvc.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include "hw_info_xe_hpc_core.h" + +namespace NEO { + +struct PVC; + +template <> +struct HwMapper { + enum { gfxFamily = IGFX_XE_HPC_CORE }; + + static const char *abbreviation; + using GfxFamily = GfxFamilyMapper(gfxFamily)>::GfxFamily; + using GfxProduct = PVC; +}; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/hw_info_xe_hpc_core.cpp b/shared/source/xe_hpc_core/hw_info_xe_hpc_core.cpp new file mode 100644 index 0000000000..f92ed72f44 --- /dev/null +++ b/shared/source/xe_hpc_core/hw_info_xe_hpc_core.cpp @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/xe_hpc_core/hw_info_xe_hpc_core.h" + +namespace NEO { +const char *GfxFamilyMapper::name = "XE_HPC_CORE"; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/hw_info_xe_hpc_core.h b/shared/source/xe_hpc_core/hw_info_xe_hpc_core.h new file mode 100644 index 0000000000..4ba0549944 --- /dev/null +++ b/shared/source/xe_hpc_core/hw_info_xe_hpc_core.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once +#include "shared/source/helpers/hw_info.h" + +namespace NEO { + +struct XE_HPC_COREFamily; + +template <> +struct GfxFamilyMapper { + using GfxFamily = XE_HPC_COREFamily; + static const char *name; +}; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/image_core_xe_hpc_core.cpp b/shared/source/xe_hpc_core/image_core_xe_hpc_core.cpp new file mode 100644 index 0000000000..e7fdb47eea --- /dev/null +++ b/shared/source/xe_hpc_core/image_core_xe_hpc_core.cpp @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/image/image_surface_state.h" +#include "shared/source/xe_hpc_core/hw_cmds_base.h" + +namespace NEO { + +using Family = XE_HPC_COREFamily; + +// clang-format off +#include "shared/source/image/image_bdw_and_later.inl" +#include "shared/source/image/image_skl_and_later.inl" +// clang-format on +} // namespace NEO diff --git a/shared/source/xe_hpc_core/implicit_scaling_xe_hpc_core.cpp b/shared/source/xe_hpc_core/implicit_scaling_xe_hpc_core.cpp new file mode 100644 index 0000000000..eebd12a438 --- /dev/null +++ b/shared/source/xe_hpc_core/implicit_scaling_xe_hpc_core.cpp @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/command_container/implicit_scaling.h" +#include "shared/source/command_container/implicit_scaling_xehp_and_later.inl" + +namespace NEO { + +using Family = XE_HPC_COREFamily; + +template <> +bool ImplicitScalingDispatch::pipeControlStallRequired = true; + +template struct ImplicitScalingDispatch; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/linux/command_stream_receiver_xe_hpc_core.cpp b/shared/source/xe_hpc_core/linux/command_stream_receiver_xe_hpc_core.cpp new file mode 100644 index 0000000000..4064839261 --- /dev/null +++ b/shared/source/xe_hpc_core/linux/command_stream_receiver_xe_hpc_core.cpp @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/command_stream/command_stream_receiver_with_aub_dump.inl" +#include "shared/source/os_interface/linux/device_command_stream.inl" +#include "shared/source/os_interface/linux/drm_command_stream.inl" +#include "shared/source/os_interface/linux/drm_command_stream_xehp_and_later.inl" + +namespace NEO { + +template class DeviceCommandStreamReceiver; +template class DrmCommandStreamReceiver; +template class CommandStreamReceiverWithAUBDump>; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/linux/direct_submission_xe_hpc_core.cpp b/shared/source/xe_hpc_core/linux/direct_submission_xe_hpc_core.cpp new file mode 100644 index 0000000000..656dad21eb --- /dev/null +++ b/shared/source/xe_hpc_core/linux/direct_submission_xe_hpc_core.cpp @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/direct_submission/direct_submission_hw.inl" +#include "shared/source/direct_submission/direct_submission_prefetch_mitigation_xe_hp_core_and_later.inl" +#include "shared/source/direct_submission/direct_submission_prefetcher_pvc_and_later.inl" +#include "shared/source/direct_submission/direct_submission_xe_hp_core_and_later.inl" +#include "shared/source/direct_submission/dispatchers/blitter_dispatcher.inl" +#include "shared/source/direct_submission/dispatchers/dispatcher.inl" +#include "shared/source/direct_submission/dispatchers/render_dispatcher.inl" +#include "shared/source/direct_submission/linux/drm_direct_submission.inl" + +#include "hw_cmds.h" + +namespace NEO { +using GfxFamily = XE_HPC_COREFamily; + +template class Dispatcher; +template class BlitterDispatcher; +template class RenderDispatcher; + +template class DirectSubmissionHw>; +template class DirectSubmissionHw>; + +template class DrmDirectSubmission>; +template class DrmDirectSubmission>; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/linux/hw_info_config_pvc.cpp b/shared/source/xe_hpc_core/linux/hw_info_config_pvc.cpp new file mode 100644 index 0000000000..d7fdb759db --- /dev/null +++ b/shared/source/xe_hpc_core/linux/hw_info_config_pvc.cpp @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/helpers/constants.h" +#include "shared/source/helpers/hw_info.h" +#include "shared/source/kernel/kernel_properties.h" +#include "shared/source/os_interface/hw_info_config.h" +#include "shared/source/os_interface/hw_info_config.inl" +#include "shared/source/os_interface/hw_info_config_dg2_and_later.inl" +#include "shared/source/os_interface/hw_info_config_xehp_and_later.inl" + +namespace NEO { +constexpr static auto gfxProduct = IGFX_PVC; + +#include "shared/source/xe_hpc_core/os_agnostic_hw_info_config_pvc.inl" + +template <> +int HwInfoConfigHw::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) { + enableCompression(hwInfo); + + hwInfo->featureTable.embargoFlags.ftr57bGPUAddressing = (hwInfo->capabilityTable.gpuAddressSpace == maxNBitValue(57)); + + enableBlitterOperationsSupport(hwInfo); + + hwInfo->featureTable.flags.ftrRcsNode = false; + if (DebugManager.flags.NodeOrdinal.get() == static_cast(aub_stream::EngineType::ENGINE_CCCS)) { + hwInfo->featureTable.flags.ftrRcsNode = true; + } + + auto &kmdNotifyProperties = hwInfo->capabilityTable.kmdNotifyProperties; + kmdNotifyProperties.enableKmdNotify = true; + kmdNotifyProperties.delayKmdNotifyMicroseconds = 20; + + return 0; +} + +template class HwInfoConfigHw; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/os_agnostic_hw_info_config_pvc.inl b/shared/source/xe_hpc_core/os_agnostic_hw_info_config_pvc.inl new file mode 100644 index 0000000000..409ee8991d --- /dev/null +++ b/shared/source/xe_hpc_core/os_agnostic_hw_info_config_pvc.inl @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +template <> +void HwInfoConfigHw::getKernelExtendedProperties(uint32_t *fp16, uint32_t *fp32, uint32_t *fp64) { + *fp16 = (FP_ATOMIC_EXT_FLAG_GLOBAL_LOAD_STORE | FP_ATOMIC_EXT_FLAG_GLOBAL_ADD | FP_ATOMIC_EXT_FLAG_GLOBAL_MIN_MAX); + *fp32 = (FP_ATOMIC_EXT_FLAG_GLOBAL_LOAD_STORE | FP_ATOMIC_EXT_FLAG_GLOBAL_ADD | FP_ATOMIC_EXT_FLAG_GLOBAL_MIN_MAX); + *fp64 = (FP_ATOMIC_EXT_FLAG_GLOBAL_LOAD_STORE | FP_ATOMIC_EXT_FLAG_GLOBAL_ADD | FP_ATOMIC_EXT_FLAG_GLOBAL_MIN_MAX); +} + +template <> +bool HwInfoConfigHw::isMaxThreadsForWorkgroupWARequired(const HardwareInfo &hwInfo) const { + auto deviceId = hwInfo.platform.usDeviceID; + return XE_HPC_COREFamily::pvcXlDeviceId == deviceId; +} + +template <> +uint32_t HwInfoConfigHw::getHwRevIdFromStepping(uint32_t stepping, const HardwareInfo &hwInfo) const { + switch (hwInfo.platform.usDeviceID) { + default: + case XE_HPC_COREFamily::pvcXtTemporaryDeviceId: + case XE_HPC_COREFamily::pvcXlDeviceId: + switch (stepping) { + case REVISION_A0: + return 0x0; + case REVISION_B: + return 0x6; + case REVISION_C: + DEBUG_BREAK_IF(true); + return 0x7; + } + break; + case XE_HPC_COREFamily::pvcXtDeviceIds[0]: + case XE_HPC_COREFamily::pvcXtDeviceIds[1]: + case XE_HPC_COREFamily::pvcXtDeviceIds[2]: + switch (stepping) { + case REVISION_A0: + return 0x3; + case REVISION_B: + return 0x9D; + case REVISION_C: + return 0x7; + } + } + return CommonConstants::invalidStepping; +} + +template <> +uint32_t HwInfoConfigHw::getSteppingFromHwRevId(const HardwareInfo &hwInfo) const { + switch (hwInfo.platform.usRevId & XE_HPC_COREFamily::pvcSteppingBits) { + case 0x0: + case 0x1: + case 0x3: + return REVISION_A0; + case 0x5: + case 0x6: + return REVISION_B; + case 0x7: + return REVISION_C; + } + return CommonConstants::invalidStepping; +} + +template <> +void HwInfoConfigHw::adjustSamplerState(void *sampler, const HardwareInfo &hwInfo) { + using SAMPLER_STATE = typename XE_HPC_COREFamily::SAMPLER_STATE; + + auto samplerState = reinterpret_cast(sampler); + if (DebugManager.flags.ForceSamplerLowFilteringPrecision.get()) { + samplerState->setLowQualityFilter(SAMPLER_STATE::LOW_QUALITY_FILTER_ENABLE); + } +} + +template <> +uint32_t HwInfoConfigHw::getDeviceMemoryMaxClkRate(const HardwareInfo *hwInfo) { + bool isBaseDieA0 = (hwInfo->platform.usRevId & XE_HPC_COREFamily::pvcBaseDieRevMask) == XE_HPC_COREFamily::pvcBaseDieA0Masked; + if (isBaseDieA0) { + // For IGFX_PVC REV A0 HBM frequency would be 3.2 GT/s = 3.2 * 1000 MT/s = 3200 MT/s + return 3200u; + } + return 0u; +} + +template <> +bool HwInfoConfigHw::isDirectSubmissionSupported(const HardwareInfo &hwInfo) const { + return true; +} + +template <> +std::string HwInfoConfigHw::getDeviceMemoryName() const { + return "HBM"; +} + +template <> +bool HwInfoConfigHw::isDisableOverdispatchAvailable(const HardwareInfo &hwInfo) const { + return getSteppingFromHwRevId(hwInfo) >= REVISION_B; +} + +template <> +bool HwInfoConfigHw::isPipeControlPriorToNonPipelinedStateCommandsWARequired(const HardwareInfo &hwInfo, bool isRcs) const { + bool required = hwInfo.gtSystemInfo.CCSInfo.NumberOfCCSEnabled > 1; + + if (DebugManager.flags.ProgramPipeControlPriorToNonPipelinedStateCommand.get() != -1) { + required = DebugManager.flags.ProgramPipeControlPriorToNonPipelinedStateCommand.get(); + } + + return required; +} diff --git a/shared/source/xe_hpc_core/preamble_xe_hpc_core.cpp b/shared/source/xe_hpc_core/preamble_xe_hpc_core.cpp new file mode 100644 index 0000000000..c824ed8bc6 --- /dev/null +++ b/shared/source/xe_hpc_core/preamble_xe_hpc_core.cpp @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2020-2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +namespace NEO { +struct XE_HPC_COREFamily; +using Family = XE_HPC_COREFamily; +} // namespace NEO + +#include "shared/source/command_stream/stream_properties.h" +#include "shared/source/helpers/preamble_xehp_and_later.inl" +#include "shared/source/os_interface/hw_info_config.h" + +namespace NEO { + +using CFE_STATE = typename Family::CFE_STATE; +template <> +void PreambleHelper::appendProgramVFEState(const HardwareInfo &hwInfo, const StreamProperties &streamProperties, void *cmd) { + auto command = static_cast(cmd); + + command->setComputeOverdispatchDisable(streamProperties.frontEndState.disableOverdispatch.value == 1); + command->setSingleSliceDispatchCcsMode(streamProperties.frontEndState.singleSliceDispatchCcsMode.value == 1); + + if (HwInfoConfig::get(hwInfo.platform.eProductFamily)->getSteppingFromHwRevId(hwInfo) >= REVISION_B) { + if (streamProperties.frontEndState.computeDispatchAllWalkerEnable.value > 0) { + command->setComputeDispatchAllWalkerEnable(true); + command->setSingleSliceDispatchCcsMode(true); + } + } + + if (DebugManager.flags.CFEComputeDispatchAllWalkerEnable.get() != -1) { + command->setComputeDispatchAllWalkerEnable(DebugManager.flags.CFEComputeDispatchAllWalkerEnable.get()); + } + + if (DebugManager.flags.CFEComputeOverdispatchDisable.get() != -1) { + command->setComputeOverdispatchDisable(DebugManager.flags.CFEComputeOverdispatchDisable.get()); + } + if (DebugManager.flags.CFESingleSliceDispatchCCSMode.get() != -1) { + command->setSingleSliceDispatchCcsMode(DebugManager.flags.CFESingleSliceDispatchCCSMode.get()); + } + + command->setNumberOfWalkers(1); + if (DebugManager.flags.CFENumberOfWalkers.get() != -1) { + command->setNumberOfWalkers(DebugManager.flags.CFENumberOfWalkers.get()); + } +} + +template <> +bool PreambleHelper::isSystolicModeConfigurable(const HardwareInfo &hwInfo) { + return Family::isAtMostXtA0(hwInfo); +} + +template <> +bool PreambleHelper::isSpecialPipelineSelectModeChanged(bool lastSpecialPipelineSelectMode, bool newSpecialPipelineSelectMode, + const HardwareInfo &hwInfo) { + return (lastSpecialPipelineSelectMode != newSpecialPipelineSelectMode) && Family::isAtMostXtA0(hwInfo); +} + +template struct PreambleHelper; + +} // namespace NEO diff --git a/shared/source/xe_hpc_core/preemption_xe_hpc_core.cpp b/shared/source/xe_hpc_core/preemption_xe_hpc_core.cpp new file mode 100644 index 0000000000..9674df7ccb --- /dev/null +++ b/shared/source/xe_hpc_core/preemption_xe_hpc_core.cpp @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2020-2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/command_stream/preemption.h" +#include "shared/source/command_stream/preemption.inl" + +namespace NEO { + +using GfxFamily = XE_HPC_COREFamily; + +#include "shared/source/command_stream/preemption_xehp_and_later.inl" + +template void PreemptionHelper::programCmdStream(LinearStream &cmdStream, PreemptionMode newPreemptionMode, + PreemptionMode oldPreemptionMode, GraphicsAllocation *preemptionCsr); +template size_t PreemptionHelper::getRequiredCmdStreamSize(PreemptionMode newPreemptionMode, PreemptionMode oldPreemptionMode); +template size_t PreemptionHelper::getPreemptionWaCsSize(const Device &device); +template void PreemptionHelper::applyPreemptionWaCmdsBegin(LinearStream *pCommandStream, const Device &device); +template void PreemptionHelper::applyPreemptionWaCmdsEnd(LinearStream *pCommandStream, const Device &device); +template void PreemptionHelper::programInterfaceDescriptorDataPreemption(INTERFACE_DESCRIPTOR_DATA *idd, PreemptionMode preemptionMode); +} // namespace NEO diff --git a/shared/source/xe_hpc_core/state_base_address_xe_hpc_core.cpp b/shared/source/xe_hpc_core/state_base_address_xe_hpc_core.cpp new file mode 100644 index 0000000000..ee17714d05 --- /dev/null +++ b/shared/source/xe_hpc_core/state_base_address_xe_hpc_core.cpp @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2020-2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/helpers/state_base_address_xehp_and_later.inl" + +namespace NEO { +template <> +void StateBaseAddressHelper::appendExtraCacheSettings(STATE_BASE_ADDRESS *stateBaseAddress, GmmHelper *gmmHelper) { + stateBaseAddress->setL1CachePolicyL1CacheControl(STATE_BASE_ADDRESS::L1_CACHE_POLICY_WBP); + + if (DebugManager.flags.ForceStatelessL1CachingPolicy.get() != -1) { + stateBaseAddress->setL1CachePolicyL1CacheControl(static_cast(DebugManager.flags.ForceStatelessL1CachingPolicy.get())); + } +} + +template struct StateBaseAddressHelper; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/state_compute_mode_helper_xe_hpc_core.cpp b/shared/source/xe_hpc_core/state_compute_mode_helper_xe_hpc_core.cpp new file mode 100644 index 0000000000..67d07f557b --- /dev/null +++ b/shared/source/xe_hpc_core/state_compute_mode_helper_xe_hpc_core.cpp @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2020-2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/helpers/state_compute_mode_helper.h" + +namespace NEO { + +template <> +bool StateComputeModeHelper::isStateComputeModeRequired(const CsrSizeRequestFlags &csrSizeRequestFlags, bool isThreadArbitionPolicyProgrammed) { + return csrSizeRequestFlags.coherencyRequestChanged || csrSizeRequestFlags.numGrfRequiredChanged || isThreadArbitionPolicyProgrammed; +} + +} // namespace NEO diff --git a/shared/source/xe_hpc_core/tbx_command_stream_receiver_xe_hpc_core.cpp b/shared/source/xe_hpc_core/tbx_command_stream_receiver_xe_hpc_core.cpp new file mode 100644 index 0000000000..dd3366e5a6 --- /dev/null +++ b/shared/source/xe_hpc_core/tbx_command_stream_receiver_xe_hpc_core.cpp @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/command_stream/command_stream_receiver_with_aub_dump.inl" +#include "shared/source/command_stream/tbx_command_stream_receiver_hw.h" +#include "shared/source/command_stream/tbx_command_stream_receiver_hw.inl" +#include "shared/source/helpers/array_count.h" +#include "shared/source/helpers/populate_factory.h" +#include "shared/source/memory_manager/memory_banks.h" +#include "shared/source/memory_manager/memory_pool.h" +#include "shared/source/xe_hpc_core/hw_cmds.h" + +namespace NEO { +using Family = XE_HPC_COREFamily; +static auto gfxCore = IGFX_XE_HPC_CORE; + +template <> +void populateFactoryTable>() { + extern TbxCommandStreamReceiverCreateFunc tbxCommandStreamReceiverFactory[IGFX_MAX_CORE]; + UNRECOVERABLE_IF(!isInRange(gfxCore, tbxCommandStreamReceiverFactory)); + tbxCommandStreamReceiverFactory[gfxCore] = TbxCommandStreamReceiverHw::create; +} + +#include "shared/source/command_stream/tbx_command_stream_receiver_xehp_and_later.inl" + +template class TbxCommandStreamReceiverHw; +template class CommandStreamReceiverWithAUBDump>; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/windows/command_stream_receiver_xe_hpc_core.cpp b/shared/source/xe_hpc_core/windows/command_stream_receiver_xe_hpc_core.cpp new file mode 100644 index 0000000000..f94bcbd52a --- /dev/null +++ b/shared/source/xe_hpc_core/windows/command_stream_receiver_xe_hpc_core.cpp @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/command_stream/command_stream_receiver_with_aub_dump.inl" +#include "shared/source/os_interface/windows/device_command_stream.inl" +#include "shared/source/os_interface/windows/wddm_device_command_stream.inl" + +namespace NEO { + +template class DeviceCommandStreamReceiver; +template class WddmCommandStreamReceiver; +template class CommandStreamReceiverWithAUBDump>; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/windows/direct_submission_xe_hpc_core.cpp b/shared/source/xe_hpc_core/windows/direct_submission_xe_hpc_core.cpp new file mode 100644 index 0000000000..e0aa091aaa --- /dev/null +++ b/shared/source/xe_hpc_core/windows/direct_submission_xe_hpc_core.cpp @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/direct_submission/direct_submission_hw.inl" +#include "shared/source/direct_submission/direct_submission_prefetch_mitigation_xe_hp_core_and_later.inl" +#include "shared/source/direct_submission/direct_submission_prefetcher_pvc_and_later.inl" +#include "shared/source/direct_submission/direct_submission_xe_hp_core_and_later.inl" +#include "shared/source/direct_submission/dispatchers/blitter_dispatcher.inl" +#include "shared/source/direct_submission/dispatchers/dispatcher.inl" +#include "shared/source/direct_submission/dispatchers/render_dispatcher.inl" +#include "shared/source/direct_submission/windows/wddm_direct_submission.inl" + +#include "hw_cmds.h" + +namespace NEO { +using GfxFamily = XE_HPC_COREFamily; + +template class Dispatcher; +template class BlitterDispatcher; +template class RenderDispatcher; + +template class DirectSubmissionHw>; +template class DirectSubmissionHw>; + +template class WddmDirectSubmission>; +template class WddmDirectSubmission>; +} // namespace NEO diff --git a/shared/source/xe_hpc_core/windows/gmm_callbacks_xe_hpc_core.cpp b/shared/source/xe_hpc_core/windows/gmm_callbacks_xe_hpc_core.cpp new file mode 100644 index 0000000000..877ca89ede --- /dev/null +++ b/shared/source/xe_hpc_core/windows/gmm_callbacks_xe_hpc_core.cpp @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/helpers/windows/gmm_callbacks_tgllp_and_later.inl" +#include "shared/source/xe_hpc_core/hw_cmds.h" + +namespace NEO { + +template struct DeviceCallbacks; +template struct TTCallbacks; + +} // namespace NEO diff --git a/shared/source/xe_hpc_core/windows/hw_info_config_pvc.cpp b/shared/source/xe_hpc_core/windows/hw_info_config_pvc.cpp new file mode 100644 index 0000000000..c07c1897eb --- /dev/null +++ b/shared/source/xe_hpc_core/windows/hw_info_config_pvc.cpp @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2021 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#include "shared/source/kernel/kernel_properties.h" +#include "shared/source/os_interface/hw_info_config.h" +#include "shared/source/os_interface/hw_info_config.inl" +#include "shared/source/os_interface/hw_info_config_dg2_and_later.inl" +#include "shared/source/os_interface/hw_info_config_xehp_and_later.inl" + +#include "hw_cmds.h" + +namespace NEO { +constexpr static auto gfxProduct = IGFX_PVC; + +#include "shared/source/xe_hpc_core/os_agnostic_hw_info_config_pvc.inl" + +template <> +int HwInfoConfigHw::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) { + enableCompression(hwInfo); + enableBlitterOperationsSupport(hwInfo); + + hwInfo->featureTable.flags.ftrRcsNode = false; + if (DebugManager.flags.NodeOrdinal.get() == static_cast(aub_stream::EngineType::ENGINE_CCCS)) { + hwInfo->featureTable.flags.ftrRcsNode = true; + } + + return 0; +} + +template class HwInfoConfigHw; + +} // namespace NEO diff --git a/third_party/aub_stream/headers/engine_node.h b/third_party/aub_stream/headers/engine_node.h index 7eb9fb9677..a02148c039 100644 --- a/third_party/aub_stream/headers/engine_node.h +++ b/third_party/aub_stream/headers/engine_node.h @@ -19,6 +19,15 @@ enum EngineType : uint32_t { ENGINE_CCS1, ENGINE_CCS2, ENGINE_CCS3, + ENGINE_CCCS, + ENGINE_BCS1, + ENGINE_BCS2, + ENGINE_BCS3, + ENGINE_BCS4, + ENGINE_BCS5, + ENGINE_BCS6, + ENGINE_BCS7, + ENGINE_BCS8, NUM_ENGINES };