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performance: Limit tlb flush WA scope on DG2 Linux

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Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
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Lukasz Jobczyk
2023-12-21 09:58:49 +00:00
committed by Compute-Runtime-Automation
parent f7eb961435
commit fa181937a4
16 changed files with 81 additions and 15 deletions
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shared/source/os_interface/product_helper.h
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@@ -159,7 +159,7 @@ class ProductHelper {
virtual bool isResolveDependenciesByPipeControlsSupported(const HardwareInfo &hwInfo, bool isOOQ, TaskCountType queueTaskCount, const CommandStreamReceiver &queueCsr) const = 0;
virtual bool isMidThreadPreemptionDisallowedForRayTracingKernels() const = 0;
virtual bool isBufferPoolAllocatorSupported() const = 0;
virtual bool isTlbFlushRequired() const = 0;
virtual bool isTlbFlushRequired(const HardwareInfo &hwInfo, bool precondition, bool isDebuggerActive) const = 0;
virtual bool isDummyBlitWaRequired() const = 0;
virtual bool isDetectIndirectAccessInKernelSupported(const KernelDescriptor &kernelDescriptor, const bool isPrecompiled) const = 0;
virtual bool isLinearStoragePreferred(bool isImage1d, bool forceLinearStorage) const = 0;