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Change-Id: Id1a94577437a4826a32411869f516fec20314ec0
This commit is contained in:
kamdiedrich
2020-02-22 21:54:11 +01:00
parent 247cc953d1
commit fa8e720f9e
660 changed files with 3 additions and 3 deletions
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9
opencl/source/gen11/CMakeLists.txt Normal file
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#
# Copyright (C) 2019-2020 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
if(SUPPORT_GEN11)
add_subdirectories()
endif()

32
opencl/source/gen11/aub_command_stream_receiver_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/helpers/array_count.h"
#include "command_stream/aub_command_stream_receiver_hw.h"
#include "command_stream/aub_command_stream_receiver_hw_bdw_plus.inl"
#include "helpers/base_object.h"
namespace NEO {
typedef ICLFamily Family;
static auto gfxCore = IGFX_GEN11_CORE;
template <>
constexpr uint32_t AUBCommandStreamReceiverHw<Family>::getMaskAndValueForPollForCompletion() {
return 0x00008000;
}
template <>
void populateFactoryTable<AUBCommandStreamReceiverHw<Family>>() {
extern AubCommandStreamReceiverCreateFunc aubCommandStreamReceiverFactory[IGFX_MAX_CORE];
UNRECOVERABLE_IF(!isInRange(gfxCore, aubCommandStreamReceiverFactory));
aubCommandStreamReceiverFactory[gfxCore] = AUBCommandStreamReceiverHw<Family>::create;
}
template class AUBCommandStreamReceiverHw<Family>;
} // namespace NEO

30
opencl/source/gen11/aub_mapper.h Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "core/memory_manager/memory_constants.h"
#include "engine_node.h"
#include "gen_common/aub_mapper_base.h"
namespace NEO {
struct ICLFamily;
template <>
struct AUBFamilyMapper<ICLFamily> {
enum { device = AubMemDump::DeviceValues::Icllp };
using AubTraits = AubMemDump::Traits<device, MemoryConstants::GfxAddressBits>;
static const AubMemDump::LrcaHelper *const csTraits[aub_stream::NUM_ENGINES];
static const MMIOList globalMMIO;
static const MMIOList *perEngineMMIO[aub_stream::NUM_ENGINES];
typedef AubMemDump::AubDump<AubTraits> AUB;
};
} // namespace NEO

100
opencl/source/gen11/aub_mem_dump_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/helpers/completion_stamp.h"
#include "core/helpers/hw_helper.h"
#include "aub_mapper.h"
#include "aub_mem_dump/aub_alloc_dump.inl"
#include "aub_mem_dump/aub_mem_dump.inl"
#include "config.h"
namespace AubMemDump {
enum {
device = DeviceValues::Icllp
};
// Instantiate these common template implementations.
template struct AubDump<Traits<device, 32>>;
template struct AubDump<Traits<device, 48>>;
template struct AubPageTableHelper32<Traits<device, 32>>;
template struct AubPageTableHelper64<Traits<device, 48>>;
} // namespace AubMemDump
namespace NEO {
using Family = ICLFamily;
static const AubMemDump::LrcaHelperRcs rcs(0x002000);
static const AubMemDump::LrcaHelperBcs bcs(0x022000);
static const AubMemDump::LrcaHelperVcs vcs(0x1c0000);
static const AubMemDump::LrcaHelperVecs vecs(0x1c8000);
const AubMemDump::LrcaHelper *const AUBFamilyMapper<Family>::csTraits[aub_stream::NUM_ENGINES] = {
&rcs,
&bcs,
&vcs,
&vecs};
const MMIOList AUBFamilyMapper<Family>::globalMMIO;
static const MMIOList mmioListRCS = {
MMIOPair(0x000020d8, 0x00020000),
MMIOPair(AubMemDump::computeRegisterOffset(rcs.mmioBase, 0x229c), 0xffff8280),
MMIOPair(0x0000C800, 0x00000009),
MMIOPair(0x0000C804, 0x00000038),
MMIOPair(0x0000C808, 0x0000003B),
MMIOPair(0x0000C80C, 0x00000039),
MMIOPair(0x0000C810, 0x00000037),
MMIOPair(0x0000C814, 0x00000039),
MMIOPair(0x0000C818, 0x00000037),
MMIOPair(0x0000C81C, 0x0000001B),
MMIOPair(0x0000C820, 0x00060037),
MMIOPair(0x0000C824, 0x00000032),
MMIOPair(0x0000C828, 0x00000033),
MMIOPair(0x0000C82C, 0x0000003B),
MMIOPair(0x0000C8C0, 0x00000037),
MMIOPair(0x0000E18C, 0x00200020),
};
static const MMIOList mmioListBCS = {
MMIOPair(AubMemDump::computeRegisterOffset(bcs.mmioBase, 0x229c), 0xffff8280),
};
static const MMIOList mmioListVCS = {
MMIOPair(AubMemDump::computeRegisterOffset(vcs.mmioBase, 0x229c), 0xffff8280),
};
static const MMIOList mmioListVECS = {
MMIOPair(AubMemDump::computeRegisterOffset(vecs.mmioBase, 0x229c), 0xffff8280),
};
const MMIOList *AUBFamilyMapper<Family>::perEngineMMIO[aub_stream::NUM_ENGINES] = {
&mmioListRCS,
&mmioListBCS,
&mmioListVCS,
&mmioListVECS};
} // namespace NEO
namespace AubAllocDump {
using namespace NEO;
template SurfaceInfo *getDumpSurfaceInfo<Family>(GraphicsAllocation &gfxAllocation, DumpFormat dumpFormat);
template uint32_t getImageSurfaceTypeFromGmmResourceType<Family>(GMM_RESOURCE_TYPE gmmResourceType);
template void dumpBufferInBinFormat<Family>(GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context);
template void dumpImageInBmpFormat<Family>(GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context);
template void dumpBufferInTreFormat<Family>(GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context);
template void dumpImageInTreFormat<Family>(GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context);
template void dumpAllocation<Family>(DumpFormat dumpFormat, GraphicsAllocation &gfxAllocation, AubMemDump::AubFileStream *stream, uint32_t context);
} // namespace AubAllocDump

18
opencl/source/gen11/buffer_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/gen11/hw_cmds.h"
#include "mem_obj/buffer_bdw_plus.inl"
namespace NEO {
typedef ICLFamily Family;
static auto gfxCore = IGFX_GEN11_CORE;
#include "mem_obj/buffer_factory_init.inl"
} // namespace NEO

27
opencl/source/gen11/command_queue_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/memory_manager/unified_memory_manager.h"
#include "command_queue/command_queue_hw.h"
#include "command_queue/command_queue_hw_bdw_plus.inl"
#include "command_queue/enqueue_resource_barrier.h"
#include "enqueue_init_dispatch_globals.h"
namespace NEO {
typedef ICLFamily Family;
static auto gfxCore = IGFX_GEN11_CORE;
template class CommandQueueHw<Family>;
template <>
void populateFactoryTable<CommandQueueHw<Family>>() {
extern CommandQueueCreateFunc commandQueueFactory[IGFX_MAX_CORE];
commandQueueFactory[gfxCore] = CommandQueueHw<Family>::create;
}
} // namespace NEO

179
opencl/source/gen11/command_stream_receiver_hw_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/command_stream/command_stream_receiver_hw_bdw_plus.inl"
#include "core/debug_settings/debug_settings_manager.h"
#include "core/helpers/blit_commands_helper_bdw_plus.inl"
#include "command_stream/device_command_stream.h"
#include "gen11/reg_configs.h"
namespace NEO {
typedef ICLFamily Family;
static auto gfxCore = IGFX_GEN11_CORE;
template <>
size_t CommandStreamReceiverHw<Family>::getCmdSizeForComputeMode() {
if (csrSizeRequestFlags.coherencyRequestChanged) {
return sizeof(typename Family::MI_LOAD_REGISTER_IMM);
}
return 0;
}
template <>
void CommandStreamReceiverHw<Family>::programComputeMode(LinearStream &stream, DispatchFlags &dispatchFlags) {
if (csrSizeRequestFlags.coherencyRequestChanged) {
LriHelper<Family>::program(&stream, gen11HdcModeRegister::address,
DwordBuilder::build(gen11HdcModeRegister::forceNonCoherentEnableBit, true, !dispatchFlags.requiresCoherency));
this->lastSentCoherencyRequest = static_cast<int8_t>(dispatchFlags.requiresCoherency);
}
}
template <>
void CommandStreamReceiverHw<Family>::programMediaSampler(LinearStream &stream, DispatchFlags &dispatchFlags) {
using PWR_CLK_STATE_REGISTER = Family::PWR_CLK_STATE_REGISTER;
if (peekHwInfo().platform.eProductFamily == IGFX_ICELAKE_LP) {
if (dispatchFlags.pipelineSelectArgs.mediaSamplerRequired) {
if (!lastVmeSubslicesConfig) {
auto pc = addPipeControlCmd(stream);
pc->setDcFlushEnable(true);
pc->setRenderTargetCacheFlushEnable(true);
pc->setInstructionCacheInvalidateEnable(true);
pc->setTextureCacheInvalidationEnable(true);
pc->setPipeControlFlushEnable(true);
pc->setVfCacheInvalidationEnable(true);
pc->setConstantCacheInvalidationEnable(true);
pc->setStateCacheInvalidationEnable(true);
uint32_t numSubslices = peekHwInfo().gtSystemInfo.SubSliceCount;
uint32_t numSubslicesWithVme = numSubslices / 2; // 1 VME unit per DSS
uint32_t numSlicesForPowerGating = 1; // power gating supported only if #Slices = 1
PWR_CLK_STATE_REGISTER reg = Family::cmdInitPwrClkStateRegister;
reg.TheStructure.Common.EUmin = peekHwInfo().gtSystemInfo.MaxEuPerSubSlice;
reg.TheStructure.Common.EUmax = peekHwInfo().gtSystemInfo.MaxEuPerSubSlice;
reg.TheStructure.Common.SSCountEn = 1; // Enable SScount
reg.TheStructure.Common.SScount = numSubslicesWithVme;
reg.TheStructure.Common.EnableSliceCountRequest = 1; // Enable SliceCountRequest
reg.TheStructure.Common.SliceCountRequest = numSlicesForPowerGating;
LriHelper<Family>::program(&stream, PWR_CLK_STATE_REGISTER::REG_ADDRESS, reg.TheStructure.RawData[0]);
addPipeControlCmd(stream);
lastVmeSubslicesConfig = true;
}
} else {
if (lastVmeSubslicesConfig) {
auto pc = addPipeControlCmd(stream);
pc->setDcFlushEnable(true);
pc->setRenderTargetCacheFlushEnable(true);
pc->setInstructionCacheInvalidateEnable(true);
pc->setTextureCacheInvalidationEnable(true);
pc->setPipeControlFlushEnable(true);
pc->setVfCacheInvalidationEnable(true);
pc->setConstantCacheInvalidationEnable(true);
pc->setStateCacheInvalidationEnable(true);
pc->setGenericMediaStateClear(true);
addPipeControlCmd(stream);
// In Gen11-LP, software programs this register as if GT consists of
// 2 slices with 4 subslices in each slice. Hardware maps this to the
// LP 1 slice/8-subslice physical layout
uint32_t numSubslices = peekHwInfo().gtSystemInfo.SubSliceCount;
uint32_t numSubslicesMapped = numSubslices / 2;
uint32_t numSlicesMapped = peekHwInfo().gtSystemInfo.SliceCount * 2;
PWR_CLK_STATE_REGISTER reg = Family::cmdInitPwrClkStateRegister;
reg.TheStructure.Common.EUmin = peekHwInfo().gtSystemInfo.MaxEuPerSubSlice;
reg.TheStructure.Common.EUmax = peekHwInfo().gtSystemInfo.MaxEuPerSubSlice;
reg.TheStructure.Common.SSCountEn = 1; // Enable SScount
reg.TheStructure.Common.SScount = numSubslicesMapped;
reg.TheStructure.Common.EnableSliceCountRequest = 1; // Enable SliceCountRequest
reg.TheStructure.Common.SliceCountRequest = numSlicesMapped;
LriHelper<Family>::program(&stream, PWR_CLK_STATE_REGISTER::REG_ADDRESS, reg.TheStructure.RawData[0]);
addPipeControlCmd(stream);
}
}
}
}
template <>
bool CommandStreamReceiverHw<Family>::detectInitProgrammingFlagsRequired(const DispatchFlags &dispatchFlags) const {
bool flag = DebugManager.flags.ForceCsrReprogramming.get();
if (peekHwInfo().platform.eProductFamily == IGFX_ICELAKE_LP) {
if (!dispatchFlags.pipelineSelectArgs.mediaSamplerRequired) {
if (lastVmeSubslicesConfig) {
flag = true;
}
}
}
return flag;
}
template <>
size_t CommandStreamReceiverHw<Family>::getCmdSizeForMediaSampler(bool mediaSamplerRequired) const {
typedef typename Family::MI_LOAD_REGISTER_IMM MI_LOAD_REGISTER_IMM;
typedef typename Family::PIPE_CONTROL PIPE_CONTROL;
if (peekHwInfo().platform.eProductFamily == IGFX_ICELAKE_LP) {
if (mediaSamplerRequired) {
if (!lastVmeSubslicesConfig) {
return sizeof(MI_LOAD_REGISTER_IMM) + 2 * sizeof(PIPE_CONTROL);
}
} else {
if (lastVmeSubslicesConfig) {
return sizeof(MI_LOAD_REGISTER_IMM) + 3 * sizeof(PIPE_CONTROL);
}
}
}
return 0;
}
template <>
void populateFactoryTable<CommandStreamReceiverHw<Family>>() {
extern CommandStreamReceiverCreateFunc commandStreamReceiverFactory[IGFX_MAX_CORE];
commandStreamReceiverFactory[gfxCore] = DeviceCommandStreamReceiver<Family>::create;
}
template class CommandStreamReceiverHw<Family>;
template struct BlitCommandsHelper<Family>;
const Family::GPGPU_WALKER Family::cmdInitGpgpuWalker = Family::GPGPU_WALKER::sInit();
const Family::INTERFACE_DESCRIPTOR_DATA Family::cmdInitInterfaceDescriptorData = Family::INTERFACE_DESCRIPTOR_DATA::sInit();
const Family::MEDIA_INTERFACE_DESCRIPTOR_LOAD Family::cmdInitMediaInterfaceDescriptorLoad = Family::MEDIA_INTERFACE_DESCRIPTOR_LOAD::sInit();
const Family::MEDIA_STATE_FLUSH Family::cmdInitMediaStateFlush = Family::MEDIA_STATE_FLUSH::sInit();
const Family::MI_BATCH_BUFFER_START Family::cmdInitBatchBufferStart = Family::MI_BATCH_BUFFER_START::sInit();
const Family::MI_BATCH_BUFFER_END Family::cmdInitBatchBufferEnd = Family::MI_BATCH_BUFFER_END::sInit();
const Family::PIPE_CONTROL Family::cmdInitPipeControl = Family::PIPE_CONTROL::sInit();
const Family::MI_SEMAPHORE_WAIT Family::cmdInitMiSemaphoreWait = Family::MI_SEMAPHORE_WAIT::sInit();
const Family::RENDER_SURFACE_STATE Family::cmdInitRenderSurfaceState = Family::RENDER_SURFACE_STATE::sInit();
const Family::PWR_CLK_STATE_REGISTER Family::cmdInitPwrClkStateRegister = Family::PWR_CLK_STATE_REGISTER::sInit();
const Family::MI_LOAD_REGISTER_IMM Family::cmdInitLoadRegisterImm = Family::MI_LOAD_REGISTER_IMM::sInit();
const Family::MI_LOAD_REGISTER_REG Family::cmdInitLoadRegisterReg = Family::MI_LOAD_REGISTER_REG::sInit();
const Family::MI_LOAD_REGISTER_MEM Family::cmdInitLoadRegisterMem = Family::MI_LOAD_REGISTER_MEM::sInit();
const Family::MI_STORE_DATA_IMM Family::cmdInitStoreDataImm = Family::MI_STORE_DATA_IMM::sInit();
const Family::MI_STORE_REGISTER_MEM Family::cmdInitStoreRegisterMem = Family::MI_STORE_REGISTER_MEM::sInit();
const Family::MI_NOOP Family::cmdInitNoop = Family::MI_NOOP::sInit();
const Family::MI_REPORT_PERF_COUNT Family::cmdInitReportPerfCount = Family::MI_REPORT_PERF_COUNT::sInit();
const Family::MI_ATOMIC Family::cmdInitAtomic = Family::MI_ATOMIC::sInit();
const Family::PIPELINE_SELECT Family::cmdInitPipelineSelect = Family::PIPELINE_SELECT::sInit();
const Family::MI_ARB_CHECK Family::cmdInitArbCheck = Family::MI_ARB_CHECK::sInit();
const Family::MEDIA_VFE_STATE Family::cmdInitMediaVfeState = Family::MEDIA_VFE_STATE::sInit();
const Family::STATE_BASE_ADDRESS Family::cmdInitStateBaseAddress = Family::STATE_BASE_ADDRESS::sInit();
const Family::MEDIA_SURFACE_STATE Family::cmdInitMediaSurfaceState = Family::MEDIA_SURFACE_STATE::sInit();
const Family::SAMPLER_STATE Family::cmdInitSamplerState = Family::SAMPLER_STATE::sInit();
const Family::GPGPU_CSR_BASE_ADDRESS Family::cmdInitGpgpuCsrBaseAddress = Family::GPGPU_CSR_BASE_ADDRESS::sInit();
const Family::STATE_SIP Family::cmdInitStateSip = Family::STATE_SIP::sInit();
const Family::BINDING_TABLE_STATE Family::cmdInitBindingTableState = Family::BINDING_TABLE_STATE::sInit();
const Family::MI_USER_INTERRUPT Family::cmdInitUserInterrupt = Family::MI_USER_INTERRUPT::sInit();
const Family::XY_SRC_COPY_BLT Family::cmdInitXyCopyBlt = Family::XY_SRC_COPY_BLT::sInit();
const Family::MI_FLUSH_DW Family::cmdInitMiFlushDw = Family::MI_FLUSH_DW::sInit();
} // namespace NEO

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opencl/source/gen11/command_stream_receiver_simulated_common_hw_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "command_stream/command_stream_receiver_simulated_common_hw_bdw_plus.inl"
namespace NEO {
typedef ICLFamily Family;
template <>
void CommandStreamReceiverSimulatedCommonHw<Family>::submitLRCA(const MiContextDescriptorReg &contextDescriptor) {
auto mmioBase = getCsTraits(osContext->getEngineType()).mmioBase;
stream->writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x2510), contextDescriptor.ulData[0]);
stream->writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x2514), contextDescriptor.ulData[1]);
// Load our new exec list
stream->writeMMIO(AubMemDump::computeRegisterOffset(mmioBase, 0x2550), 1);
}
template class CommandStreamReceiverSimulatedCommonHw<Family>;
} // namespace NEO

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opencl/source/gen11/device_enqueue.h Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "../execution_model/device_enqueue.h"
// Uncomment this macro to build "empty" schedulers
//#define WA_DISABLE_SCHEDULERS 1
#define OCLRT_GPGPU_WALKER_CMD_DEVICE_CMD_G11 (15 * sizeof(uint))
#define OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G11 (6 * sizeof(uint))
#define OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G11_DWORD_OFFSET (6)
#define OCLRT_GPGPU_WALKER_CMD_DEVICE_CMD_G11_DWORD_OFFSET (15)
#define SLB_SPACE_FOR_EACH_ENQUEUE_UNALIGNED_GEN11 (OCLRT_SIZEOF_MEDIA_STATE_FLUSH + OCLRT_SIZEOF_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DEVICE_CMD + OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G11 + OCLRT_GPGPU_WALKER_CMD_DEVICE_CMD_G11 + OCLRT_SIZEOF_MEDIA_STATE_FLUSH + OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G11)
#define SLB_SIZE_ALIGNEMENT_WA_GEN11 52
#define SECOND_LEVEL_BUFFER_SPACE_FOR_EACH_ENQUEUE_GEN11 (SLB_SPACE_FOR_EACH_ENQUEUE_UNALIGNED_GEN11 + SLB_SIZE_ALIGNEMENT_WA_GEN11 + CS_PREFETCH_SIZE)
#define SECOND_LEVEL_BUFFER_NUMBER_OF_ENQUEUES_GEN11 (128)

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opencl/source/gen11/device_queue_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/gen11/hw_cmds.h"
#include "device_queue/device_queue_hw.h"
#include "device_queue/device_queue_hw_bdw_plus.inl"
#include "device_queue/device_queue_hw_profiling.inl"
#include "gen11/device_enqueue.h"
namespace NEO {
typedef ICLFamily Family;
static auto gfxCore = IGFX_GEN11_CORE;
template <>
void populateFactoryTable<DeviceQueueHw<Family>>() {
extern DeviceQueueCreateFunc deviceQueueFactory[IGFX_MAX_CORE];
deviceQueueFactory[gfxCore] = DeviceQueueHw<Family>::create;
}
static const size_t csPrefetchSizeAlignementWa = SLB_SIZE_ALIGNEMENT_WA_GEN11;
template <>
size_t DeviceQueueHw<Family>::getCSPrefetchSize() {
return 8 * MemoryConstants::cacheLineSize + csPrefetchSizeAlignementWa;
}
template <>
size_t DeviceQueueHw<Family>::getWaCommandsSize() { return 0; }
template <>
void DeviceQueueHw<Family>::addArbCheckCmdWa() {}
template <>
void DeviceQueueHw<Family>::addMiAtomicCmdWa(uint64_t atomicOpPlaceholder) {}
template <>
void DeviceQueueHw<Family>::addLriCmdWa(bool setArbCheck) {}
template <>
void DeviceQueueHw<Family>::addPipeControlCmdWa(bool isNoopCmd) {}
template class DeviceQueueHw<Family>;
} // namespace NEO

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opencl/source/gen11/enable_family_full_ocl_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/command_stream/command_stream_receiver_hw.h"
#include "command_queue/command_queue_hw.h"
#include "command_stream/aub_command_stream_receiver_hw.h"
#include "command_stream/tbx_command_stream_receiver_hw.h"
#include "device_queue/device_queue_hw.h"
#ifdef HAVE_INSTRUMENTATION
#include "event/perf_counter.h"
#endif
#include "mem_obj/buffer.h"
#include "mem_obj/image.h"
#include "sampler/sampler.h"
namespace NEO {
typedef ICLFamily Family;
struct EnableOCLGen11 {
EnableOCLGen11() {
populateFactoryTable<AUBCommandStreamReceiverHw<Family>>();
populateFactoryTable<TbxCommandStreamReceiverHw<Family>>();
populateFactoryTable<CommandQueueHw<Family>>();
populateFactoryTable<DeviceQueueHw<Family>>();
populateFactoryTable<CommandStreamReceiverHw<Family>>();
populateFactoryTable<BufferHw<Family>>();
populateFactoryTable<ImageHw<Family>>();
populateFactoryTable<SamplerHw<Family>>();
}
};
static EnableOCLGen11 enable;
} // namespace NEO

26
opencl/source/gen11/experimental_command_buffer_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/command_stream/experimental_command_buffer.h"
#include "core/command_stream/experimental_command_buffer.inl"
#include "core/helpers/hw_helper.h"
namespace NEO {
typedef ICLFamily GfxFamily;
template void ExperimentalCommandBuffer::injectBufferStart<GfxFamily>(LinearStream &parentStream, size_t cmdBufferOffset);
template size_t ExperimentalCommandBuffer::getRequiredInjectionSize<GfxFamily>() noexcept;
template size_t ExperimentalCommandBuffer::programExperimentalCommandBuffer<GfxFamily>();
template size_t ExperimentalCommandBuffer::getTotalExperimentalSize<GfxFamily>() noexcept;
template void ExperimentalCommandBuffer::addTimeStampPipeControl<GfxFamily>();
template size_t ExperimentalCommandBuffer::getTimeStampPipeControlSize<GfxFamily>() noexcept;
template void ExperimentalCommandBuffer::addExperimentalCommands<GfxFamily>();
template size_t ExperimentalCommandBuffer::getExperimentalCommandsSize<GfxFamily>() noexcept;
} // namespace NEO

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opencl/source/gen11/gpgpu_walker_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/gen11/hw_info.h"
#include "command_queue/gpgpu_walker_bdw_plus.inl"
#include "command_queue/hardware_interface_bdw_plus.inl"
namespace NEO {
template class HardwareInterface<ICLFamily>;
template class GpgpuWalkerHelper<ICLFamily>;
template struct EnqueueOperation<ICLFamily>;
} // namespace NEO

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opencl/source/gen11/gtpin_setup_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "gtpin/gtpin_hw_helper.h"
#include "gtpin/gtpin_hw_helper.inl"
#include "ocl_igc_shared/gtpin/gtpin_ocl_interface.h"
namespace NEO {
extern GTPinHwHelper *gtpinHwHelperFactory[IGFX_MAX_CORE];
typedef ICLFamily Family;
static const auto gfxFamily = IGFX_GEN11_CORE;
template <>
uint32_t GTPinHwHelperHw<Family>::getGenVersion() {
return gtpin::GTPIN_GEN_11;
}
template class GTPinHwHelperHw<Family>;
struct GTPinEnableGen11 {
GTPinEnableGen11() {
gtpinHwHelperFactory[gfxFamily] = &GTPinHwHelperHw<Family>::get();
}
};
static GTPinEnableGen11 gtpinEnable;
} // namespace NEO

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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/debug_settings/debug_settings_manager.h"
#include "core/gen11/hw_cmds.h"
#include "helpers/hardware_commands_helper.h"
#include "helpers/hardware_commands_helper.inl"
#include "helpers/hardware_commands_helper_base.inl"
namespace NEO {
template <>
bool HardwareCommandsHelper<ICLFamily>::doBindingTablePrefetch() {
return false;
}
template struct HardwareCommandsHelper<ICLFamily>;
} // namespace NEO

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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/helpers/flat_batch_buffer_helper_hw.inl"
#include "core/helpers/hw_helper_bdw_plus.inl"
#include "aub/aub_helper_bdw_plus.inl"
namespace NEO {
typedef ICLFamily Family;
template <>
uint32_t HwHelperHw<Family>::getComputeUnitsUsedForScratch(const HardwareInfo *pHwInfo) const {
return pHwInfo->gtSystemInfo.MaxSubSlicesSupported * pHwInfo->gtSystemInfo.MaxEuPerSubSlice * 8;
}
template <>
std::string HwHelperHw<Family>::getExtensions() const {
return "cl_intel_subgroup_local_block_io ";
}
template class AubHelperHw<Family>;
template class HwHelperHw<Family>;
template class FlatBatchBufferHelperHw<Family>;
template struct MemorySynchronizationCommands<Family>;
} // namespace NEO

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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/gen11/hw_cmds.h"
#include "core/memory_manager/memory_constants.h"
#include "aub_mem_dump/aub_services.h"
#include "engine_node.h"
namespace NEO {
const char *HwMapper<IGFX_ELKHARTLAKE>::abbreviation = "ehl";
bool isSimulationEHL(unsigned short deviceId) {
switch (deviceId) {
case IEHL_1x4x8_SUPERSKU_DEVICE_A0_ID:
return true;
}
return false;
};
const PLATFORM EHL::platform = {
IGFX_ELKHARTLAKE,
PCH_UNKNOWN,
IGFX_GEN11_CORE,
IGFX_GEN11_CORE,
PLATFORM_NONE, // default init
0, // usDeviceID
0, // usRevId. 0 sets the stepping to A0
0, // usDeviceID_PCH
0, // usRevId_PCH
GTTYPE_UNDEFINED};
const RuntimeCapabilityTable EHL::capabilityTable{
EngineDirectSubmissionInitVec{
{aub_stream::ENGINE_RCS, {true, true}}}, // directSubmissionEngines
{0, 0, 0, false, false, false}, // kmdNotifyProperties
MemoryConstants::max36BitAddress, // gpuAddressSpace
83.333, // defaultProfilingTimerResolution
MemoryConstants::pageSize, // requiredPreemptionSurfaceSize
&isSimulationEHL, // isSimulation
PreemptionMode::MidThread, // defaultPreemptionMode
aub_stream::ENGINE_RCS, // defaultEngineType
0, // maxRenderFrequency
12, // clVersionSupport
CmdServicesMemTraceVersion::DeviceValues::Ehl, // aubDeviceId
1, // extraQuantityThreadsPerEU
64, // slmSize
sizeof(EHL::GRF), // grfSize
false, // blitterOperationsSupported
false, // ftrSupportsInteger64BitAtomics
false, // ftrSupportsFP64
false, // ftrSupports64BitMath
false, // ftrSvm
true, // ftrSupportsCoherency
true, // ftrSupportsVmeAvcTextureSampler
true, // ftrSupportsVmeAvcPreemption
false, // ftrRenderCompressedBuffers
false, // ftrRenderCompressedImages
true, // ftr64KBpages
true, // instrumentationEnabled
true, // forceStatelessCompilationFor32Bit
"lp", // platformType
true, // sourceLevelDebuggerSupported
false, // supportsVme
false, // supportCacheFlushAfterWalker
true, // supportsImages
true, // supportsDeviceEnqueue
true // hostPtrTrackingEnabled
};
WorkaroundTable EHL::workaroundTable = {};
FeatureTable EHL::featureTable = {};
void EHL::setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo) {
FeatureTable *featureTable = &hwInfo->featureTable;
WorkaroundTable *workaroundTable = &hwInfo->workaroundTable;
featureTable->ftrL3IACoherency = true;
featureTable->ftrPPGTT = true;
featureTable->ftrSVM = true;
featureTable->ftrIA32eGfxPTEs = true;
featureTable->ftrStandardMipTailFormat = true;
featureTable->ftrDisplayYTiling = true;
featureTable->ftrTranslationTable = true;
featureTable->ftrUserModeTranslationTable = true;
featureTable->ftrTileMappedResource = true;
featureTable->ftrEnableGuC = true;
featureTable->ftrFbc = true;
featureTable->ftrFbc2AddressTranslation = true;
featureTable->ftrFbcBlitterTracking = true;
featureTable->ftrFbcCpuTracking = true;
featureTable->ftrTileY = true;
featureTable->ftrAstcHdr2D = true;
featureTable->ftrAstcLdr2D = true;
featureTable->ftr3dMidBatchPreempt = true;
featureTable->ftrGpGpuMidBatchPreempt = true;
featureTable->ftrGpGpuMidThreadLevelPreempt = true;
featureTable->ftrGpGpuThreadGroupLevelPreempt = true;
featureTable->ftrPerCtxtPreemptionGranularityControl = true;
workaroundTable->wa4kAlignUVOffsetNV12LinearSurface = true;
workaroundTable->waReportPerfCountUseGlobalContextID = true;
};
const HardwareInfo EHL_1x2x4::hwInfo = {
&EHL::platform,
&EHL::featureTable,
&EHL::workaroundTable,
&EHL_1x2x4::gtSystemInfo,
EHL::capabilityTable,
};
GT_SYSTEM_INFO EHL_1x2x4::gtSystemInfo = {0};
void EHL_1x2x4::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable) {
GT_SYSTEM_INFO *gtSysInfo = &hwInfo->gtSystemInfo;
gtSysInfo->ThreadCount = gtSysInfo->EUCount * EHL::threadsPerEu;
gtSysInfo->SliceCount = 1;
gtSysInfo->L3CacheSizeInKb = 1280;
gtSysInfo->L3BankCount = 4;
gtSysInfo->MaxFillRate = 8;
gtSysInfo->TotalVsThreads = 56;
gtSysInfo->TotalHsThreads = 56;
gtSysInfo->TotalDsThreads = 56;
gtSysInfo->TotalGsThreads = 56;
gtSysInfo->TotalPsThreadsWindowerRange = 64;
gtSysInfo->CsrSizeInMb = 8;
gtSysInfo->MaxEuPerSubSlice = EHL::maxEuPerSubslice;
gtSysInfo->MaxSlicesSupported = EHL::maxSlicesSupported;
gtSysInfo->MaxSubSlicesSupported = EHL::maxSubslicesSupported;
gtSysInfo->IsL3HashModeEnabled = false;
gtSysInfo->IsDynamicallyPopulated = false;
if (setupFeatureTableAndWorkaroundTable) {
setupFeatureAndWorkaroundTable(hwInfo);
}
};
const HardwareInfo EHL_1x4x4::hwInfo = {
&EHL::platform,
&EHL::featureTable,
&EHL::workaroundTable,
&EHL_1x4x4::gtSystemInfo,
EHL::capabilityTable,
};
GT_SYSTEM_INFO EHL_1x4x4::gtSystemInfo = {0};
void EHL_1x4x4::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable) {
GT_SYSTEM_INFO *gtSysInfo = &hwInfo->gtSystemInfo;
gtSysInfo->ThreadCount = gtSysInfo->EUCount * EHL::threadsPerEu;
gtSysInfo->SliceCount = 1;
gtSysInfo->L3CacheSizeInKb = 1280;
gtSysInfo->L3BankCount = 4;
gtSysInfo->MaxFillRate = 8;
gtSysInfo->TotalVsThreads = 112;
gtSysInfo->TotalHsThreads = 112;
gtSysInfo->TotalDsThreads = 112;
gtSysInfo->TotalGsThreads = 112;
gtSysInfo->TotalPsThreadsWindowerRange = 64;
gtSysInfo->CsrSizeInMb = 8;
gtSysInfo->MaxEuPerSubSlice = EHL::maxEuPerSubslice;
gtSysInfo->MaxSlicesSupported = EHL::maxSlicesSupported;
gtSysInfo->MaxSubSlicesSupported = EHL::maxSubslicesSupported;
gtSysInfo->IsL3HashModeEnabled = false;
gtSysInfo->IsDynamicallyPopulated = false;
if (setupFeatureTableAndWorkaroundTable) {
setupFeatureAndWorkaroundTable(hwInfo);
}
};
const HardwareInfo EHL_1x4x8::hwInfo = {
&EHL::platform,
&EHL::featureTable,
&EHL::workaroundTable,
&EHL_1x4x8::gtSystemInfo,
EHL::capabilityTable,
};
GT_SYSTEM_INFO EHL_1x4x8::gtSystemInfo = {0};
void EHL_1x4x8::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable) {
GT_SYSTEM_INFO *gtSysInfo = &hwInfo->gtSystemInfo;
gtSysInfo->ThreadCount = gtSysInfo->EUCount * EHL::threadsPerEu;
gtSysInfo->SliceCount = 1;
gtSysInfo->L3CacheSizeInKb = 1280;
gtSysInfo->L3BankCount = 4;
gtSysInfo->MaxFillRate = 8;
gtSysInfo->TotalVsThreads = 224;
gtSysInfo->TotalHsThreads = 224;
gtSysInfo->TotalDsThreads = 224;
gtSysInfo->TotalGsThreads = 224;
gtSysInfo->TotalPsThreadsWindowerRange = 64;
gtSysInfo->CsrSizeInMb = 8;
gtSysInfo->MaxEuPerSubSlice = EHL::maxEuPerSubslice;
gtSysInfo->MaxSlicesSupported = EHL::maxSlicesSupported;
gtSysInfo->MaxSubSlicesSupported = EHL::maxSubslicesSupported;
gtSysInfo->IsL3HashModeEnabled = false;
gtSysInfo->IsDynamicallyPopulated = false;
if (setupFeatureTableAndWorkaroundTable) {
setupFeatureAndWorkaroundTable(hwInfo);
}
};
const HardwareInfo EHL_1x4x6::hwInfo = {
&EHL::platform,
&EHL::featureTable,
&EHL::workaroundTable,
&EHL_1x4x6::gtSystemInfo,
EHL::capabilityTable,
};
GT_SYSTEM_INFO EHL_1x4x6::gtSystemInfo = {0};
void EHL_1x4x6::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable) {
GT_SYSTEM_INFO *gtSysInfo = &hwInfo->gtSystemInfo;
gtSysInfo->ThreadCount = gtSysInfo->EUCount * EHL::threadsPerEu;
gtSysInfo->SliceCount = 1;
gtSysInfo->L3CacheSizeInKb = 1280;
gtSysInfo->L3BankCount = 4;
gtSysInfo->MaxFillRate = 8;
gtSysInfo->TotalVsThreads = 168;
gtSysInfo->TotalHsThreads = 168;
gtSysInfo->TotalDsThreads = 168;
gtSysInfo->TotalGsThreads = 168;
gtSysInfo->TotalPsThreadsWindowerRange = 64;
gtSysInfo->CsrSizeInMb = 8;
gtSysInfo->MaxEuPerSubSlice = EHL::maxEuPerSubslice;
gtSysInfo->MaxSlicesSupported = EHL::maxSlicesSupported;
gtSysInfo->MaxSubSlicesSupported = EHL::maxSubslicesSupported;
gtSysInfo->IsL3HashModeEnabled = false;
gtSysInfo->IsDynamicallyPopulated = false;
if (setupFeatureTableAndWorkaroundTable) {
setupFeatureAndWorkaroundTable(hwInfo);
}
};
const HardwareInfo EHL::hwInfo = EHL_1x4x8::hwInfo;
const uint64_t EHL::defaultHardwareInfoConfig = 0x100040008;
void setupEHLHardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig) {
if (hwInfoConfig == 0x100040008) {
EHL_1x4x8::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable);
} else if (hwInfoConfig == 0x100040006) {
EHL_1x4x6::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable);
} else if (hwInfoConfig == 0x100040004) {
EHL_1x4x4::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable);
} else if (hwInfoConfig == 0x100020004) {
EHL_1x2x4::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable);
} else if (hwInfoConfig == 0x0) {
// Default config
EHL_1x4x8::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable);
} else {
UNRECOVERABLE_IF(true);
}
}
void (*EHL::setupHardwareInfo)(HardwareInfo *, bool, uint64_t) = setupEHLHardwareInfoImpl;
} // namespace NEO

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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#ifdef SUPPORT_ICLLP
#include "hw_info_icllp.inl"
#endif
#ifdef SUPPORT_LKF
#include "hw_info_lkf.inl"
#endif
#ifdef SUPPORT_EHL
#include "hw_info_ehl.inl"
#endif
namespace NEO {
const char *GfxFamilyMapper<IGFX_GEN11_CORE>::name = "Gen11";
} // namespace NEO

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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/gen11/hw_cmds.h"
#include "core/memory_manager/memory_constants.h"
#include "aub_mem_dump/aub_services.h"
#include "engine_node.h"
namespace NEO {
const char *HwMapper<IGFX_ICELAKE_LP>::abbreviation = "icllp";
bool isSimulationICLLP(unsigned short deviceId) {
switch (deviceId) {
case IICL_LP_GT1_MOB_DEVICE_F0_ID:
return true;
}
return false;
};
const PLATFORM ICLLP::platform = {
IGFX_ICELAKE_LP,
PCH_UNKNOWN,
IGFX_GEN11_CORE,
IGFX_GEN11_CORE,
PLATFORM_NONE, // default init
0, // usDeviceID
0, // usRevId. 0 sets the stepping to A0
0, // usDeviceID_PCH
0, // usRevId_PCH
GTTYPE_UNDEFINED};
const RuntimeCapabilityTable ICLLP::capabilityTable{
EngineDirectSubmissionInitVec{
{aub_stream::ENGINE_RCS, {true, true}}}, // directSubmissionEngines
{0, 0, 0, false, false, false}, // kmdNotifyProperties
MemoryConstants::max48BitAddress, // gpuAddressSpace
83.333, // defaultProfilingTimerResolution
MemoryConstants::pageSize, // requiredPreemptionSurfaceSize
&isSimulationICLLP, // isSimulation
PreemptionMode::MidThread, // defaultPreemptionMode
aub_stream::ENGINE_RCS, // defaultEngineType
0, // maxRenderFrequency
21, // clVersionSupport
CmdServicesMemTraceVersion::DeviceValues::Icllp, // aubDeviceId
1, // extraQuantityThreadsPerEU
64, // slmSize
sizeof(ICLLP::GRF), // grfSize
false, // blitterOperationsSupported
true, // ftrSupportsInteger64BitAtomics
false, // ftrSupportsFP64
false, // ftrSupports64BitMath
true, // ftrSvm
true, // ftrSupportsCoherency
true, // ftrSupportsVmeAvcTextureSampler
true, // ftrSupportsVmeAvcPreemption
false, // ftrRenderCompressedBuffers
false, // ftrRenderCompressedImages
false, // ftr64KBpages
true, // instrumentationEnabled
true, // forceStatelessCompilationFor32Bit
"lp", // platformType
true, // sourceLevelDebuggerSupported
true, // supportsVme
false, // supportCacheFlushAfterWalker
true, // supportsImages
true, // supportsDeviceEnqueue
true // hostPtrTrackingEnabled
};
WorkaroundTable ICLLP::workaroundTable = {};
FeatureTable ICLLP::featureTable = {};
void ICLLP::setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo) {
FeatureTable *featureTable = &hwInfo->featureTable;
WorkaroundTable *workaroundTable = &hwInfo->workaroundTable;
featureTable->ftrL3IACoherency = true;
featureTable->ftrPPGTT = true;
featureTable->ftrSVM = true;
featureTable->ftrIA32eGfxPTEs = true;
featureTable->ftrStandardMipTailFormat = true;
featureTable->ftrDisplayYTiling = true;
featureTable->ftrTranslationTable = true;
featureTable->ftrUserModeTranslationTable = true;
featureTable->ftrTileMappedResource = true;
featureTable->ftrEnableGuC = true;
featureTable->ftrFbc = true;
featureTable->ftrFbc2AddressTranslation = true;
featureTable->ftrFbcBlitterTracking = true;
featureTable->ftrFbcCpuTracking = true;
featureTable->ftrTileY = true;
featureTable->ftrAstcHdr2D = true;
featureTable->ftrAstcLdr2D = true;
featureTable->ftr3dMidBatchPreempt = true;
featureTable->ftrGpGpuMidBatchPreempt = true;
featureTable->ftrGpGpuMidThreadLevelPreempt = true;
featureTable->ftrGpGpuThreadGroupLevelPreempt = true;
featureTable->ftrPerCtxtPreemptionGranularityControl = true;
workaroundTable->wa4kAlignUVOffsetNV12LinearSurface = true;
workaroundTable->waReportPerfCountUseGlobalContextID = true;
};
const HardwareInfo ICLLP_1x8x8::hwInfo = {
&ICLLP::platform,
&ICLLP::featureTable,
&ICLLP::workaroundTable,
&ICLLP_1x8x8::gtSystemInfo,
ICLLP::capabilityTable,
};
GT_SYSTEM_INFO ICLLP_1x8x8::gtSystemInfo = {0};
void ICLLP_1x8x8::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable) {
GT_SYSTEM_INFO *gtSysInfo = &hwInfo->gtSystemInfo;
gtSysInfo->ThreadCount = gtSysInfo->EUCount * ICLLP::threadsPerEu;
gtSysInfo->SliceCount = 1;
gtSysInfo->L3CacheSizeInKb = 3072;
gtSysInfo->L3BankCount = 8;
gtSysInfo->MaxFillRate = 16;
gtSysInfo->TotalVsThreads = 336;
gtSysInfo->TotalHsThreads = 336;
gtSysInfo->TotalDsThreads = 336;
gtSysInfo->TotalGsThreads = 336;
gtSysInfo->TotalPsThreadsWindowerRange = 64;
gtSysInfo->CsrSizeInMb = 5;
gtSysInfo->MaxEuPerSubSlice = ICLLP::maxEuPerSubslice;
gtSysInfo->MaxSlicesSupported = ICLLP::maxSlicesSupported;
gtSysInfo->MaxSubSlicesSupported = ICLLP::maxSubslicesSupported;
gtSysInfo->IsL3HashModeEnabled = false;
gtSysInfo->IsDynamicallyPopulated = false;
if (setupFeatureTableAndWorkaroundTable) {
setupFeatureAndWorkaroundTable(hwInfo);
}
};
const HardwareInfo ICLLP_1x4x8::hwInfo = {
&ICLLP::platform,
&ICLLP::featureTable,
&ICLLP::workaroundTable,
&ICLLP_1x4x8::gtSystemInfo,
ICLLP::capabilityTable,
};
GT_SYSTEM_INFO ICLLP_1x4x8::gtSystemInfo = {0};
void ICLLP_1x4x8::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable) {
GT_SYSTEM_INFO *gtSysInfo = &hwInfo->gtSystemInfo;
gtSysInfo->ThreadCount = gtSysInfo->EUCount * ICLLP::threadsPerEu;
gtSysInfo->SliceCount = 1;
gtSysInfo->L3CacheSizeInKb = 2304;
gtSysInfo->L3BankCount = 6;
gtSysInfo->MaxFillRate = 8;
gtSysInfo->TotalVsThreads = 364;
gtSysInfo->TotalHsThreads = 224;
gtSysInfo->TotalDsThreads = 364;
gtSysInfo->TotalGsThreads = 224;
gtSysInfo->TotalPsThreadsWindowerRange = 128;
gtSysInfo->CsrSizeInMb = 5;
gtSysInfo->MaxEuPerSubSlice = ICLLP::maxEuPerSubslice;
gtSysInfo->MaxSlicesSupported = ICLLP::maxSlicesSupported;
gtSysInfo->MaxSubSlicesSupported = ICLLP::maxSubslicesSupported;
gtSysInfo->IsL3HashModeEnabled = false;
gtSysInfo->IsDynamicallyPopulated = false;
if (setupFeatureTableAndWorkaroundTable) {
setupFeatureAndWorkaroundTable(hwInfo);
}
};
const HardwareInfo ICLLP_1x6x8::hwInfo = {
&ICLLP::platform,
&ICLLP::featureTable,
&ICLLP::workaroundTable,
&ICLLP_1x6x8::gtSystemInfo,
ICLLP::capabilityTable,
};
GT_SYSTEM_INFO ICLLP_1x6x8::gtSystemInfo = {0};
void ICLLP_1x6x8::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable) {
GT_SYSTEM_INFO *gtSysInfo = &hwInfo->gtSystemInfo;
gtSysInfo->ThreadCount = gtSysInfo->EUCount * ICLLP::threadsPerEu;
gtSysInfo->SliceCount = 1;
gtSysInfo->L3CacheSizeInKb = 2304;
gtSysInfo->L3BankCount = 6;
gtSysInfo->MaxFillRate = 8;
gtSysInfo->TotalVsThreads = 364;
gtSysInfo->TotalHsThreads = 224;
gtSysInfo->TotalDsThreads = 364;
gtSysInfo->TotalGsThreads = 224;
gtSysInfo->TotalPsThreadsWindowerRange = 128;
gtSysInfo->CsrSizeInMb = 5;
gtSysInfo->MaxEuPerSubSlice = ICLLP::maxEuPerSubslice;
gtSysInfo->MaxSlicesSupported = ICLLP::maxSlicesSupported;
gtSysInfo->MaxSubSlicesSupported = ICLLP::maxSubslicesSupported;
gtSysInfo->IsL3HashModeEnabled = false;
gtSysInfo->IsDynamicallyPopulated = false;
if (setupFeatureTableAndWorkaroundTable) {
setupFeatureAndWorkaroundTable(hwInfo);
}
};
const HardwareInfo ICLLP::hwInfo = ICLLP_1x8x8::hwInfo;
const uint64_t ICLLP::defaultHardwareInfoConfig = 0x100080008;
void setupICLLPHardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig) {
if (hwInfoConfig == 0x100080008) {
ICLLP_1x8x8::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable);
} else if (hwInfoConfig == 0x100040008) {
ICLLP_1x4x8::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable);
} else if (hwInfoConfig == 0x100060008) {
ICLLP_1x6x8::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable);
} else if (hwInfoConfig == 0x0) {
// Default config
ICLLP_1x8x8::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable);
} else {
UNRECOVERABLE_IF(true);
}
}
void (*ICLLP::setupHardwareInfo)(HardwareInfo *, bool, uint64_t) = setupICLLPHardwareInfoImpl;
} // namespace NEO

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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/gen11/hw_cmds_lkf.h"
#include "core/memory_manager/memory_constants.h"
#include "aub_mem_dump/aub_services.h"
#include "engine_node.h"
namespace NEO {
const char *HwMapper<IGFX_LAKEFIELD>::abbreviation = "lkf";
bool isSimulationLKF(unsigned short deviceId) {
switch (deviceId) {
case ILKF_1x8x8_DESK_DEVICE_F0_ID:
return true;
}
return false;
};
const PLATFORM LKF::platform = {
IGFX_LAKEFIELD,
PCH_UNKNOWN,
IGFX_GEN11_CORE,
IGFX_GEN11_CORE,
PLATFORM_NONE, // default init
0, // usDeviceID
0, // usRevId. 0 sets the stepping to A0
0, // usDeviceID_PCH
0, // usRevId_PCH
GTTYPE_UNDEFINED};
const RuntimeCapabilityTable LKF::capabilityTable{
EngineDirectSubmissionInitVec{
{aub_stream::ENGINE_RCS, {true, true}}}, // directSubmissionEngines
{0, 0, 0, false, false, false}, // kmdNotifyProperties
MemoryConstants::max36BitAddress, // gpuAddressSpace
83.333, // defaultProfilingTimerResolution
MemoryConstants::pageSize, // requiredPreemptionSurfaceSize
&isSimulationLKF, // isSimulation
PreemptionMode::MidThread, // defaultPreemptionMode
aub_stream::ENGINE_RCS, // defaultEngineType
0, // maxRenderFrequency
12, // clVersionSupport
CmdServicesMemTraceVersion::DeviceValues::Lkf, // aubDeviceId
1, // extraQuantityThreadsPerEU
64, // slmSize
sizeof(LKF::GRF), // grfSize
false, // blitterOperationsSupported
false, // ftrSupportsInteger64BitAtomics
false, // ftrSupportsFP64
false, // ftrSupports64BitMath
false, // ftrSvm
true, // ftrSupportsCoherency
false, // ftrSupportsVmeAvcTextureSampler
false, // ftrSupportsVmeAvcPreemption
false, // ftrRenderCompressedBuffers
false, // ftrRenderCompressedImages
true, // ftr64KBpages
true, // instrumentationEnabled
true, // forceStatelessCompilationFor32Bit
"lp", // platformType
true, // sourceLevelDebuggerSupported
false, // supportsVme
false, // supportCacheFlushAfterWalker
true, // supportsImages
true, // supportsDeviceEnqueue
true // hostPtrTrackingEnabled
};
WorkaroundTable LKF::workaroundTable = {};
FeatureTable LKF::featureTable = {};
void LKF::setupFeatureAndWorkaroundTable(HardwareInfo *hwInfo) {
FeatureTable *featureTable = &hwInfo->featureTable;
WorkaroundTable *workaroundTable = &hwInfo->workaroundTable;
featureTable->ftrL3IACoherency = true;
featureTable->ftrPPGTT = true;
featureTable->ftrSVM = true;
featureTable->ftrIA32eGfxPTEs = true;
featureTable->ftrStandardMipTailFormat = true;
featureTable->ftrDisplayYTiling = true;
featureTable->ftrTranslationTable = true;
featureTable->ftrUserModeTranslationTable = true;
featureTable->ftrTileMappedResource = true;
featureTable->ftrEnableGuC = true;
featureTable->ftrFbc = true;
featureTable->ftrFbc2AddressTranslation = true;
featureTable->ftrFbcBlitterTracking = true;
featureTable->ftrFbcCpuTracking = true;
featureTable->ftrTileY = true;
featureTable->ftrAstcHdr2D = true;
featureTable->ftrAstcLdr2D = true;
featureTable->ftr3dMidBatchPreempt = true;
featureTable->ftrGpGpuMidBatchPreempt = true;
featureTable->ftrGpGpuMidThreadLevelPreempt = true;
featureTable->ftrGpGpuThreadGroupLevelPreempt = true;
featureTable->ftrPerCtxtPreemptionGranularityControl = true;
workaroundTable->wa4kAlignUVOffsetNV12LinearSurface = true;
workaroundTable->waReportPerfCountUseGlobalContextID = true;
};
const HardwareInfo LKF_1x8x8::hwInfo = {
&LKF::platform,
&LKF::featureTable,
&LKF::workaroundTable,
&LKF_1x8x8::gtSystemInfo,
LKF::capabilityTable,
};
GT_SYSTEM_INFO LKF_1x8x8::gtSystemInfo = {0};
void LKF_1x8x8::setupHardwareInfo(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable) {
GT_SYSTEM_INFO *gtSysInfo = &hwInfo->gtSystemInfo;
gtSysInfo->ThreadCount = gtSysInfo->EUCount * LKF::threadsPerEu;
gtSysInfo->SliceCount = 1;
gtSysInfo->L3CacheSizeInKb = 2560;
gtSysInfo->L3BankCount = 8;
gtSysInfo->MaxFillRate = 16;
gtSysInfo->TotalVsThreads = 448;
gtSysInfo->TotalHsThreads = 448;
gtSysInfo->TotalDsThreads = 448;
gtSysInfo->TotalGsThreads = 448;
gtSysInfo->TotalPsThreadsWindowerRange = 64;
gtSysInfo->CsrSizeInMb = 8;
gtSysInfo->MaxEuPerSubSlice = LKF::maxEuPerSubslice;
gtSysInfo->MaxSlicesSupported = LKF::maxSlicesSupported;
gtSysInfo->MaxSubSlicesSupported = LKF::maxSubslicesSupported;
gtSysInfo->IsL3HashModeEnabled = false;
gtSysInfo->IsDynamicallyPopulated = false;
if (setupFeatureTableAndWorkaroundTable) {
setupFeatureAndWorkaroundTable(hwInfo);
}
};
const HardwareInfo LKF::hwInfo = LKF_1x8x8::hwInfo;
const uint64_t LKF::defaultHardwareInfoConfig = 0x100080008;
void setupLKFHardwareInfoImpl(HardwareInfo *hwInfo, bool setupFeatureTableAndWorkaroundTable, uint64_t hwInfoConfig) {
if (hwInfoConfig == 0x100080008) {
LKF_1x8x8::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable);
} else if (hwInfoConfig == 0x0) {
// Default config
LKF_1x8x8::setupHardwareInfo(hwInfo, setupFeatureTableAndWorkaroundTable);
} else {
UNRECOVERABLE_IF(true);
}
}
void (*LKF::setupHardwareInfo)(HardwareInfo *, bool, uint64_t) = setupLKFHardwareInfoImpl;
} // namespace NEO

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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/gen11/hw_cmds_base.h"
#include "mem_obj/image.h"
#include "mem_obj/image.inl"
#include <map>
namespace NEO {
typedef ICLFamily Family;
static auto gfxCore = IGFX_GEN11_CORE;
template <typename GfxFamily>
void ImageHw<GfxFamily>::setMediaSurfaceRotation(void *memory) {
using MEDIA_SURFACE_STATE = typename GfxFamily::MEDIA_SURFACE_STATE;
using SURFACE_FORMAT = typename MEDIA_SURFACE_STATE::SURFACE_FORMAT;
auto surfaceState = reinterpret_cast<MEDIA_SURFACE_STATE *>(memory);
surfaceState->setRotation(MEDIA_SURFACE_STATE::ROTATION_NO_ROTATION_OR_0_DEGREE);
surfaceState->setXOffset(0);
surfaceState->setYOffset(0);
}
template <typename GfxFamily>
void ImageHw<GfxFamily>::setSurfaceMemoryObjectControlStateIndexToMocsTable(void *memory, uint32_t value) {
using MEDIA_SURFACE_STATE = typename GfxFamily::MEDIA_SURFACE_STATE;
using SURFACE_FORMAT = typename MEDIA_SURFACE_STATE::SURFACE_FORMAT;
auto surfaceState = reinterpret_cast<MEDIA_SURFACE_STATE *>(memory);
surfaceState->setSurfaceMemoryObjectControlStateIndexToMocsTables(value);
}
template <>
void ImageHw<Family>::appendSurfaceStateParams(RENDER_SURFACE_STATE *surfaceState) {
if (hasAlphaChannel(&imageFormat)) {
surfaceState->setSampleTapDiscardDisable(RENDER_SURFACE_STATE::SAMPLE_TAP_DISCARD_DISABLE_ENABLE);
}
}
#include "mem_obj/image_factory_init.inl"
} // namespace NEO

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opencl/source/gen11/linux/command_stream_receiver_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "command_stream/command_stream_receiver_with_aub_dump.inl"
#include "os_interface/linux/device_command_stream.inl"
#include "os_interface/linux/drm_command_stream.inl"
#include "os_interface/linux/drm_command_stream_bdw_plus.inl"
namespace NEO {
template class DeviceCommandStreamReceiver<ICLFamily>;
template class DrmCommandStreamReceiver<ICLFamily>;
template class CommandStreamReceiverWithAUBDump<DrmCommandStreamReceiver<ICLFamily>>;
} // namespace NEO

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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/helpers/hw_info.h"
#include "core/os_interface/hw_info_config.h"
namespace NEO {
template <>
int HwInfoConfigHw<IGFX_ELKHARTLAKE>::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) {
if (nullptr == osIface) {
return 0;
}
GT_SYSTEM_INFO *gtSystemInfo = &hwInfo->gtSystemInfo;
gtSystemInfo->SliceCount = 1;
return 0;
}
template class HwInfoConfigHw<IGFX_ELKHARTLAKE>;
} // namespace NEO

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opencl/source/gen11/linux/hw_info_config_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/os_interface/hw_info_config.inl"
#include "core/os_interface/hw_info_config_bdw_plus.inl"
#ifdef SUPPORT_ICLLP
#include "hw_info_config_icllp.inl"
#endif
#ifdef SUPPORT_LKF
#include "hw_info_config_lkf.inl"
#endif
#ifdef SUPPORT_EHL
#include "hw_info_config_ehl.inl"
#endif

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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/helpers/hw_info.h"
#include "core/os_interface/hw_info_config.h"
namespace NEO {
template <>
int HwInfoConfigHw<IGFX_ICELAKE_LP>::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) {
if (nullptr == osIface) {
return 0;
}
GT_SYSTEM_INFO *gtSystemInfo = &hwInfo->gtSystemInfo;
gtSystemInfo->SliceCount = 1;
return 0;
}
template class HwInfoConfigHw<IGFX_ICELAKE_LP>;
} // namespace NEO

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opencl/source/gen11/linux/hw_info_config_lkf.inl Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/helpers/hw_info.h"
#include "core/os_interface/hw_info_config.h"
namespace NEO {
template <>
int HwInfoConfigHw<IGFX_LAKEFIELD>::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) {
if (nullptr == osIface) {
return 0;
}
GT_SYSTEM_INFO *gtSystemInfo = &hwInfo->gtSystemInfo;
gtSystemInfo->SliceCount = 1;
return 0;
}
template class HwInfoConfigHw<IGFX_LAKEFIELD>;
} // namespace NEO

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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "core/helpers/preamble.h"
namespace NEO {
struct ICLFamily;
template <>
struct L3CNTLREGConfig<IGFX_ICELAKE_LP> {
static const uint32_t valueForSLM = 0xA0000720u;
static const uint32_t valueForNoSLM = 0xA0000720u;
};
template <>
struct L3CNTLRegisterOffset<ICLFamily> {
static const uint32_t registerOffset = 0x7034;
};
template <>
struct DebugModeRegisterOffset<ICLFamily> {
enum {
registerOffset = 0x20d8,
debugEnabledValue = (1 << 5) | (1 << 21)
};
};
namespace gen11HdcModeRegister {
const uint32_t address = 0xE5F4;
const uint32_t forceNonCoherentEnableBit = 4;
} // namespace gen11HdcModeRegister
namespace gen11PowerClockStateRegister {
const uint32_t address = 0x20C8;
const uint32_t minEuCountShift = 0;
const uint32_t maxEuCountShift = 4;
const uint32_t subSliceCountShift = 8;
const uint32_t sliceCountShift = 12;
const uint32_t vmeSliceCount = 1;
const uint32_t enabledValue = 0x80040800u;
const uint32_t disabledValue = 0x80040800u;
} // namespace gen11PowerClockStateRegister
} // namespace NEO

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opencl/source/gen11/sampler_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/gen11/hw_cmds.h"
#include "sampler/sampler.h"
#include "sampler/sampler.inl"
namespace NEO {
typedef ICLFamily Family;
static auto gfxCore = IGFX_GEN11_CORE;
#include "sampler/sampler_factory_init.inl"
} // namespace NEO

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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "scheduler_definitions.h"
uint GetPatchValueForSLMSize(uint slMsize) {
uint PatchValue = 0;
if (slMsize == 0) {
PatchValue = 0;
} else if (slMsize <= (1 * 1024)) {
PatchValue = 1;
} else if (slMsize <= (2 * 1024)) {
PatchValue = 2;
} else if (slMsize <= (4 * 1024)) {
PatchValue = 3;
} else if (slMsize <= (8 * 1024)) {
PatchValue = 4;
} else if (slMsize <= (16 * 1024)) {
PatchValue = 5;
} else if (slMsize <= (32 * 1024)) {
PatchValue = 6;
} else if (slMsize <= (64 * 1024)) {
PatchValue = 7;
}
return PatchValue;
}
//on SKL we have pipe control in pairs, therefore when we NOOP we need to do this for both pipe controls
void NOOPCSStallPipeControl(__global uint *secondaryBatchBuffer, uint dwordOffset, uint pipeControlOffset) {
dwordOffset += pipeControlOffset;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
}
//on SKL+ with mid thread preemption we need to have 2 pipe controls instead of 1 any time we do post sync operation
void PutCSStallPipeControl(__global uint *secondaryBatchBuffer, uint dwordOffset, uint pipeControlOffset) {
dwordOffset += pipeControlOffset;
//first pipe control doing CS stall
secondaryBatchBuffer[dwordOffset] = PIPE_CONTROL_CSTALL_DWORD0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = PIPE_CONTROL_CSTALL_DWORD1;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
//second pipe control , doing actual timestamp write
secondaryBatchBuffer[dwordOffset] = PIPE_CONTROL_CSTALL_DWORD0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = PIPE_CONTROL_CSTALL_DWORD1;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
secondaryBatchBuffer[dwordOffset] = 0;
dwordOffset++;
}

147
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#define SCHEDULER_COMPILATION_SIZE 8
#define SIZEOF_INTERFACE_DESCRIPTOR_DATA_G11 32
#define NUMBER_OF_INERFACE_DESCRIPTORS 64
#define IDT_BREAKDOWN (NUMBER_OF_INERFACE_DESCRIPTORS - 2)
#define MAX_WKG_SIZE 448
#define INTERFACE_DESCRIPTOR_TABLE_SIZE_G11 (NUMBER_OF_INERFACE_DESCRIPTORS * SIZEOF_INTERFACE_DESCRIPTOR_DATA_G11)
#define SIZEOF_COLOR_CALCULATOR_STATE_G11 0xC0
#define INTERFACE_DESCRIPTOR_TABLE_START_ADDRESS_G11 SIZEOF_COLOR_CALCULATOR_STATE_G11
#define OCLRT_SIZEOF_SAMPLER_STATE_G11 (16)
#define SIZEOF_COLOR_CALCULATOR_STATE SIZEOF_COLOR_CALCULATOR_STATE_G11
#define SIZEOF_INTERFACE_DESCRIPTOR_DATA SIZEOF_INTERFACE_DESCRIPTOR_DATA_G11
#define INTERFACE_DESCRIPTOR_TABLE_SIZE INTERFACE_DESCRIPTOR_TABLE_SIZE_G11
#define INTERFACE_DESCRIPTOR_TABLE_START_ADDRESS INTERFACE_DESCRIPTOR_TABLE_START_ADDRESS_G11
#define OCLRT_SIZEOF_SAMPLER_STATE OCLRT_SIZEOF_SAMPLER_STATE_G11
#define SECOND_LEVEL_BUFFER_SPACE_FOR_EACH_ENQUEUE (SECOND_LEVEL_BUFFER_SPACE_FOR_EACH_ENQUEUE_GEN11)
#define SECOND_LEVEL_BUFFER_NUMBER_OF_ENQUEUES (SECOND_LEVEL_BUFFER_NUMBER_OF_ENQUEUES_GEN11)
//#define OCLRT_MEDIA_VFE_STATE_OFFSET ( MEDIA_STATE_FLUSH_INITIAL_OFFSET + OCLRT_SIZEOF_MSFLUSH_DWORD )
#define OCLRT_MEDIA_VFE_STATE_OFFSET (0)
//address is QWORD in size and starts on DWORD 1
#define MEDIA_VFE_STATE_ADDRESS_OFFSET (OCLRT_MEDIA_VFE_STATE_OFFSET + 1)
// DWORD OFFSET
#define MEDIA_STATE_FLUSH_INITIAL_OFFSET 0
//bits 0-5 of 1st DWORD
#define MEDIA_STATE_FLUSH_INITIAL_INTERFACE_DESCRIPTOR_OFFSET (MEDIA_STATE_FLUSH_INITIAL_OFFSET + 1)
#define MI_ARB_CHECK_AFTER_MEDIA_STATE_FLUSH_INITIAL_OFFSET 0
#define MI_ATOMIC_CMD_OFFSET 0
#define MEDIA_INTERFACE_DESCRIPTOR_LOAD_OFFSET (MEDIA_STATE_FLUSH_INITIAL_OFFSET + OCLRT_SIZEOF_MSFLUSH_DWORD)
// DWORD OFFSET of InterfaceDescriptor Length
// bits 0 - 16
#define MEDIA_INTERFACE_DESCRIPTOR_LOAD_INTERFACEDESCRIPTORLENGTH_OFFSET (MEDIA_INTERFACE_DESCRIPTOR_LOAD_OFFSET + 2)
// DWORD OFFSET of Interface Descriptor Start Address
#define MEDIA_INTERFACE_DESCRIPTOR_LOAD_INTERFACEDESCRIPTORSTARTADDRESS_OFFSET (MEDIA_INTERFACE_DESCRIPTOR_LOAD_OFFSET + 3)
#define PIPE_CONTROL_FOR_TIMESTAMP_START_OFFSET (MEDIA_INTERFACE_DESCRIPTOR_LOAD_OFFSET + OCLRT_SIZEOF_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DEVICE_CMD_DWORD_OFFSET)
#define INTERFACE_DESCRIPTOR_SAMPLER_STATE_TABLE_DWORD 3
#define INTERFACE_DESCRIPTOR_BINDING_TABLE_POINTER_DWORD 4
#define INTERFACE_DESCRIPTOR_CONSTANT_URB_ENTRY_READ_OFFSET 5
#define INTERFACE_DESCRIPTOR_HWTHREADS_NUMBER_DWORD 6
#define INTERFACE_DESCRIPTOR_SLMSIZE_DWORD 6
#define INTERFACE_DESCRIPTOR_HWTHREADS_UPPER_BIT 9
#define SAMPLER_STATE_INDIRECT_STATE_MASK (0x7FFFFC0)
#define SAMPLER_STATE_BORDER_COLOR_MASK (0xFFFFFFE0)
#define SAMPLER_STATE_DESCRIPTOR_BORDER_COLOR_POINTER_DWORD 2
#define GPGPU_WALKER_OFFSET (PIPE_CONTROL_FOR_TIMESTAMP_START_OFFSET + OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G11_DWORD_OFFSET)
// DWORD OFFSET of the Interface Descriptor Offset for GPGPU_WALKER
// bits 0 - 5
#define GPGPU_WALKER_INTERFACE_DESCRIPTOR_ID_OFFSET (GPGPU_WALKER_OFFSET + 1)
// DWORD OFFSET of the Indirect data length Offset for GPGPU_WALKER
// bits 0 - 16
#define GPGPU_WALKER_INDIRECT_DATA_LENGTH_OFFSET (GPGPU_WALKER_OFFSET + 2)
// DWORD OFFSET of the Indirect Start Address for GPGPU_WALKER
#define GPGPU_WALKER_INDIRECT_START_ADDRESS_OFFSET (GPGPU_WALKER_OFFSET + 3)
// DWORD OFFSET of the Thread Width Counter Maximum for GPGPU_WALKER
// bits 0 - 5
#define GPGPU_WALKER_THREAD_WIDTH_DWORD (GPGPU_WALKER_OFFSET + 4)
// DWORD OFFSET of the Thread Height Counter Maximum for GPGPU_WALKER
// bits 8 - 13
#define GPGPU_WALKER_THREAD_HEIGHT_DWORD (GPGPU_WALKER_OFFSET + 4)
// DWORD OFFSET of the Thread Depth Counter Maximum for GPGPU_WALKER
// bits 16 - 21
#define GPGPU_WALKER_THREAD_DEPTH_DWORD (GPGPU_WALKER_OFFSET + 4)
// DWORD OFFSET of the SIMD Size for GPGPU_WALKER
// bits 30 - 31
#define GPGPU_WALKER_SIMDSIZE_DWORD (GPGPU_WALKER_OFFSET + 4)
// DWORD OFFSET of the Starting in X pos for GPGPU_WALKER
//bits 0 - 31
#define GPGPU_WALKER_GROUP_ID_START_X (GPGPU_WALKER_OFFSET + 5)
// DWORD OFFSET of the X Dimension for GPGPU_WALKER
#define GPGPU_WALKER_XDIM_DWORD (GPGPU_WALKER_OFFSET + 7)
// DWORD OFFSET of the Starting in Y pos for GPGPU_WALKER
//bits 0 - 31
#define GPGPU_WALKER_GROUP_ID_START_Y (GPGPU_WALKER_OFFSET + 8)
// DWORD OFFSET of the Y Dimension for GPGPU_WALKER
#define GPGPU_WALKER_YDIM_DWORD (GPGPU_WALKER_OFFSET + 10)
// DWORD OFFSET of the Starting in Z pos for GPGPU_WALKER
//bits 0 - 31
#define GPGPU_WALKER_GROUP_ID_START_Z (GPGPU_WALKER_OFFSET + 11)
// DWORD OFFSET of the X Dimension for GPGPU_WALKER
#define GPGPU_WALKER_ZDIM_DWORD (GPGPU_WALKER_OFFSET + 12)
// DWORD OFFSET of the Right or X Mask for GPGPU_WALKER
#define GPGPU_WALKER_XMASK_DWORD (GPGPU_WALKER_OFFSET + 13)
// DWORD OFFSET of the Bottom or Y Mask for GPGPU_WALKER
#define GPGPU_WALKER_YMASK_DWORD (GPGPU_WALKER_OFFSET + 14)
#define MEDIA_STATE_FLUSH_OFFSET (GPGPU_WALKER_OFFSET + OCLRT_GPGPU_WALKER_CMD_DEVICE_CMD_G11_DWORD_OFFSET)
//bits 0-5 of 1st DWORD of M_S_F command
#define MEDIA_STATE_FLUSH_INTERFACE_DESCRIPTOR_OFFSET (MEDIA_STATE_FLUSH_OFFSET + 1)
#define PIPE_CONTROL_FOR_TIMESTAMP_END_OFFSET (MEDIA_STATE_FLUSH_OFFSET + OCLRT_SIZEOF_MSFLUSH_DWORD)
#define PIPE_CONTROL_FOR_TIMESTAMP_END_OFFSET_TO_PATCH (PIPE_CONTROL_FOR_TIMESTAMP_END_OFFSET)
#define PIPE_CONTROL_POST_SYNC_DWORD 1
#define PIPE_CONTROL_POST_SYNC_START_BIT 14
#define PIPE_CONTROL_POST_SYNC_END_BIT 15
#define PIPE_CONTROL_GENERATE_TIME_STAMP 3
#define PIPE_CONTROL_NO_POSTSYNC_OPERATION 0
#define PIPE_CONTROL_ADDRESS_FIELD_DWORD 2
#define PIPE_CONTROL_PROFILING_START_TIMESTAMP_ADDRESS_OFFSET (PIPE_CONTROL_FOR_TIMESTAMP_START_OFFSET + PIPE_CONTROL_ADDRESS_FIELD_DWORD) //DWORD 2
#define PIPE_CONTROL_GRAPHICS_ADDRESS_START_BIT 2
#define PIPE_CONTROL_GRAPHICS_ADDRESS_END_BIT 31
#define PIPE_CONTROL_GRAPHICS_ADDRESS_HIGH_START_BIT 0
#define PIPE_CONTROL_GRAPHICS_ADDRESS_HIGH_END_BIT 15
#define PIPE_CONTROL_TIME_STAMP_DWORD0 0x7A000004
#define PIPE_CONTROL_TIME_STAMP_DWORD1 0x0010C4A4
#define PIPE_CONTROL_CSTALL_DWORD0 0x7A000004
#define PIPE_CONTROL_CSTALL_DWORD1 0x001004A4
#define PIPE_CONTROL_TAG_WRITE_DWORD0 0x7A000004
#define PIPE_CONTROL_TAG_WRITE_DWORD1 0x001044A4
// the value of g_cInitMiBatchBufferStartCmdG11 DWORD0
#define OCLRT_BATCH_BUFFER_BEGIN_CMD_DWORD0 (0x18800101)
#if defined WA_LRI_COMMANDS_EXIST
#define IMM_LOAD_REGISTER_FOR_ENABLE_PREEMPTION_OFFSET (PIPE_CONTROL_FOR_TIMESTAMP_END_OFFSET + OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G11_DWORD_OFFSET + OCLRT_PIPE_CONTROL_CMD_DEVICE_CMD_G11_DWORD_OFFSET)
#endif
#define OCLRT_LOAD_REGISTER_IMM_CMD 0x11000001
#define CTXT_PREMP_DBG_ADDRESS_VALUE 0x2248
#define CTXT_PREMP_ON_MI_ARB_CHECK_ONLY 0x00000100
#define CTXT_PREMP_DEFAULT_VALUE 0x0
#define IMM_LOAD_REGISTER_ADDRESS_DWORD_OFFSET 1
#define IMM_LOAD_REGISTER_VALUE_DWORD_OFFSET 2

13
opencl/source/gen11/state_base_address_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/helpers/state_base_address.h"
#include "core/helpers/state_base_address_bdw_plus.inl"
namespace NEO {
template struct StateBaseAddressHelper<ICLFamily>;
}

39
opencl/source/gen11/tbx_command_stream_receiver_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/gen11/hw_cmds.h"
#include "core/helpers/array_count.h"
#include "command_stream/command_stream_receiver_with_aub_dump.inl"
#include "command_stream/tbx_command_stream_receiver_hw.h"
#include "command_stream/tbx_command_stream_receiver_hw.inl"
#include "helpers/base_object.h"
namespace NEO {
typedef ICLFamily Family;
static auto gfxCore = IGFX_GEN11_CORE;
template <>
uint32_t TbxCommandStreamReceiverHw<Family>::getMaskAndValueForPollForCompletion() const {
return 0x80;
}
template <>
bool TbxCommandStreamReceiverHw<Family>::getpollNotEqualValueForPollForCompletion() const {
return true;
}
template <>
void populateFactoryTable<TbxCommandStreamReceiverHw<Family>>() {
extern TbxCommandStreamReceiverCreateFunc tbxCommandStreamReceiverFactory[IGFX_MAX_CORE];
UNRECOVERABLE_IF(!isInRange(gfxCore, tbxCommandStreamReceiverFactory));
tbxCommandStreamReceiverFactory[gfxCore] = TbxCommandStreamReceiverHw<Family>::create;
}
template class TbxCommandStreamReceiverHw<Family>;
template class CommandStreamReceiverWithAUBDump<TbxCommandStreamReceiverHw<Family>>;
} // namespace NEO

17
opencl/source/gen11/windows/command_stream_receiver_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "command_stream/command_stream_receiver_with_aub_dump.inl"
#include "os_interface/windows/device_command_stream.inl"
#include "os_interface/windows/wddm_device_command_stream.inl"
namespace NEO {
template class DeviceCommandStreamReceiver<ICLFamily>;
template class WddmCommandStreamReceiver<ICLFamily>;
template class CommandStreamReceiverWithAUBDump<WddmCommandStreamReceiver<ICLFamily>>;
} // namespace NEO

15
opencl/source/gen11/windows/gmm_callbacks_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/gen11/hw_cmds.h"
#include "core/helpers/windows/gmm_callbacks.h"
#include "core/helpers/windows/gmm_callbacks.inl"
using namespace NEO;
template struct DeviceCallbacks<ICLFamily>;
template struct TTCallbacks<ICLFamily>;

40
opencl/source/gen11/windows/hw_info_config_gen11.cpp Normal file
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/*
* Copyright (C) 2018-2020 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "core/helpers/hw_info.h"
#include "core/os_interface/hw_info_config.h"
#include "core/os_interface/hw_info_config.inl"
#include "core/os_interface/hw_info_config_bdw_plus.inl"
namespace NEO {
#ifdef SUPPORT_ICLLP
template <>
int HwInfoConfigHw<IGFX_ICELAKE_LP>::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) {
return 0;
}
template class HwInfoConfigHw<IGFX_ICELAKE_LP>;
#endif
#ifdef SUPPORT_LKF
template <>
int HwInfoConfigHw<IGFX_LAKEFIELD>::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) {
return 0;
}
template class HwInfoConfigHw<IGFX_LAKEFIELD>;
#endif
#ifdef SUPPORT_EHL
template <>
int HwInfoConfigHw<IGFX_ELKHARTLAKE>::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) {
return 0;
}
template class HwInfoConfigHw<IGFX_ELKHARTLAKE>;
#endif
} // namespace NEO