diff --git a/level_zero/core/source/cmdlist/cmdlist_hw.inl b/level_zero/core/source/cmdlist/cmdlist_hw.inl index c5fd11acd8..e175ac5e3e 100644 --- a/level_zero/core/source/cmdlist/cmdlist_hw.inl +++ b/level_zero/core/source/cmdlist/cmdlist_hw.inl @@ -3564,7 +3564,8 @@ void CommandListCoreFamily::dispatchPostSyncCompute(uint64_t gpuA value, 0u, false, - workloadPartition); + workloadPartition, + nullptr); } template diff --git a/shared/source/command_container/command_encoder.h b/shared/source/command_container/command_encoder.h index 1df46e642d..360010a4eb 100644 --- a/shared/source/command_container/command_encoder.h +++ b/shared/source/command_container/command_encoder.h @@ -587,7 +587,8 @@ struct EncodeStoreMemory { uint32_t dataDword0, uint32_t dataDword1, bool storeQword, - bool workloadPartitionOffset); + bool workloadPartitionOffset, + void **outCmdPtr); static void programStoreDataImm(MI_STORE_DATA_IMM *cmdBuffer, uint64_t gpuAddress, diff --git a/shared/source/command_container/command_encoder.inl b/shared/source/command_container/command_encoder.inl index 33ebcdd37a..32c3248494 100644 --- a/shared/source/command_container/command_encoder.inl +++ b/shared/source/command_container/command_encoder.inl @@ -1187,8 +1187,12 @@ inline void EncodeStoreMemory::programStoreDataImm(LinearStream &command uint32_t dataDword0, uint32_t dataDword1, bool storeQword, - bool workloadPartitionOffset) { + bool workloadPartitionOffset, + void **outCmdPtr) { auto miStoreDataImmBuffer = commandStream.getSpaceForCmd(); + if (outCmdPtr != nullptr) { + *outCmdPtr = miStoreDataImmBuffer; + } EncodeStoreMemory::programStoreDataImm(miStoreDataImmBuffer, gpuAddress, dataDword0, diff --git a/shared/source/debugger/debugger_l0.inl b/shared/source/debugger/debugger_l0.inl index 16807438db..b36c0115f0 100644 --- a/shared/source/debugger/debugger_l0.inl +++ b/shared/source/debugger/debugger_l0.inl @@ -1,5 +1,5 @@ /* - * Copyright (C) 2020-2023 Intel Corporation + * Copyright (C) 2020-2024 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -51,7 +51,8 @@ void DebuggerL0Hw::captureStateBaseAddress(NEO::LinearStream &cmdStre static_cast(generalStateBaseAddress & 0x0000FFFFFFFFULL), static_cast(generalStateBaseAddress >> 32), true, - false); + false, + nullptr); } if (sbaCanonized.surfaceStateBaseAddress) { auto surfaceStateBaseAddress = sbaCanonized.surfaceStateBaseAddress; @@ -60,7 +61,8 @@ void DebuggerL0Hw::captureStateBaseAddress(NEO::LinearStream &cmdStre static_cast(surfaceStateBaseAddress & 0x0000FFFFFFFFULL), static_cast(surfaceStateBaseAddress >> 32), true, - false); + false, + nullptr); } if (sbaCanonized.dynamicStateBaseAddress) { auto dynamicStateBaseAddress = sbaCanonized.dynamicStateBaseAddress; @@ -69,7 +71,8 @@ void DebuggerL0Hw::captureStateBaseAddress(NEO::LinearStream &cmdStre static_cast(dynamicStateBaseAddress & 0x0000FFFFFFFFULL), static_cast(dynamicStateBaseAddress >> 32), true, - false); + false, + nullptr); } if (sbaCanonized.indirectObjectBaseAddress) { auto indirectObjectBaseAddress = sbaCanonized.indirectObjectBaseAddress; @@ -78,7 +81,8 @@ void DebuggerL0Hw::captureStateBaseAddress(NEO::LinearStream &cmdStre static_cast(indirectObjectBaseAddress & 0x0000FFFFFFFFULL), static_cast(indirectObjectBaseAddress >> 32), true, - false); + false, + nullptr); } if (sbaCanonized.instructionBaseAddress) { auto instructionBaseAddress = sbaCanonized.instructionBaseAddress; @@ -87,7 +91,8 @@ void DebuggerL0Hw::captureStateBaseAddress(NEO::LinearStream &cmdStre static_cast(instructionBaseAddress & 0x0000FFFFFFFFULL), static_cast(instructionBaseAddress >> 32), true, - false); + false, + nullptr); } if (sbaCanonized.bindlessSurfaceStateBaseAddress) { auto bindlessSurfaceStateBaseAddress = sbaCanonized.bindlessSurfaceStateBaseAddress; @@ -96,7 +101,8 @@ void DebuggerL0Hw::captureStateBaseAddress(NEO::LinearStream &cmdStre static_cast(bindlessSurfaceStateBaseAddress & 0x0000FFFFFFFFULL), static_cast(bindlessSurfaceStateBaseAddress >> 32), true, - false); + false, + nullptr); } } } diff --git a/shared/source/direct_submission/direct_submission_hw.inl b/shared/source/direct_submission/direct_submission_hw.inl index 9dccaf68fc..c3533d2b10 100644 --- a/shared/source/direct_submission/direct_submission_hw.inl +++ b/shared/source/direct_submission/direct_submission_hw.inl @@ -655,7 +655,8 @@ void DirectSubmissionHw::updateRelaxedOrderingQueueSize(u this->currentRelaxedOrderingQueueSize = newSize; EncodeStoreMemory::programStoreDataImm(this->ringCommandStream, this->relaxedOrderingQueueSizeLimitValueVa, - this->currentRelaxedOrderingQueueSize, 0, false, false); + this->currentRelaxedOrderingQueueSize, 0, false, false, + nullptr); } template diff --git a/shared/source/direct_submission/dispatchers/dispatcher.inl b/shared/source/direct_submission/dispatchers/dispatcher.inl index 923b993624..42abb268fa 100644 --- a/shared/source/direct_submission/dispatchers/dispatcher.inl +++ b/shared/source/direct_submission/dispatchers/dispatcher.inl @@ -1,5 +1,5 @@ /* - * Copyright (C) 2020-2021 Intel Corporation + * Copyright (C) 2020-2024 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -54,7 +54,8 @@ inline void Dispatcher::dispatchStoreDwordCommand(LinearStream &cmdBu value, 0, false, - false); + false, + nullptr); } template diff --git a/shared/source/helpers/flat_batch_buffer_helper_hw.inl b/shared/source/helpers/flat_batch_buffer_helper_hw.inl index 2ff26decdb..3efccaac04 100644 --- a/shared/source/helpers/flat_batch_buffer_helper_hw.inl +++ b/shared/source/helpers/flat_batch_buffer_helper_hw.inl @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018-2023 Intel Corporation + * Copyright (C) 2018-2024 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -170,7 +170,8 @@ char *FlatBatchBufferHelperHw::getIndirectPatchCommands(size_t &indir static_cast((patchInfoData.sourceAllocation + patchInfoData.sourceAllocationOffset) & 0x0000FFFFFFFFULL), static_cast((patchInfoData.sourceAllocation + patchInfoData.sourceAllocationOffset) >> 32), !is32BitAddress, - false); + false, + nullptr); PatchInfoData patchInfoForAddress(patchInfoData.targetAllocation, patchInfoData.targetAllocationOffset, diff --git a/shared/source/helpers/timestamp_packet.h b/shared/source/helpers/timestamp_packet.h index 1326c3a4c5..a44a654231 100644 --- a/shared/source/helpers/timestamp_packet.h +++ b/shared/source/helpers/timestamp_packet.h @@ -137,7 +137,8 @@ struct TimestampPacketHelper { static void nonStallingContextEndNodeSignal(LinearStream &cmdStream, const TagNodeBase ×tampPacketNode, bool multiTileOperation) { uint64_t contextEndAddress = getContextEndGpuAddress(timestampPacketNode); - NEO::EncodeStoreMemory::programStoreDataImm(cmdStream, contextEndAddress, 0, 0, false, multiTileOperation); + NEO::EncodeStoreMemory::programStoreDataImm(cmdStream, contextEndAddress, 0, 0, false, multiTileOperation, + nullptr); } template diff --git a/shared/source/utilities/software_tags_manager.h b/shared/source/utilities/software_tags_manager.h index 28209d9f33..28efd165de 100644 --- a/shared/source/utilities/software_tags_manager.h +++ b/shared/source/utilities/software_tags_manager.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021-2023 Intel Corporation + * Copyright (C) 2021-2024 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -64,7 +64,8 @@ void SWTagsManager::insertBXMLHeapAddress(LinearStream &cmdStream) { ptr->magicNumber, 0, false, - false); + false, + nullptr); memoryManager->unlockResource(bxmlHeap); } @@ -76,7 +77,8 @@ void SWTagsManager::insertSWTagHeapAddress(LinearStream &cmdStream) { ptr->magicNumber, 0, false, - false); + false, + nullptr); memoryManager->unlockResource(tagHeap); } diff --git a/shared/test/unit_test/encoders/command_encoder_tests_xehp_and_later.cpp b/shared/test/unit_test/encoders/command_encoder_tests_xehp_and_later.cpp index 6a952f31a3..e39f025681 100644 --- a/shared/test/unit_test/encoders/command_encoder_tests_xehp_and_later.cpp +++ b/shared/test/unit_test/encoders/command_encoder_tests_xehp_and_later.cpp @@ -73,7 +73,8 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, XeHPAndLaterHardwareCommandsTest, givenPartitionArg dword0, dword1, false, - false); + false, + nullptr); auto storeDataImm = genCmdCast(buffer); ASSERT_NE(nullptr, storeDataImm); @@ -96,7 +97,8 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, XeHPAndLaterHardwareCommandsTest, givenPartitionArg dword0, dword1, false, - true); + true, + nullptr); auto storeDataImm = genCmdCast(buffer); ASSERT_NE(nullptr, storeDataImm); diff --git a/shared/test/unit_test/encoders/test_command_encoder.cpp b/shared/test/unit_test/encoders/test_command_encoder.cpp index d65030a23b..0c2bcb20d6 100644 --- a/shared/test/unit_test/encoders/test_command_encoder.cpp +++ b/shared/test/unit_test/encoders/test_command_encoder.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021-2023 Intel Corporation + * Copyright (C) 2021-2024 Intel Corporation * * SPDX-License-Identifier: MIT * @@ -125,14 +125,18 @@ HWTEST_F(CommandEncoderTest, GivenDwordStoreWhenAddingStoreDataImmThenExpectDwor uint8_t buffer[bufferSize]; LinearStream cmdStream(buffer, bufferSize); + void *outSdiCmd = nullptr; + EncodeStoreMemory::programStoreDataImm(cmdStream, gpuAddress, dword0, dword1, false, - false); + false, + &outSdiCmd); size_t usedAfter = cmdStream.getUsed(); EXPECT_EQ(size, usedAfter); + ASSERT_NE(nullptr, outSdiCmd); auto storeDataImm = genCmdCast(buffer); ASSERT_NE(nullptr, storeDataImm); @@ -141,6 +145,8 @@ HWTEST_F(CommandEncoderTest, GivenDwordStoreWhenAddingStoreDataImmThenExpectDwor EXPECT_EQ(0u, storeDataImm->getDataDword1()); EXPECT_FALSE(storeDataImm->getStoreQword()); EXPECT_EQ(MI_STORE_DATA_IMM::DWORD_LENGTH::DWORD_LENGTH_STORE_DWORD, storeDataImm->getDwordLength()); + + EXPECT_EQ(storeDataImm, outSdiCmd); } HWTEST_F(CommandEncoderTest, GivenQwordStoreWhenAddingStoreDataImmThenExpectQwordProgramming) { @@ -161,7 +167,8 @@ HWTEST_F(CommandEncoderTest, GivenQwordStoreWhenAddingStoreDataImmThenExpectQwor dword0, dword1, true, - false); + false, + nullptr); size_t usedAfter = cmdStream.getUsed(); EXPECT_EQ(size, usedAfter);