fix: Add infrastructure to force dc flush when mitigate dc

-force dc on next tag update after RT kernel
-force dc when release shared object

Related-To: NEO-10556

Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>

shared/source/command_stream/command_stream_receiver.h

@@ -329,6 +329,16 @@ class CommandStreamReceiver {
         requiresInstructionCacheFlush = true;
     }
 
+    MOCKABLE_VIRTUAL bool checkDcFlushRequiredForDcMitigationAndReset() {
+        auto ret = this->requiresDcFlush;
+        this->requiresDcFlush = false;
+        return ret;
+    }
+
+    void registerDcFlushForDcMitigation() {
+        this->requiresDcFlush = true;
+    }
+
     bool isLocalMemoryEnabled() const { return localMemoryEnabled; }
 
     uint32_t getRootDeviceIndex() const { return rootDeviceIndex; }
@@ -637,6 +647,7 @@ class CommandStreamReceiver {
     bool nTo1SubmissionModelEnabled = false;
     bool lastSystolicPipelineSelectMode = false;
     bool requiresInstructionCacheFlush = false;
+    bool requiresDcFlush = false;
 
     bool localMemoryEnabled = false;
     bool pageTableManagerInitialized = false;

shared/source/command_stream/command_stream_receiver_hw_base.inl

@@ -1206,7 +1206,7 @@ SubmissionStatus CommandStreamReceiverHw<GfxFamily>::flushPipeControl(bool state
     auto lock = obtainUniqueOwnership();
 
     PipeControlArgs args;
-    args.dcFlushEnable = this->dcFlushSupport;
+    args.dcFlushEnable = this->dcFlushSupport || this->checkDcFlushRequiredForDcMitigationAndReset();
     args.notifyEnable = isUsedNotifyEnableForPostSync();
     args.workloadPartitionOffset = isMultiTileOperationEnabled();
 
@@ -1794,6 +1794,7 @@ inline void CommandStreamReceiverHw<GfxFamily>::processBarrierWithPostSync(Linea
     auto &rootDeviceEnvironment = this->peekRootDeviceEnvironment();
 
     args.dcFlushEnable = getDcFlushRequired(dispatchFlags.dcFlush);
+    args.dcFlushEnable |= this->checkDcFlushRequiredForDcMitigationAndReset();
     args.notifyEnable = isUsedNotifyEnableForPostSync();
     args.tlbInvalidation |= dispatchFlags.memoryMigrationRequired;
     args.textureCacheInvalidationEnable |= dispatchFlags.textureCacheFlush;
@@ -2153,6 +2154,7 @@ void CommandStreamReceiverHw<GfxFamily>::dispatchImmediateFlushClientBufferComma
 
         PipeControlArgs args = {};
         args.dcFlushEnable = this->dcFlushSupport;
+        args.dcFlushEnable |= this->checkDcFlushRequiredForDcMitigationAndReset();
         args.notifyEnable = isUsedNotifyEnableForPostSync();
         args.workloadPartitionOffset = isMultiTileOperationEnabled();
         MemorySynchronizationCommands<GfxFamily>::addBarrierWithPostSyncOperation(

shared/test/common/libult/ult_command_stream_receiver.h

@@ -256,6 +256,11 @@ class UltCommandStreamReceiver : public CommandStreamReceiverHw<GfxFamily>, publ
         downloadAllocationCalled = true;
     }
 
+    bool checkDcFlushRequiredForDcMitigationAndReset() override {
+        this->registeredDcFlushForDcFlushMitigation = this->requiresDcFlush;
+        return BaseClass::checkDcFlushRequiredForDcMitigationAndReset();
+    }
+
     WaitStatus waitForCompletionWithTimeout(const WaitParams &params, TaskCountType taskCountToWait) override {
         std::lock_guard<std::mutex> guard(mutex);
         latestWaitForCompletionWithTimeoutTaskCount.store(taskCountToWait);
@@ -457,6 +462,7 @@ class UltCommandStreamReceiver : public CommandStreamReceiverHw<GfxFamily>, publ
 
     SubmissionStatus sendRenderStateCacheFlush() override {
         this->renderStateCacheFlushed = true;
+        this->renderStateCacheDcFlushForced = this->requiresDcFlush;
         if (callBaseSendRenderStateCacheFlush) {
             return BaseClass::sendRenderStateCacheFlush();
         }
@@ -523,6 +529,7 @@ class UltCommandStreamReceiver : public CommandStreamReceiverHw<GfxFamily>, publ
     std::atomic<uint32_t> downloadAllocationsCalledCount = 0;
 
     bool renderStateCacheFlushed = false;
+    bool renderStateCacheDcFlushForced = false;
     bool cpuCopyForHostPtrSurfaceAllowed = false;
     bool createPageTableManagerCalled = false;
     bool recordFlusheBatchBuffer = false;
@@ -551,6 +558,7 @@ class UltCommandStreamReceiver : public CommandStreamReceiverHw<GfxFamily>, publ
     bool isKmdWaitOnTaskCountAllowedValue = false;
     bool stopDirectSubmissionCalled = false;
     bool stopDirectSubmissionCalledBlocking = false;
+    bool registeredDcFlushForDcFlushMitigation = false;
 };
 
 } // namespace NEO

shared/test/unit_test/command_stream/command_stream_receiver_tests.cpp

@@ -3440,6 +3440,37 @@ HWTEST_F(CommandStreamReceiverHwTest, givenFlushPipeControlWhenFlushWithStateCac
     EXPECT_TRUE(UnitTestHelper<FamilyType>::findStateCacheFlushPipeControl(commandStreamReceiver, commandStreamReceiver.commandStream));
 }
 
+HWTEST_F(CommandStreamReceiverHwTest, givenDcFlushForcedWhenSendRenderStateCacheFlushThenExpectDcFlush) {
+    using PIPE_CONTROL = typename FamilyType::PIPE_CONTROL;
+    auto &commandStreamReceiver = pDevice->getUltCommandStreamReceiver<FamilyType>();
+
+    commandStreamReceiver.registerDcFlushForDcMitigation();
+    commandStreamReceiver.sendRenderStateCacheFlush();
+
+    HardwareParse hwParserCsr;
+    hwParserCsr.parsePipeControl = true;
+    hwParserCsr.parseCommands<FamilyType>(commandStreamReceiver.commandStream, 0);
+    hwParserCsr.findHardwareCommands<FamilyType>();
+
+    bool stateCacheFlushFound = false;
+    auto itorPipeControl = hwParserCsr.pipeControlList.begin();
+    while (itorPipeControl != hwParserCsr.pipeControlList.end()) {
+        auto pipeControl = reinterpret_cast<PIPE_CONTROL *>(*itorPipeControl);
+
+        if (pipeControl->getDcFlushEnable() &&
+            pipeControl->getRenderTargetCacheFlushEnable() &&
+            pipeControl->getStateCacheInvalidationEnable() &&
+            pipeControl->getTextureCacheInvalidationEnable() &&
+            ((commandStreamReceiver.isTlbFlushRequiredForStateCacheFlush() && pipeControl->getTlbInvalidate()) || (!commandStreamReceiver.isTlbFlushRequiredForStateCacheFlush() && !pipeControl->getTlbInvalidate()))) {
+            stateCacheFlushFound = true;
+            break;
+        }
+        itorPipeControl++;
+    }
+
+    EXPECT_TRUE(stateCacheFlushFound);
+}
+
 HWTEST2_F(CommandStreamReceiverHwTest,
           givenRayTracingAllocationPresentWhenFlushingTaskThenDispatchBtdStateCommandOnceAndResidentAlways,
           IsAtLeastXeHpCore) {