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Remove VEBOX related ftr flags

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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
This commit is contained in:
Bartosz Dunajski
2022-01-28 09:42:16 +00:00
committed by Compute-Runtime-Automation
parent 0ec6deddf1
commit fef36e058d
18 changed files with 7 additions and 98 deletions
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1
opencl/test/unit_test/gen9/bxt/linux/hw_info_config_tests.cpp
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@@ -38,7 +38,6 @@ BXTTEST_F(HwInfoConfigTestLinuxBxt, WhenConfiguringHwInfoThenConfigIsCorrect) {
EXPECT_EQ(aub_stream::ENGINE_RCS, outHwInfo.capabilityTable.defaultEngineType);
//constant sysInfo/ftr flags
EXPECT_EQ(1u, outHwInfo.gtSystemInfo.VEBoxInfo.Instances.Bits.VEBox0Enabled);
EXPECT_TRUE(outHwInfo.gtSystemInfo.VEBoxInfo.IsValid);
drm->storedDeviceID = 0x5A85;

3
opencl/test/unit_test/gen9/bxt/test_hw_info_config_bxt.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -51,7 +51,6 @@ BXTTEST_F(BxtHwInfo, givenBoolWhenCallBxtHardwareInfoSetupThenFeatureTableAndWor
EXPECT_EQ(setParamBool, featureTable.flags.ftrGpGpuMidBatchPreempt);
EXPECT_EQ(setParamBool, featureTable.flags.ftrGpGpuThreadGroupLevelPreempt);
EXPECT_EQ(setParamBool, featureTable.flags.ftrL3IACoherency);
EXPECT_EQ(setParamBool, featureTable.flags.ftrVEBOX);
EXPECT_EQ(setParamBool, featureTable.flags.ftrULT);
EXPECT_EQ(setParamBool, featureTable.flags.ftrGpGpuMidThreadLevelPreempt);
EXPECT_EQ(setParamBool, featureTable.flags.ftr3dMidBatchPreempt);

3
opencl/test/unit_test/gen9/cfl/test_hw_info_config_cfl.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -52,7 +52,6 @@ CFLTEST_F(CflHwInfo, givenBoolWhenCallCflHardwareInfoSetupThenFeatureTableAndWor
EXPECT_EQ(setParamBool, featureTable.flags.ftrGpGpuMidBatchPreempt);
EXPECT_EQ(setParamBool, featureTable.flags.ftrGpGpuThreadGroupLevelPreempt);
EXPECT_EQ(setParamBool, featureTable.flags.ftrL3IACoherency);
EXPECT_EQ(setParamBool, featureTable.flags.ftrVEBOX);
EXPECT_EQ(setParamBool, featureTable.flags.ftrGpGpuMidThreadLevelPreempt);
EXPECT_EQ(setParamBool, featureTable.flags.ftr3dMidBatchPreempt);
EXPECT_EQ(setParamBool, featureTable.flags.ftr3dObjectLevelPreempt);

3
opencl/test/unit_test/gen9/kbl/test_hw_info_config_kbl.cpp
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +54,6 @@ KBLTEST_F(KblHwInfo, givenBoolWhenCallKblHardwareInfoSetupThenFeatureTableAndWor
EXPECT_EQ(setParamBool, featureTable.flags.ftrGpGpuMidBatchPreempt);
EXPECT_EQ(setParamBool, featureTable.flags.ftrGpGpuThreadGroupLevelPreempt);
EXPECT_EQ(setParamBool, featureTable.flags.ftrL3IACoherency);
EXPECT_EQ(setParamBool, featureTable.flags.ftrVEBOX);
EXPECT_EQ(setParamBool, featureTable.flags.ftrGpGpuMidThreadLevelPreempt);
EXPECT_EQ(setParamBool, featureTable.flags.ftr3dMidBatchPreempt);
EXPECT_EQ(setParamBool, featureTable.flags.ftr3dObjectLevelPreempt);

3
opencl/test/unit_test/gen9/skl/test_hw_info_config_skl.cpp
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@@ -70,10 +70,7 @@ SKLTEST_F(SklHwInfo, givenBoolWhenCallSklHardwareInfoSetupThenFeatureTableAndWor
EXPECT_EQ(setParamBool, featureTable.flags.ftrFbc2AddressTranslation);
EXPECT_EQ(setParamBool, featureTable.flags.ftrFbcBlitterTracking);
EXPECT_EQ(setParamBool, featureTable.flags.ftrFbcCpuTracking);
EXPECT_EQ(setParamBool, featureTable.flags.ftrVEBOX);
EXPECT_EQ(setParamBool, featureTable.flags.ftrTileY);
EXPECT_EQ(false, featureTable.flags.ftrSingleVeboxSlice);
EXPECT_EQ(false, featureTable.flags.ftrVcs2);
EXPECT_EQ(setParamBool, workaroundTable.flags.waEnablePreemptionGranularityControlByUMD);
EXPECT_EQ(setParamBool, workaroundTable.flags.waSendMIFLUSHBeforeVFE);

6
opencl/test/unit_test/sku_info/sku_info_base_reference.h
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@@ -24,8 +24,6 @@ struct SkuInfoBaseReference {
refFtrTable.FtrTileY = 1;
refFtrTable.FtrDisplayYTiling = 1;
refFtrTable.FtrFbc = 1;
refFtrTable.FtrVERing = 1;
refFtrTable.FtrVcs2 = 1;
refFtrTable.FtrLCIA = 1;
refFtrTable.FtrIA32eGfxPTEs = 1;
refFtrTable.FtrWddm2GpuMmu = 1;
@@ -107,9 +105,6 @@ struct SkuInfoBaseReference {
refFtrTable.flags.ftrFbcBlitterTracking = true;
refFtrTable.flags.ftrFbcCpuTracking = true;
refFtrTable.flags.ftrVcs2 = true;
refFtrTable.flags.ftrVEBOX = true;
refFtrTable.flags.ftrSingleVeboxSlice = true;
refFtrTable.flags.ftrULT = true;
refFtrTable.flags.ftrLCIA = true;
refFtrTable.flags.ftrGttCacheInvalidation = true;
@@ -122,7 +117,6 @@ struct SkuInfoBaseReference {
refFtrTable.flags.ftrCrystalwell = true;
refFtrTable.flags.ftrLLCBypass = true;
refFtrTable.flags.ftrDisplayEngineS3d = true;
refFtrTable.flags.ftrVERing = true;
refFtrTable.flags.ftrWddm2GpuMmu = true;
refFtrTable.flags.ftrWddm2_1_64kbPages = true;