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Add PC before NP state commands

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Add pipe control before state base address, state compute
mode and state sip commands on DG2 and PVC when CCS flow is used.

Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
This commit is contained in:
Krzysztof Gibala
2022-02-04 15:43:17 +00:00
committed by Compute-Runtime-Automation
parent c1eae01ce9
commit ff7882bcbe
26 changed files with 492 additions and 78 deletions
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12
shared/source/command_stream/command_stream_receiver_hw_dg2_and_later.inl
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation
* Copyright (C) 2021-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -41,7 +41,10 @@ size_t CommandStreamReceiverHw<Family>::getCmdSizeForPerDssBackedBuffer(const Ha
size_t size = sizeof(_3DSTATE_BTD);
auto hwInfoConfig = HwInfoConfig::get(hwInfo.platform.eProductFamily);
if (hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs())) {
const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs());
std::ignore = isWARequiredOnSingleCCS;
if (isWARequiredOnMultiCCS) {
size += sizeof(typename Family::PIPE_CONTROL);
}
@@ -52,10 +55,13 @@ template <typename GfxFamily>
inline void CommandStreamReceiverHw<GfxFamily>::addPipeControlBefore3dState(LinearStream &commandStream, DispatchFlags &dispatchFlags) {
auto &hwInfo = peekHwInfo();
auto hwInfoConfig = HwInfoConfig::get(hwInfo.platform.eProductFamily);
const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs());
std::ignore = isWARequiredOnSingleCCS;
PipeControlArgs args;
args.dcFlushEnable = MemorySynchronizationCommands<GfxFamily>::getDcFlushEnable(true, hwInfo);
if (hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs()) && dispatchFlags.usePerDssBackedBuffer && !isPerDssBackedBufferSent) {
if (isWARequiredOnMultiCCS && dispatchFlags.usePerDssBackedBuffer && !isPerDssBackedBufferSent) {
DEBUG_BREAK_IF(perDssBackedBuffer == nullptr);
addPipeControlPriorToNonPipelinedStateCommand(commandStream, args);

7
shared/source/command_stream/command_stream_receiver_hw_tgllp_and_later.inl
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2021 Intel Corporation
* Copyright (C) 2019-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -20,7 +20,10 @@ void CommandStreamReceiverHw<GfxFamily>::programComputeMode(LinearStream &stream
programAdditionalPipelineSelect(stream, dispatchFlags.pipelineSelectArgs, true);
auto hwInfoConfig = HwInfoConfig::get(hwInfo.platform.eProductFamily);
if (hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs())) {
const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs());
const auto isWARequired = isWARequiredOnSingleCCS || isWARequiredOnMultiCCS;
if (isWARequired) {
PipeControlArgs args;
args.dcFlushEnable = MemorySynchronizationCommands<GfxFamily>::getDcFlushEnable(true, hwInfo);
addPipeControlPriorToNonPipelinedStateCommand(stream, args);

19
shared/source/command_stream/command_stream_receiver_hw_xehp_and_later.inl
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation
* Copyright (C) 2021-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -59,7 +59,10 @@ size_t CommandStreamReceiverHw<GfxFamily>::getCmdSizeForComputeMode() {
auto &hwInfo = peekHwInfo();
if (isComputeModeNeeded()) {
auto hwInfoConfig = HwInfoConfig::get(hwInfo.platform.eProductFamily);
if (hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs())) {
const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs());
const auto isWARequired = isWARequiredOnSingleCCS || isWARequiredOnMultiCCS;
if (isWARequired) {
size += sizeof(typename GfxFamily::PIPE_CONTROL);
}
size += sizeof(typename GfxFamily::STATE_COMPUTE_MODE);
@@ -164,8 +167,9 @@ template <typename GfxFamily>
inline void CommandStreamReceiverHw<GfxFamily>::addPipeControlPriorToNonPipelinedStateCommand(LinearStream &commandStream, PipeControlArgs args) {
auto &hwInfo = peekHwInfo();
auto hwInfoConfig = HwInfoConfig::get(hwInfo.platform.eProductFamily);
const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs());
if (hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs())) {
if (isWARequiredOnMultiCCS) {
args.textureCacheInvalidationEnable = true;
args.hdcPipelineFlush = true;
args.amfsFlushEnable = true;
@@ -175,6 +179,10 @@ inline void CommandStreamReceiverHw<GfxFamily>::addPipeControlPriorToNonPipeline
args.dcFlushEnable = false;
setPipeControlPriorToNonPipelinedStateCommandExtraProperties(args);
} else if (isWARequiredOnSingleCCS) {
args.hdcPipelineFlush = true;
setPipeControlPriorToNonPipelinedStateCommandExtraProperties(args);
}
@@ -189,9 +197,10 @@ inline void CommandStreamReceiverHw<GfxFamily>::addPipeControlBeforeStateSip(Lin
bool debuggingEnabled = device.getDebugger() != nullptr;
PipeControlArgs args;
args.dcFlushEnable = MemorySynchronizationCommands<GfxFamily>::getDcFlushEnable(true, hwInfo);
const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs());
const auto isWARequired = isWARequiredOnSingleCCS || isWARequiredOnMultiCCS;
if (hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs()) && debuggingEnabled &&
!hwHelper.isSipWANeeded(hwInfo)) {
if (isWARequired && debuggingEnabled && !hwHelper.isSipWANeeded(hwInfo)) {
addPipeControlPriorToNonPipelinedStateCommand(commandStream, args);
}
}

7
shared/source/command_stream/preemption_xehp_and_later.inl
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2021 Intel Corporation
* Copyright (C) 2018-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@@ -83,7 +83,10 @@ size_t PreemptionHelper::getRequiredStateSipCmdSize<GfxFamily>(Device &device, b
size += 2 * sizeof(typename GfxFamily::MI_LOAD_REGISTER_IMM);
} else {
auto hwInfoConfig = HwInfoConfig::get(hwInfo.platform.eProductFamily);
if (hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs)) {
const auto &[isWARequiredOnSingleCCS, isWARequiredOnMultiCCS] = hwInfoConfig->isPipeControlPriorToNonPipelinedStateCommandsWARequired(hwInfo, isRcs);
const auto isWARequired = isWARequiredOnSingleCCS || isWARequiredOnMultiCCS;
if (isWARequired) {
size += sizeof(typename GfxFamily::PIPE_CONTROL);
}
size += sizeof(typename GfxFamily::STATE_SIP);