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115 Commits

Author SHA1 Message Date
Aravind Gopalakrishnan
95c3ef28fc Enable flush task for immediate command lists 
Previously enabled for: DG2, PVC.
With this commit enabling for Gen9 onwards.

Related-To: LOCI-3379

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@intel.com>
 2022-10-28 19:17:42 +02:00
Katarzyna Cencelewska
bbd75959d5 Calculate CS timestamp based on OA timestamp and frequencies ratio 
Changes affect cores up to xe_hpg

Resolves: NEO-7346
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
 2022-10-28 16:26:53 +02:00
Compute-Runtime-Validation
fb453f5190 Revert "Enable flush task for immediate command lists" 
This reverts commit a4eb78d524.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2022-10-19 03:32:53 +02:00
Aravind Gopalakrishnan
a4eb78d524 Enable flush task for immediate command lists 
Enabling for all platforms

Related-To: LOCI-3379

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@intel.com>
 2022-10-18 17:17:05 +02:00
Compute-Runtime-Validation
5e36b1fcbf Revert "Calculate CS timestamp based on OA timestamp and frequencies ratio" 
This reverts commit 03c528382f.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2022-10-16 11:14:46 +02:00
Katarzyna Cencelewska
03c528382f Calculate CS timestamp based on OA timestamp and frequencies ratio 
Resolves: NEO-7346
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
 2022-10-13 17:41:49 +02:00
Zbigniew Zdanowicz
81f2d04f5a correct and unify programming of front end disable overdispatch property support 
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2022-09-22 13:13:38 +02:00
Naklicki, Mateusz
ec3668fc18 Add initialization method to ioctl helpers 
Signed-off-by: Naklicki, Mateusz <mateusz.naklicki@intel.com>
 2022-09-22 11:55:59 +02:00
Lukasz Jobczyk
efac290ba3 Do not use selector copy engine 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2022-09-20 21:49:00 +02:00
Michal Mrozek
3d5e34f727 Reduce the size of masks to 4. 
32 is not required.

Signed-off-by: Michal Mrozek <michal.mrozek@intel.com>
 2022-09-19 21:53:40 +02:00
Zbigniew Zdanowicz
cee520b311 simplify systolic mode code and reduce double implementation 
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2022-09-15 11:57:54 +02:00
Zbigniew Zdanowicz
647661e701 add pipeline select hw properties support flags 
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2022-09-14 11:23:44 +02:00
Zbigniew Zdanowicz
18af46296d Optimize programming of front end by selecting correct hardware 
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2022-09-02 17:41:37 +02:00
Zbigniew Zdanowicz
c3f7e40a8d Rename special pipeline select mode to systolic 
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2022-08-31 22:16:26 +02:00
Dominik Dabek
8cc0177f1c Change DG2 l1 cache policy to WB 
With compiler LSC WAs this gives better performance.

If debugger is active, policy will not be changed ie.
will be WBP.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
 2022-08-31 14:31:23 +02:00
Zbigniew Zdanowicz
816e059c66 connect hardware support with front end properties state management 
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2022-08-31 11:09:10 +02:00
Compute-Runtime-Validation
2621460e80 Revert "Change DG2 l1 cache policy to WB" 
This reverts commit a820e73dd7.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2022-08-27 08:04:19 +02:00
Dominik Dabek
a820e73dd7 Change DG2 l1 cache policy to WB 
With compiler LSC WAs this gives better performance.

If debugger is active, policy will not be changed ie.
will be WBP.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
 2022-08-26 12:58:45 +02:00
Zbigniew Zdanowicz
f656707fc0 Use hardware support flags for state compute mode state changes 
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2022-08-25 18:46:37 +02:00
Zbigniew Zdanowicz
72c3a04bfd connect hardware pipeline properties support flags to stream properties 
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2022-08-24 14:32:29 +02:00
Krystian Chmielewski
835174c076 Remove builtins duplication 
Resolves: NEO-7064

Signed-off-by: Krystian Chmielewski <krystian.chmielewski@intel.com>
 2022-08-24 07:27:46 +02:00
Compute-Runtime-Validation
54041d0f2f Revert "Add hardware support for each pipeline property" 
This reverts commit 02cf62902b.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2022-08-24 04:54:22 +02:00
Zbigniew Zdanowicz
02cf62902b Add hardware support for each pipeline property 
This change is a baseline for tight control over
when dispatch pipeline state commands and which
pipeline state properties can be changed for a
given hardware platform

Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2022-08-23 17:29:14 +02:00
Lukasz Jobczyk
b10b3ed9dd Add initial enqueue bcs split infrastructure 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2022-08-18 15:02:08 +02:00
Rafal Maziejuk
5e58104f5a Add flag to control prefetcher disabling behaviour 
Certain platforms might not require prefetcher to
be disabled in direct submission. This change
provides a way to control that behaviour.

Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
Related-To: NEO-7218
 2022-08-16 16:01:30 +02:00
Mateusz Jablonski
7b86c8da2e Add support for limiting number of CCS engines 
This commit adds support for ZEX_NUMBER_OF_CCS flag which can be used
for limiting number of CCS engines

Format is as follows:

ZEX_NUMBER_OF_CCS=RootDeviceIndex:NumberOfCCS;RootDeviceIndex:NumberOfCCS...

i.e. setting Root Device Index 0 to 4 CCS, and Root Device Index 1 To 1 CCS

ZEX_NUMBER_OF_CCS=0:4,1:1

Related-To: NEO-7195
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2022-08-10 19:38:03 +02:00
Mateusz Jablonski
3b3d40252e Revert "Limit number of CCS engines on PVC" 
This reverts commit 8f8370be32.

Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2022-08-08 18:40:24 +02:00
Mateusz Jablonski
8f8370be32 Limit number of CCS engines on PVC 
Expose only one CCS engine

Related-To: NEO-7195
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2022-08-08 14:05:35 +02:00
Kamil Kopryk
d4d54f5093 Cleanup includes 
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
 2022-07-25 09:58:38 +02:00
Milczarek, Slawomir
e768d0ed5e Add regkey to enable support for concurrent access in usm capabilities 
The new regkey is EnableUsmConcurrentAccessSupport that takes a bitmask
with usm capabilities to enable concurrent access for (bit0: host, bit1: device,
bit2: shared single-device, bit3: shared cross-device, bit4: shared system)

Related-To: NEO-6733

Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
 2022-07-06 13:58:10 +02:00
Lukasz Jobczyk
880464da77 Apply additional synchronization WA to DG2 ULLS 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2022-07-06 13:37:56 +02:00
Joshua Santosh Ranjan
e8494abbe8 Add support for ze_device_memory_ext_properties_t 
Related-To: LOCI-3099

Signed-off-by: Joshua Santosh Ranjan <joshua.santosh.ranjan@intel.com>
 2022-07-06 08:18:22 +02:00
Szymon Morek
76e023b941 Link build option with L1 cache policy helper 
Related-To: NEO-7003

Add L1CachePolicyHelper struct.
This struct is resposible for L1 cache policy
in build option, Surface State and stateless
caching. Currently default option for all
platforms is WBP (write by-pass)


Signed-off-by: Szymon Morek <szymon.morek@intel.com>
 2022-07-04 11:49:55 +02:00
Szymon Morek
5236b34629 Set L1 policy globally 
Related-To: NEO-7003

Add function to control l1 policy for both
stateless and surface state cache.


Signed-off-by: Szymon Morek <szymon.morek@intel.com>
 2022-06-27 14:57:31 +02:00
Lukasz Jobczyk
f98c6b1a8b Disable round robin engine assign on PVC 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2022-06-20 15:24:18 +02:00
Katarzyna Cencelewska
615fd4c37a Add programming of Dispatch Walk Order in COMPUTE_WALKER for xe_hpg 
- update xe_hpg generated commands
- add method isAdjustWalkOrderAvailable

Related-To: NEO-7065
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
 2022-06-17 10:42:15 +02:00
Maciej Plewka
213dc2fe24 Make CPU copy for read buffer when host ptr is write combined on DG2 
With this commit on DG2 32bit driver will check if passed host ptr for
clEnqueueReadBuffer is write combined memory. If check will be true copy
will be make on CPU.

Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2022-06-13 21:23:21 +02:00
Katarzyna Cencelewska
c59c4b2957 Add hwInfo as argument to method getSupportedDeviceFeatureCapabilities 
set proper value in method isMatrixMultiplyAccumulateSupported to be
consistent with support of extension *matrix_multiply_accumulate*

Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
 2022-06-13 15:03:43 +02:00
Filip Hazubski
d7420f1786 Add isMatrixMultiplyAccumulateSupported query to HwInfoConfig 
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2022-05-30 16:35:12 +02:00
Filip Hazubski
35d1f2e341 Add debug flag to control programming of thread arbitration policy with SCM 
Related-To: NEO-6801

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2022-05-27 11:35:41 +02:00
Daniel Chabrowski
b5495169ca Enable implicit scaling via platform config 
Related-To: NEO-6819
Signed-off-by: Daniel Chabrowski <daniel.chabrowski@intel.com>
 2022-05-26 13:57:19 +02:00
Daniel Chabrowski
7463e1970b Cleanup headers 
Make TUs and headers self-contained, remove unused headers

Signed-off-by: Daniel Chabrowski <daniel.chabrowski@intel.com>
 2022-05-18 11:42:06 +02:00
Katarzyna Cencelewska
96e1eb7467 Move variables baseDieRev and baseDieA0Masked from xe_hpc to pvc 
Pvc specific variables should be located in pvc struct

Related-To: NEO-6738
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
 2022-05-17 12:19:16 +02:00
Dominik Dabek
5dcdf53d12 Fix: enable split taskcount from wait only on dg2 
Related-To: NEO-6948

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
 2022-05-13 14:30:16 +02:00
Katarzyna Cencelewska
0b68fdbe52 Move isCooperativeEngineSupported to HwInfoConfig 
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
 2022-05-12 12:10:23 +02:00
Filip Hazubski
3413039a69 Add debug variable to control whether large grf should be programmed with SCM 
Add debug variable ForceGrfNumProgrammingWithScm.
Do not update large grf value in StreamProperties when unnecessary.

Related-To: NEO-6659

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2022-05-06 15:45:46 +02:00
Filip Hazubski
3900c9d24a Report to StreamProperties whether large grf should be programmed with SCM 
Add helper method to UnitTestHelper to query programmed grf values.

Related-To: NEO-6659

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2022-04-27 13:20:14 +02:00
Kamil Kopryk
10be59cb15 Improve isIpSamplingSupported helper 
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
Related-To: NEO-6738
 2022-04-20 17:02:20 +02:00
Bartosz Dunajski
884d729e4e Improve pat index programming on linux 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2022-04-12 08:18:20 +02:00
Kamil Kopryk
c415edaba1 Improve isGlobalFenceInCommandStreamRequired helper 
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
Related-To: NEO-6738
 2022-03-24 11:27:54 +01:00