- resources are dumped in make non resident call
- in order to dump correct data we need to be sure that GPU is done processing
- waiting needs to be unconditional to handle all cases
- remove not needed parameter to makeSurfacePackNonResident
Change-Id: Ib2b065d486cd3a5d86e599c51b24f3c958c3a10b
- new ExtendableEnum struct that serves as enum but can
be extended with values
- decrease dependencies on graphics_allocation.h header -
use forward class declaration when possible
- memoryPool indicates what kind of memory is allocated
for a given GraphicsAllocation
Change-Id: I7a707c28dc4544cc73abc5f0ed5263ba5be17452
- replace createGraphicsAllocationWithRequiredBitness with more general
methodallocateGraphicsMemoryInPreferredPool based on passed
AllocationData
- proper flags for allocation selected based on AllocationType
- remove allocateGraphicsMemory(size_t size, size_t alignment)
and use allocateGraphicsMemory(size_t size) instead where default
alignment is sufficient, otherwise use full options version:
allocateGraphicsMemory(size_t size, size_t alignment,
bool forcePin, bool uncacheable)
Change-Id: I2da891f372ee181253cb840568a61b33c0d71fc9
- makeCoherent should be called after TBX finished processing
- this is when tagAddress is updated with taskCount
makeCoherent is called from makeNonResident which is invoked just
after flush and may happen before TBX server finished processing
leading to invalid data to be read back to CPU accessible memory
- this fix adds waiting for taskCount to blocking calls for TBX CSR
before calling makeNonResident on surfaces to guarantee correct data
from TBX server is ready.
Change-Id: I498a5454e0826eec2a5413a08880af40268550e1
- add tests to check residency of allocations created
from different storage
Change-Id: I60465ef0d0dc603853d10fa27ec43eb25ff3e923
Signed-off-by: Jacek Danecki <jacek.danecki@intel.com>
When different graphics allocations are created from
the same backing storage makeResident should be called only once.
Change-Id: Ide8ab385894505fd405eef010768dbcac3b92fba
Signed-off-by: Jacek Danecki <jacek.danecki@intel.com>
- For every command buffer that we submit, pass it to gem close worker.
- Gem close worker will do asynchronous cleanup if this resource is meant to
be destroyed.
- if the resource is not meant to be destroyed we will call IOCTL wait for
this batch buffer.
- This will result in bumping up GPU clocks and better performance.
Change-Id: If9f181e411d7748573f31682e875a97c5355abe5
Refactoring in ULTs around preemption:
-refactoring ULTS to not fail with default preemption mode
-fixing ULT memory leaks observed after enabling preemption
-mocking getSipKernel in ULTs (to minimize ULT execution time)
Change-Id: I194b56173d7cb23aae94eeeca60051759c817e10
- Decission about timeout enabling and value moved out of CSR
- Timeout multiplier is no longer Linux specific
Change-Id: I6858fe2f811ef13802b95e0470e310210a9dea8b
- remove unused MemoryManagementFixture.
MemoryLeaks are tracked using MemoryLeakListener no need to duplicate
with Fixure.
MMF should be used when you need to inject memory allocation failure
Change-Id: I95bcaa7051acf540c5b015c5489ed6a6fc38ee8e
- Switch to internal heap for kernel ISA allocations.
- remove IH from various functions
- remove IHState from CSR , IH is never dirty
- ISA is no longer copied on enqueue calls.
Change-Id: I0099cf2a9ebab6192ea03a74dd35f7da963fd5a5
- read only memory cannot be used for allocation,
Oses cannot create graphics alocation for such memory
- if memory allocation fails for host_ptr passed
to enqueueWrite calls, then try doing new allocation
and copy host_ptr on cpu
Change-Id: I415a4673ae1319ea8f77e53bd8fba7489fe85218
New debug option FlattenBatchBufferForAUBDump has been added. When set it
modifies AUB dump in such way that commands from main and chained batch
buffer are dumped as single allocation. Commands from chained batch buffer are
dumped directly after commands from main batch buffer without
MI_BATCH_BUFFER_START. This feature also requires ImmediateDispatch mode which
can be forced using debug option CsrDispatchMode = 1.
Change-Id: I730760791693a748e7f4e1463ce8e7af94287b93
-If out of order flag was disabled then pipe control was not having dc flush.
-This could led to a batch buffer that doesn't end with dc flush.
-This change adds differentiation between pipe controls that may be erased and
pipe controls that are used as a part of epilogue command
Change-Id: Ic9c970c75c89ff524a0e40506eff6dd097760145
- Call waitForTaskCountAndCleanAllocationList with latest flushed task count
to reflect what was actually sent to HW.
- refactor cleanAllocationList to waitForTaskCountAndCleanAllocationList
Change-Id: I5301185c5fce212e39eb017b952b43c279559cf4
This commit as aimed to add support for batched dispatch,
but doesn't make it the default mode for AubCSR yet.
Change-Id: I4dc366ec5f01adf2c4793009da2100ba0230c60a
