Prepare cache setup and reservation logic to be extended w.r.t other
cache-levels.
Conceptually this change is like adding a switch-statement, in several
places, in which existing code makes a single (and only) case. This is
caused by splitting larger development to ease the review. Further cases
will be added in following steps. Such approach sometimes creates code
which may seem redundant but it is meant to simplify plugging following
extensions in an easy way.
Related-To: NEO-12837
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
Added a logic to check the reset status after the completion to make
sure we go through the logic at least once
Related-To: GSD-8902
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
Modified default values for disableScratch and gpuPageFault
to true and 10 respectively in drm_neo.cpp, in order to
disable scratch pages by default.
Modified to set gpuPageFault to 0 as a default value when
scratch page is not disabled.
Related-To: GSD-5673
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
when i915 reports gtt size between 47 and 48 bits we consider
it as 48 bit VA space
Related-To: GSD-8215
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
when i915 reports gtt size between 47 and 48 bits we consider
it as 48 bit VA space
Related-To: GSD-8215
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
Modified default values for disableScratch and gpuPageFault
to true and 10 respectively in drm_nep.cpp, in order to
disable scratch pages by default.
Related-To: GSD-5673
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
Modified drm_neo.h and .cpp to check when condition is greater
than and equal to instead of equal, and changed gpuFaultCheckCounter
to be atomic
Related-To: GSD-5673
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
Implemented to go through entire contexts in the process and then query
reset status to check the unexpected GPU segfault.
Added a new debug variable GpuFaultCheckThreshold to change the checking
frequency for each hang check for performance analysis.
Related-To: GSD-5673
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
Device allocation chunking only applies for multi-tile mode for implicit scaling
Related-To: NEO-9051
Signed-off-by: John Falkowski <john.falkowski@intel.com>
xe topology info to byte aligned storage
xe engine info to 2 byte aligned storage
system info to 4 byte aligned storage
all other info to 8 byte aligned storage
Related-To: NEO-9038
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
The new classes SysmanKmdInterface, SysmanKmdInterfaceI915 and
SysmanKmdInterfaceXe have been introduced.
A map is maintained in the SysmanKmdInterfaceI915 and
SysmanKmdInterfaceXe class for the sysfs file names.
The access specifier of the function getDrmVersion has been changed from
protected to public so as to use it in the sysman code. This is required
for the SysmanKmdInterface pointer to point to the
SysmanKmdInterfaceI915 and SysmanKmdInterfaceXe accordingly.
The ULTs have been added for the new sysfs file path corresponding to
the i915 and the Xe driver.
Related-To: LOCI-4399
Signed-off-by: Bari, Pratik <pratik.bari@intel.com>
The previous name "pageSize2Mb" defined in
shared/source/helpers/constant.h is inconsistent to other variable,
i.e. pageSize64k.
Furthermore, it's a bit misleading because the page size is defined in
Megabytes (MB), not in Megabits (Mb).
Related-to: NEO-7695
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
Related-to: NEO-7695
New debug keys added:
EnableBOChunking is now a mask
0 = no chunking (default).
1 = shared allocations only
2 = device allocations only
3 = shared and device allocations
MinimalAllocationSizeForChunking sets the minimum allocation
size to apply chunking. Default is 2MB.
Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
- by default ZE_ENABLE_PCI_ID_DEVICE_ORDER is disabled
- by default devices are sorted by type (discrete first), then by pci order
- when ZE_ENABLE_PCI_ID_DEVICE_ORDER is enabled, devices are sorted by pci id
Related-To: LOCI-4520
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
