Commit Graph

518 Commits

Author SHA1 Message Date
Zbigniew Zdanowicz
2e2b7a473a refactor: change additional walker fields encoder 5/n
- move compute dispatch all walker into dedicated encoder
- group same implementations into single file

Related-To: NEO-12639

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2024-11-04 13:11:59 +01:00
Marcel Skierkowski
49d999abe6 fix: remove defaultProfilingTimerResolution from RuntimeCapabilityTable
Related-To: NEO-12275
Signed-off-by: Marcel Skierkowski <marcel.skierkowski@intel.com>
2024-11-04 12:02:11 +01:00
Zbigniew Zdanowicz
32fd00e150 refactor: change additional walker fields encoder 4/n
- move post sync system fence into dedicated encoder

Related-To: NEO-12639

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2024-10-31 14:41:55 +01:00
Compute-Runtime-Validation
45a26c22dd Revert "performance: limit tlb flush scope to DG2"
This reverts commit 10d123ae3e.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2024-10-30 22:38:17 +01:00
Szymon Morek
10d123ae3e performance: limit tlb flush scope to DG2
Related-To: NEO-7116

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2024-10-30 18:27:19 +01:00
Zbigniew Zdanowicz
6f4994c269 refactor: change additional walker fields encoder 1/n
- move encoding l3 prefetch field into dedicated function

Related-To: NEO-12639

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2024-10-29 21:37:38 +01:00
Zbigniew Zdanowicz
2dccdd886a refactor: change encoder for thread group over dispatch 2/n
- bind algorithms to input arguments
- use thread group count array for regular kernels

Related-To: NEO-12639

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2024-10-29 21:20:59 +01:00
Compute-Runtime-Validation
022f9e642d Revert "refactor: change encoder for thread group over dispatch 2/n"
This reverts commit 046631767b.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2024-10-29 01:51:52 +01:00
Zbigniew Zdanowicz
046631767b refactor: change encoder for thread group over dispatch 2/n
- bind algorithms to input arguments

Related-To: NEO-12639

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2024-10-28 10:11:13 +01:00
Zbigniew Zdanowicz
bbdf1ac7b6 refactor: change encoder for thread group over dispatch 1/n
- change method name to more meaningful
- add all inputs of the algorithm as explicit function arguments
- position all implementations accordingly
- rename unit test names to fit new method name
- fix unit test to have correct initial command values
- fix unit test to have consistent input values with command values
- fix unit test to change input values together with command values

Related-To: NEO-12639

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2024-10-25 16:31:39 +02:00
Tomasz Biernacik
c982981dde feature: add number of rt stacks to capability table
Related-To: NEO-12138

Signed-off-by: Tomasz Biernacik <tomasz.biernacik@intel.com>
2024-10-17 14:46:19 +02:00
Szymon Morek
9fe53bdc60 Revert "performance: Enable direct submission on DG2 Windows"
This reverts commit 8c5be5c55a.

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2024-10-16 14:50:09 +02:00
Jack Myers
10f67bcd1a feature: finalizes 2d block load/store query
Finalized the implementation of the 2d block
load/store extension query. Namely, this adds
the extension info to the `DriverHandleImp`.

Also fixed support matrix in the current
implementation that incorrectly includes
MTL and ARL in the supported products. ULTs
and the implementation have both been changed
to match the true support matrix.

Related-To: NEO-11592
Signed-off-by: Jack Myers <jack.myers@intel.com>
2024-10-16 02:19:22 +02:00
Szymon Morek
8c5be5c55a performance: Enable direct submission on DG2 Windows
Related-To: NEO-12892

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2024-10-09 17:57:32 +02:00
Mateusz Jablonski
0168067c9c refactor: define dg2 g10 device ids in separate file
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2024-10-09 17:45:05 +02:00
Compute-Runtime-Validation
946e421f77 Revert "performance: Enable direct submission on DG2 Windows"
This reverts commit b520c64775.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2024-10-09 08:18:06 +02:00
Katarzyna Cencelewska
42ca656edb fix: change logic to calculate available thread count
don't use magic number, value depend on grf size

Related-To: HSD-18039369782
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2024-10-07 15:46:33 +02:00
Szymon Morek
b520c64775 performance: Enable direct submission on DG2 Windows
Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2024-10-07 15:38:20 +02:00
Zbigniew Zdanowicz
cb3b2134ab refactor: unify programming of preferred slm size 4/n
- remove xe hpg encode preferred slm size
- add dg2/mtl/arl release helper preferred slm array
- drop dg2 preproduction stepping values for preferred slm size
- remove obsolete product helper method

Related-To: NEO-12639

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2024-10-07 14:28:23 +02:00
Zbigniew Zdanowicz
d6016e1b91 refactor: unify programming of preferred slm size 3/n
- add shared implementation to encode preferred slm size
- add pvc release helper preferred slm array
- drop pvc preproduction steppings values for preferred slm size
- remove obsolete product helper method

Related-To: NEO-12639

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2024-10-07 12:10:27 +02:00
Zbigniew Zdanowicz
49371cb13e refactor: unify programming of preferred slm size 1/n
- rename function to reflect actual task function does

Related-To: NEO-12639

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2024-10-03 18:52:01 +02:00
Compute-Runtime-Validation
680e62d333 Revert "performance: Set dispatch all for small TG"
This reverts commit 0dc2870513.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2024-10-02 05:41:13 +02:00
Mateusz Jablonski
9db83b8231 refactor: unify isMidThreadPreemptionSupported function
mid thread preemption can be enabled only by ftrWalkerMTP flag
pre-Xe2 devices doesn't support MTP

Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2024-10-01 11:26:04 +02:00
Lukasz Jobczyk
0dc2870513 performance: Set dispatch all for small TG
Resolves: NEO-11814

Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2024-10-01 09:28:55 +02:00
Zbigniew Zdanowicz
ede98e3d2c refactor: define product helper method once
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2024-09-24 12:18:26 +02:00
Mateusz Jablonski
8e7959b243 refactor: remove not needed code
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2024-09-16 14:55:55 +02:00
Zbigniew Zdanowicz
7ce4a8adc2 performance: replace virtual calls with native class methods
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2024-09-11 11:10:40 +02:00
Jemale Lockett
efeee0018f fix: Set debugger supported on arl
Resolves: NEO-12136

Signed-off-by: Jemale Lockett <jemale.lockett@intel.com>
2024-09-05 18:23:47 +02:00
Jack Myers
c8746638c9 feature: implements 2d block load/store helpers
Implemented the product helper specializations for querying device
support for 2D block load/store operations.

The desired support matrix is both load and store is supported for PVC
and up, and unsupported forall else.

The interface for querying 2d block load/storecapabilities was
implemented in a previous PR.

Related-To: NEO-11592
Signed-off-by: Jack Myers <jack.myers@intel.com>
2024-08-09 18:42:56 +02:00
Compute-Runtime-Validation
e27efd701f Revert "fix: correct calculating max subslice space"
This reverts commit 67f2500c03.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2024-08-02 12:28:13 +02:00
Mateusz Jablonski
67f2500c03 fix: correct calculating max subslice space
computeMaxNeededSubSliceSpace is no longer needed as getHighestEnabledSubSlice
already determines maximum index from all enabled subslices

Related-To: NEO-12073
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2024-08-01 16:38:24 +02:00
Compute-Runtime-Validation
2d1b263e9a Revert "refactor: remove redundant function computeMaxNeededSubSliceSpace"
This reverts commit c0b96dcd6e.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2024-08-01 03:54:56 +02:00
Mateusz Jablonski
c0b96dcd6e refactor: remove redundant function computeMaxNeededSubSliceSpace
use GfxCoreHelper::getHighestEnabledDualSubSlice instead

Related-To: NEO-12073
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2024-07-31 14:50:13 +02:00
Zbigniew Zdanowicz
b33fe6ccf1 feature: adding flag to block dispatch implicit scaling commands
- this feature is part of making compute walker command view
- compute walker is programed for implicit scaling but not dispatched
- together with new flag, comes the refactor to reduce number of arguments

Related-To: NEO-11972

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2024-07-31 14:24:27 +02:00
Filip Hazubski
42ed8a5ba5 build: Correct logic to include xe_lpg definitions
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2024-07-30 11:39:34 +02:00
Dominik Dabek
796edfeeb5 performance: enable host usm alloc recycle
Enable on pre xe2 platforms.

Related-To: NEO-6893

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2024-07-29 14:29:08 +02:00
Bartosz Dunajski
9c2acfe5b2 refactor: pass WG count to helper method
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2024-07-24 16:05:19 +02:00
Maciej Plewka
afee8814ef refactor: get ioh alignment from static function
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2024-07-24 14:43:31 +02:00
Mateusz Jablonski
59c9930efb fix: correct subslice space calculation for dg2
respect max subslice count

Related-To: NEO-12086
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2024-07-23 18:15:33 +02:00
Dominik Dabek
9b3ccf73b7 refactor: host usm recycle
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2024-07-23 16:20:21 +02:00
Szymon Morek
39ec7facee performance: use BCS for transfers if CCS is busy
Related-To: NEO-11501

Also, if device is iGPU, don't use staging buffers
in that case.

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2024-07-22 15:36:26 +02:00
Filip Hazubski
8b99cbe48b refactor: Add getProductConfigFromHwInfoAdditionalArl helper function
Move ARL device IDs to a separate file.

Explicitly define XE_LPG platform in cmake.

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2024-07-22 09:49:42 +02:00
Szymon Morek
6a11e8a077 fix: revert changes around zero-copy
Related-To: NEO-12018

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2024-07-19 12:29:18 +02:00
Szymon Morek
33ab962121 fix: adjust compression hint usage for ocl buffers
Related-To: NEO-11989

Also, use zero-copy on lnl

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2024-07-18 18:24:48 +02:00
Maciej Plewka
85e708819a fix: Add per product cache line size property
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2024-07-18 12:47:47 +02:00
Kamil Kopryk
ac00ca60f7 test: introduce method for testing variant of walkers
This commit adds a pattern that removes the strong dependency
on the compile-time DefaultWalkerType typename in generic unit tests.

Related-To: NEO-10641
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2024-07-17 16:14:35 +02:00
Lukasz Jobczyk
a96f2ea13a performance: disable blit enqueue on LNL
Resolves: NEO-11471

Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2024-07-04 05:41:31 +02:00
Mateusz Jablonski
85289f6658 refactor: extract common code for populating ftr and wa table
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2024-06-27 13:00:15 +02:00
Mateusz Jablonski
66d4d141e1 fix: extract common logic for filling default gt system info
gt system info should be queried from KMD

Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2024-06-25 20:21:57 +02:00
Szymon Morek
8322495b53 performance: enable staging buffers copy
Related-To: NEO-11501

Enable copy through staging buffers on Windows,
limited platforms.

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2024-06-25 14:14:42 +02:00