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175 Commits

Author SHA1 Message Date
Maciej Bielski
a8779c2387 fix: report ZE_MEMORY_ACCESS_CAP_FLAG_CONCURRENT correctly 
At the moment the capability is returned only based on the value
returned by the `productHelper`, which is too liberal. The capability
must also consider the support reported by `memoryManager`. Only then
the support reported is aligned with actual logic of handling
USM-allocations.

Related-To: NEO-10040
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
 2025-01-29 00:17:38 +01:00
Mateusz Hoppe
e00da808cb feature: add logic to control secondaryContextsSupport in ProductHelper 
- product helper sets flag in GfxCoreHelper - this allows to control
secondary contexts support per product - not whole core family

Related-To: NEO-13789

Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2025-01-25 06:43:56 +01:00
Lukasz Jobczyk
c0838e1f76 fix: Apply dispatch all for small TG only on BMG 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2025-01-22 13:04:44 +01:00
Mateusz Jablonski
112abeeeef fix: don't adjust programmed per thread scratch size 
when adjusting scratch space size then adjust only allocation size

Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2025-01-10 11:35:50 +01:00
Mateusz Jablonski
a3b6c1fa6d fix: correct thread/eu ratio for scratch to Xe2 
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2025-01-09 22:42:36 +01:00
Bartosz Dunajski
5862cbcb9f refactor: add max local region size query 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2024-11-22 17:33:22 +01:00
Filip Hazubski
8797c326b6 refactor: Move isDummyBlitWaRequired function to release helper 
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2024-11-15 13:22:00 +01:00
Bartosz Dunajski
67581f57a4 refactor: unify local dispatch size query 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2024-11-15 10:00:53 +01:00
Zbigniew Zdanowicz
cb3b2134ab refactor: unify programming of preferred slm size 4/n 
- remove xe hpg encode preferred slm size
- add dg2/mtl/arl release helper preferred slm array
- drop dg2 preproduction stepping values for preferred slm size
- remove obsolete product helper method

Related-To: NEO-12639

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2024-10-07 14:28:23 +02:00
Zbigniew Zdanowicz
d6016e1b91 refactor: unify programming of preferred slm size 3/n 
- add shared implementation to encode preferred slm size
- add pvc release helper preferred slm array
- drop pvc preproduction steppings values for preferred slm size
- remove obsolete product helper method

Related-To: NEO-12639

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2024-10-07 12:10:27 +02:00
Mateusz Jablonski
bbffbd16a0 refactor: remove not needed code 
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2024-10-04 11:59:45 +02:00
Andrzej Koska
6abc5eb1a1 fix: using releaseHelper to determine MTP enablement 
Related-To: NEO-12466

Signed-off-by: Andrzej Koska <andrzej.koska@intel.com>
 2024-10-01 15:06:07 +02:00
Bartosz Dunajski
b8fd1bda36 feature: use sysInfo helper to detect memory type 
Related-To: NEO-12807

Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2024-09-30 18:19:42 +02:00
Dominik Dabek
3bd2befe74 refactor: indirect detection helpers, VC 
Allow for different required version for VC compiled kernels.
Define constant for detection disabled.

Related-To: NEO-12491

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
 2024-09-13 19:42:57 +02:00
Dominik Dabek
571d703135 refactor: indirect detection helpers 
Check indirect detection version from igc header for JIT.
Move required version to its own method.

This allows for different required versions per platform.

Related-To: NEO-12491

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
 2024-09-11 14:49:54 +02:00
Lukasz Jobczyk
a54a3bf624 performance: Optimize heap handling when mitigate dc flush 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-09-06 04:33:41 +02:00
Compute-Runtime-Validation
dc84b163b5 Revert "performance: Optimize heap handling when mitigate dc flush" 
This reverts commit 9249c5c65c.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2024-09-03 08:33:20 +02:00
Lukasz Jobczyk
9249c5c65c performance: Optimize heap handling when mitigate dc flush 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-09-02 18:12:19 +02:00
Compute-Runtime-Validation
d3f32358e9 Revert "performance: Optimize heap handling when mitigate dc flush" 
This reverts commit 452f4b1dd1.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2024-08-31 06:03:18 +02:00
Lukasz Jobczyk
452f4b1dd1 performance: Optimize heap handling when mitigate dc flush 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-08-30 10:54:54 +02:00
Compute-Runtime-Validation
63528e70a7 Revert "performance: Optimize heap handling when mitigate dc flush" 
This reverts commit 1a8149e91c.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2024-08-30 05:59:25 +02:00
Lukasz Jobczyk
1a8149e91c performance: Optimize heap handling when mitigate dc flush 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-08-29 17:03:55 +02:00
Lukasz Jobczyk
496012d82f performance: Use copy buffer rect middle builtin 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-08-28 15:32:00 +02:00
Lukasz Jobczyk
5aa5d40937 performance: Mitigate dc flush on LNL Windows 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-08-28 13:35:17 +02:00
Lukasz Jobczyk
0b848a5fdb fix: Don't use copy buffer rect middle builtin 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-08-27 12:01:58 +02:00
Compute-Runtime-Validation
ad0d6f5435 Revert "refactor: Add dc flush mitigation infrastructure" 
This reverts commit e4412e385a.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2024-08-27 02:35:06 +02:00
Lukasz Jobczyk
e4412e385a refactor: Add dc flush mitigation infrastructure 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-08-26 10:38:56 +02:00
Lukasz Jobczyk
c1a5fb089b performance: Add copy buffer rect middle builtin 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-08-22 10:30:17 +02:00
Maciej Bielski
a4060013de refactor: move CLOS-related steps from core- to product-helper 
Future HW will not support cache reservation uniquely for the whole
platform. Implementation of some functions may vary between products.

Related-To: NEO-10158
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
 2024-08-12 09:27:04 +02:00
Compute-Runtime-Validation
e27efd701f Revert "fix: correct calculating max subslice space" 
This reverts commit 67f2500c03.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2024-08-02 12:28:13 +02:00
Mateusz Jablonski
67f2500c03 fix: correct calculating max subslice space 
computeMaxNeededSubSliceSpace is no longer needed as getHighestEnabledSubSlice
already determines maximum index from all enabled subslices

Related-To: NEO-12073
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2024-08-01 16:38:24 +02:00
Compute-Runtime-Validation
2d1b263e9a Revert "refactor: remove redundant function computeMaxNeededSubSliceSpace" 
This reverts commit c0b96dcd6e.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2024-08-01 03:54:56 +02:00
Mateusz Jablonski
c0b96dcd6e refactor: remove redundant function computeMaxNeededSubSliceSpace 
use GfxCoreHelper::getHighestEnabledDualSubSlice instead

Related-To: NEO-12073
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2024-07-31 14:50:13 +02:00
Jack Myers
f5d00b2616 feature: 2d-block-load-transpose query 
Implemented device property query API for determining
support capabilities regarding 2d-block-load-tranpose
features for which not all Intel devices support.

Related-To: NEO-11592
Signed-off-by: Jack Myers <jack.myers@intel.com>
 2024-07-30 18:21:07 +02:00
Dominik Dabek
9b3ccf73b7 refactor: host usm recycle 
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
 2024-07-23 16:20:21 +02:00
Szymon Morek
39ec7facee performance: use BCS for transfers if CCS is busy 
Related-To: NEO-11501

Also, if device is iGPU, don't use staging buffers
in that case.

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
 2024-07-22 15:36:26 +02:00
Szymon Morek
6a11e8a077 fix: revert changes around zero-copy 
Related-To: NEO-12018

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
 2024-07-19 12:29:18 +02:00
Compute-Runtime-Validation
0cb2a22c55 Revert "fix: correct number of slice count in configureHwInfoDrm" 
This reverts commit b597f47a70.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2024-07-19 04:35:03 +02:00
Szymon Morek
33ab962121 fix: adjust compression hint usage for ocl buffers 
Related-To: NEO-11989

Also, use zero-copy on lnl

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
 2024-07-18 18:24:48 +02:00
Mateusz Jablonski
b597f47a70 fix: correct number of slice count in configureHwInfoDrm 
adjust slice count to proper value based on previously calculated
max slices and max subslice counts

Related-To: NEO-12073
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2024-07-18 16:54:51 +02:00
Maciej Plewka
85e708819a fix: Add per product cache line size property 
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2024-07-18 12:47:47 +02:00
Mateusz Jablonski
1d7ce005d7 refactor: extract common logic from wddm and drm product helpers 
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2024-07-17 11:03:02 +02:00
Compute-Runtime-Validation
e3053121cb Revert "refactor: extract common logic from wddm and drm product helpers" 
This reverts commit 585caab757.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2024-07-17 04:53:28 +02:00
Mateusz Jablonski
585caab757 refactor: extract common logic from wddm and drm product helpers 
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2024-07-16 11:17:18 +02:00
Mateusz Jablonski
80afda1ac9 refactor: extract common logic of setting kmd notify properties 
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2024-07-15 17:58:34 +02:00
Mateusz Jablonski
789a008470 fix: setup proper preemption surface size when forcing builtin SIP 
when getting SIP kernel from IGC, setup related surface size based on IGC data

Related-To: NEO-8188
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2024-07-15 15:56:24 +02:00
Compute-Runtime-Validation
9a6403f3bc Revert "refactor: Add dc flush mitigation infrastructure" 
This reverts commit d6076941a8.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2024-07-15 11:47:30 +02:00
Lukasz Jobczyk
d6076941a8 refactor: Add dc flush mitigation infrastructure 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-07-12 14:45:51 +02:00
Compute-Runtime-Validation
38872b7e1b Revert "refactor: Add dc flush mitigation infrastructure" 
This reverts commit 1cba900ad9.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2024-07-04 08:20:18 +02:00
Lukasz Jobczyk
a96f2ea13a performance: disable blit enqueue on LNL 
Resolves: NEO-11471

Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-07-04 05:41:31 +02:00