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55dcca993c20639f5ceefbf3e6b916fed6a668ee
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154 Commits

Author SHA1 Message Date
Filip Hazubski
55dcca993c Apply getPaddingForISAAllocation PVC implementation to PVC and later platforms 
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2022-04-27 15:55:39 +02:00
Krzysztof Gibala
9b778863b4 Store GmmHelper in Gmm class 
Store GmmHelper in Gmm class instead of GmmClientContext

Related-To: NEO-6523
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
 2022-04-27 15:45:49 +02:00
Krystian Chmielewski
ee0d183cf9 Handle legacy hasBarriers properly 
Previous change regarding NEO-6785 added encoding of number of barriers
to specific value representation depending on hardware that we program for.

In patch token format encoding of number of barriers is sent via
hasBarriers field in a token.
In zebin true number of barriers is sent via barrier_count field in
zeInfo.

To remove this discrepancy, translate encoded number of barriers into
true number of barriers in legacy format.

Resolves: NEO-6785

Signed-off-by: Krystian Chmielewski <krystian.chmielewski@intel.com>
 2022-04-12 09:44:10 +02:00
Krystian Chmielewski
2c1bfbb5b2 Encode number barriers 
When programming number of barriers use BARRIER_SIZE enumeration.
Resolves: NEO-6785

Signed-off-by: Krystian Chmielewski <krystian.chmielewski@intel.com>
 2022-04-08 10:32:23 +02:00
Filip Hazubski
d2462ff8fb Add debug flag to control ISA allocation padding 
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2022-04-04 15:12:30 +02:00
Zbigniew Zdanowicz
9858438121 Limit multiple partition count to compute command lists 
Related-To: NEO-6811

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2022-03-29 07:29:08 +02:00
Konstanty Misiak
174c27eb31 Fix CFEFusedEUDispatch debug flag 
Signed-off-by: Konstanty Misiak <konstanty.misiak@intel.com>
 2022-03-28 12:32:05 +02:00
Artur Harasimiuk
2c16ac9355 code cleanup 
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
 2022-03-21 10:51:43 +01:00
Aravind Gopalakrishnan
16f2fbbc37 [9/n] L0 immediate commandlist improvements 
Add HwInfo utility for more fine-grained flush task enablement
Related-To: LOCI-1988

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@intel.com>
 2022-02-18 19:51:28 +01:00
Aravind Gopalakrishnan
74cdd60255 [7/n] L0 immediate commandlist improvements 
Enable flushTask only for specific families for now

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@intel.com>
 2022-02-15 18:43:30 +01:00
Bartosz Dunajski
a95198521e Initial implementation of CacheSettingsHelper 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2022-02-08 16:18:06 +01:00
Bartosz Dunajski
c88fce0def Gmm construction cleanup 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2022-02-08 10:20:24 +01:00
Bartosz Dunajski
4b0d986876 Move AllocationType enum out of GraphicsAllocation class 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2022-02-04 17:49:09 +01:00
Maciej Plewka
9d8ce7aace Command container appends BB_END on cmd buffer allocation end 
When linear stream created for command container has not enough space
for command and BB_END it will program BB_END and allocate new command
buffer allocation. Pointer returned from getSpace in this case will
return storage from new command buffer allocation.

Related-To: NEO-5707

Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2022-01-31 16:15:37 +01:00
Igor Venevtsev
d9aae805c7 Do not apply L0 debugger WA (Disable L3 cache) for highest DG2 steppings 
Related-To: NEO-6320

Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
 2022-01-17 13:46:40 +01:00
Filip Hazubski
5be4d89b73 Rename function 
Rename MemorySynchronizationCommands::isDcFlushAllowed
to MemorySynchronizationCommands::getDcFlushEnable

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2021-12-30 17:03:22 +01:00
Maciej Plewka
615688336f Program all fields in SCM 
Related-To: NEO-6432

This change applies WA that always programs all fields in SCM for
gen12lp. Also for those platforms Force Non-Coherent is set to 0x2.

Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2021-12-28 16:30:47 +01:00
Mateusz Jablonski
896e01c1cb Require exact revision when getting binary builtin for PVC 
this change also implements logic for recompilation of builtin from spv in L0
in case when binary resource is not available


Related-To: NEO-6170
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-12-22 19:56:54 +01:00
Filip Hazubski
f4c151cce5 Refactor PipeControlArgs struct 
Remove struct PipeControlArgsBase

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2021-12-22 17:13:16 +01:00
Filip Hazubski
0fd685541d Add isDcFlushAllowed function to HwInfoConfig 
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2021-12-21 18:29:43 +01:00
Filip Hazubski
6d439f88bb Explicitly set dcFlushEnable value 
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2021-12-21 12:21:11 +01:00
Igor Venevtsev
fe250d99b1 Disable L3 caches for debug on ATS and DG2 
Resolves: NEO-6320

Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
 2021-12-14 13:59:09 +01:00
Bartosz Dunajski
d07c76c237 unTypedDataPortCacheFlush pipe_control helper support 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-12-09 13:00:10 +01:00
Milczarek, Slawomir
b16438de56 Add regkey to override MOCS index in surface state for scratch space 
Introduce the debug regkey OverrideMocsIndexForScratchSpace
to control MOCS index in surface state for scratch space

Related-To: NEO-6509

Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
 2021-12-07 16:27:33 +01:00
Bartosz Dunajski
dfdd3c597a Remove redundant BUFFER_COMPRESSED allocation type 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-12-07 13:35:49 +01:00
Bartosz Dunajski
68aea5bf62 Rename compression flags and helpers 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-12-03 18:09:02 +01:00
Bartosz Dunajski
995cb88bfa Improve ftr/wa flags packing 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2021-11-25 16:05:57 +01:00
Zbigniew Zdanowicz
36fd163837 Refactor pipe control post sync operations 
Related-To: NEO-6262

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2021-11-10 08:53:03 +01:00
Mateusz Jablonski
c16eb0ff84 Correct getGpgpuEngineInstances function 
dont expose bcs engine if blitter operations not supported

Related-To: NEO-6325
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-11-09 08:36:05 +01:00
Mateusz Hoppe
ee418efadf Per-thread scratch offset calculation 
Related-To: NEO-6404

Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2021-11-05 11:03:17 +01:00
Mateusz Jablonski
0cde8eb7ff Change default revision for xe_hp_sdv 
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-10-29 13:39:52 +02:00
Sebastian Luzynski
ce78bab177 Image compression checks 
Signed-off-by: Sebastian Luzynski <sebastian.jozef.luzynski@intel.com>
Related-To: NEO-6102
 2021-10-27 13:36:41 +02:00
Rafal Maziejuk
95032bb215 Move isBlitterForImagesSupported ULTs to correct files 
Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
 2021-10-18 09:46:20 +02:00
Mateusz Jablonski
7b57e87ad1 Move some mocks to shared 
- MockAllocationProperties
- MockBuiltinsLib
- MockWddmMemoryManager
- MockAubCsr


Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-10-15 09:59:47 +02:00
Mateusz Jablonski
8f81f2ae8d Cleanup MockGmm 
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-10-14 21:56:53 +02:00
Katarzyna Cencelewska
1c8a6d895a Use hwInfoConfig to check blitter support for image 
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
 2021-10-13 17:51:00 +02:00
Mateusz Jablonski
44112f8d94 Cleanup includes in shared 
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-10-13 17:02:22 +02:00
Kamil Kopryk
cfc673b77c Add compilerHwInfoConfig 
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
Related-To: NEO-6237
 2021-10-06 21:27:34 +02:00
Igor Venevtsev
da982b41be Add readSbaBuffer() interface 
Related-To: NEO-6277

Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
 2021-09-30 18:02:00 +02:00
Rafal Maziejuk
82f27e882d Refactor Gen12LP helpers 
Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
Related-To: NEO-4541
 2021-09-27 14:07:37 +02:00
Krzysztof Gibala
3b4a5c25da Move isPipeControlPriorToNonPipelinedStateCommandsWARequired to hwInfoConfig 
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
 2021-09-21 16:03:49 +02:00
Mateusz Jablonski
4caa10f76e Don't use Platform class in shared tests 
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2021-09-20 18:23:07 +02:00
Rafal Maziejuk
09ac89339e Move local memory access mode getters from HwHelper to HwInfoConfig 
Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
Related-To: NEO-4541
 2021-09-13 13:10:14 +02:00
Krzysztof Gibala
7c1ea18f74 Enable adding extra pipe control on specific platforms 
Related-To: NEO-6056
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
 2021-09-10 16:22:47 +02:00
Dominik Dabek
a204b11c8f Do not require aux translation on built ins 
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
 2021-09-10 14:38:04 +02:00
Rafal Maziejuk
bbfbf19a02 Move allowStatelessCompression from HwHelper to HwInfoConfig 
Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
Related-To: NEO-4541
 2021-09-09 11:37:47 +02:00
Rafal Maziejuk
6b062a62b8 Move allowRenderCompression function from HwHelper to HwInfoConfig 
Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
Related-To: NEO-4541
 2021-09-08 11:59:29 +02:00
Kamil Kopryk
ae88789bce Move isMidThreadPreemptionSupported helper to hwHelper 
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
 2021-09-07 20:28:55 +02:00
Rafal Maziejuk
824102dc6c Move isDisableOverdispatchAvailable function from HwHelper to HwInfoConfig 
Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
Related-To: NEO-4541
 2021-09-07 14:12:48 +02:00
Kamil Kopryk
a203cd2863 Add sip kernel as hexadecimal array header 
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
Related-To: NEO-5777
 2021-09-03 17:16:58 +02:00