Commit Graph

94 Commits

Author SHA1 Message Date
Maciej Bielski
0d0d6a300e Debugger: simplify captureStateBaseAddress()
So far captureStateBaseAddress() was a wrapper around
programSbaTrackingCommands(), doing an additional checking before
calling the latter. The checking is apparently no longer relevant, so
unify the distinction and remove part of the code which is no longer
needed.

In practice, keep the captureStateBaseAddress() while moving the body of
programSbaTrackingCommands() into it. This imposes lower diff-impact
onto the class hierarchy. Remove the second function. Simplify the
caller which had to distinct these two functions previously.

Related-To: NEO-6774
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
2022-09-13 17:08:31 +02:00
Kamil Kopryk
410fd7d909 Correct binding table prefetch
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
Related-To: NEO-6075

Binding table entry count was zeroed even when
ForceBtpPrefetchMode debug flag was enabled
2022-09-13 14:34:30 +02:00
Maciej Bielski
e1b80ba1a8 Cleanup: updateStreamProperties(), SBA tracking
Fixes found out while working on the StateBaseAddress adaptation to
StreamProperties. Removing unused parameters, improving code reuse
(further improvements come with following commits).

Related-To: NEO-6774
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
2022-09-12 17:56:28 +02:00
Zbigniew Zdanowicz
a4b9b3b837 Extend encode class for start and end hw commands
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-09-02 16:29:36 +02:00
Dominik Dabek
8cc0177f1c Change DG2 l1 cache policy to WB
With compiler LSC WAs this gives better performance.

If debugger is active, policy will not be changed ie.
will be WBP.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-08-31 14:31:23 +02:00
Compute-Runtime-Validation
2621460e80 Revert "Change DG2 l1 cache policy to WB"
This reverts commit a820e73dd7.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-08-27 08:04:19 +02:00
Dominik Dabek
a820e73dd7 Change DG2 l1 cache policy to WB
With compiler LSC WAs this gives better performance.

If debugger is active, policy will not be changed ie.
will be WBP.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-08-26 12:58:45 +02:00
Rafal Maziejuk
ed0c36117e Apply heuristics when setting TG dispatch size on XE_HPC_CORE
The default TG dispatch size can be changed
to a better value based on number of threads in TG or
currently available amount of threads on GPU.
Decision on what TG dispatch size should be are based on
implemented heuristics.

Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
Related-To: NEO-6989
2022-08-08 16:43:10 +02:00
Dunajski, Bartosz
98d776867f Add initial support for KernelArgsBuffer allocation
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-08-03 20:28:21 +02:00
Bartosz Dunajski
61b2ee45cd Use LogicalStateHelper to encode SystemMemoryFence
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-06-24 13:29:58 +02:00
Maciej Bielski
8de043b71f Stop redundant SBA programming due to global atomics
For all platforms different than XE_HP_SDV (ATS) stop considering the
`useGlobalAtomics` flag as a decisive factor for trigerring the SBA
(StateBaseAddress) programming on the HW. Only XE_HP_SDV supports such
flag.

For consistency of the implementation, keep the related logic in one
place only, that is a helper in `command_encoder` and then just reuse it
in different places (`command_stream_receiver`).

Related-To: NEO-6953
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
2022-06-08 10:39:56 +02:00
Katarzyna Cencelewska
96e1eb7467 Move variables baseDieRev and baseDieA0Masked from xe_hpc to pvc
Pvc specific variables should be located in pvc struct

Related-To: NEO-6738
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-05-17 12:19:16 +02:00
Artur Harasimiuk
d643c587b9 style: correct variable naming
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2022-05-16 15:02:15 +02:00
Bartosz Dunajski
db9c0d1103 Refactor and enable MI_MEM_FENCE programming for DirectSubmission dispatch
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-04-07 12:53:56 +02:00
Zbigniew Zdanowicz
f4407064a4 Refactor store register mem encoder to include partition parameter
Related-To: NEO-6811

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-04-06 14:00:56 +02:00
Mateusz Hoppe
beff0019d1 SBA tracking for single address space
Related-To: NEO-6539


Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
2022-04-01 15:24:11 +02:00
Filip Hazubski
3eab7009ac Move SCM related WAs logic from CSR to EncodeComputeMode
This will help with unifying the logic between APIs and GENs.

Related-To: NEO-6728

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-03-11 14:00:53 +01:00
Bartosz Dunajski
e24322f266 Debug flag to control MI_ARB_CHECK prefetcher
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-03-10 12:50:05 +01:00
Katarzyna Cencelewska
dd63f1d2f9 Add new function append3dStateBtd
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-02-03 14:42:10 +01:00
Maciej Plewka
9d8ce7aace Command container appends BB_END on cmd buffer allocation end
When linear stream created for command container has not enough space
for command and BB_END it will program BB_END and allocate new command
buffer allocation. Pointer returned from getSpace in this case will
return storage from new command buffer allocation.

Related-To: NEO-5707

Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2022-01-31 16:15:37 +01:00
Maciej Plewka
f8c104feaa Use fw declaration of IndirectHeap in CommandContainer
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2022-01-26 13:30:26 +01:00
Mateusz Jablonski
5e238dc7f1 Unify surface state programming logic related to implicit scaling
OCL image surface state programming for Xe Hp core is now reusing logic
of EncodeSurfaceState helper

Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-01-25 09:02:28 +01:00
Mateusz Jablonski
5cd76aef6a Refactor surface state programming, add enum value for default halign value
Related-To: NEO-6466
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-01-19 14:31:28 +01:00
Filip Hazubski
9a450d1b74 Pass hwInfo to appendMiFlushDw
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-22 15:22:47 +01:00
Mateusz Jablonski
66bf806018 Remove magic number from set/getBatchBufferStartAddressGraphicsaddress methods
rename methods to set/getBatchBufferStartAddress

Related-To: NEO-6466
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-12-16 19:03:01 +01:00
Zbigniew Zdanowicz
47dbe359bf Add command encoder for store data command
Related-To: NEO-6262

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-12-02 20:56:07 +01:00
Bartosz Dunajski
55959d4d1d Helper method to check if allocation is compressed
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-12-02 16:13:53 +01:00
Zbigniew Zdanowicz
76b8f6296f Move noop programming to dedicated encoder
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-11-18 10:28:56 +01:00
Zbigniew Zdanowicz
9d56939980 Refactor creation of buffer surface state 1/n
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-10-21 13:11:31 +02:00
Mateusz Jablonski
5d2d81b2d1 Use uint64_t instead of void * in indirect dispatch programming
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-10-06 18:37:36 +02:00
Mateusz Jablonski
92bf4b978a Implement implicit args for indirect dispatch
Related-To: NEO-5081
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-10-06 16:10:41 +02:00
Mateusz Jablonski
ae340ff6f5 Add L0 aub tests for indirect dispatch
Related-To: NEO-5081
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-10-05 21:05:40 +02:00
Mateusz Jablonski
b891ec2588 Correct cross thread data GPU address in indirect dispatch programming
Related-To: NEO-5081
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-10-04 14:59:41 +02:00
Zbigniew Zdanowicz
6b299a3ab0 Make partitioned post sync operations for partitioned workloads
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-09-03 20:20:29 +02:00
Bartosz Dunajski
856dee2b08 Improve Sampler programming
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-08-25 19:47:30 +02:00
Lukasz Jobczyk
dbf9198186 Flush tlb on BCS direct submission
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2021-07-30 16:26:47 +02:00
Dominik Dabek
62f89b174a Add work_dim patching to l0 kernel
Related-To: NEO-5931

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2021-07-05 20:09:20 +02:00
Mateusz Jablonski
72d124e275 add function to append params for image from buffer
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-06-24 13:33:43 +02:00
Zbigniew Zdanowicz
0e5ca243e2 Add notify enable parameter to post sync commands
Related-To: NEO-5845

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-06-17 19:22:51 +02:00
Szymon Morek
3ed0f074af Add method to set compression flag
Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2021-06-10 12:27:24 +02:00
Zbigniew Zdanowicz
4fa5041f27 Add inline directive to smallest functions
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-06-10 09:27:07 +02:00
Maciej Plewka
689ceacfe6 Fix set allocation adress in SS when offset is patched
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2021-06-08 13:05:38 +02:00
Zbigniew Zdanowicz
8f91fcdd73 Add new atomic operation
Related-To: NEO-5244

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-06-04 09:00:11 +02:00
Maciej Plewka
159404f38e Revert "Program border color once per dsh"
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2021-05-18 12:26:58 +02:00
Maciej Plewka
b943ad078f Program border color once per dsh
Related-To: NEO-4928

Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2021-04-30 13:31:58 +02:00
Milczarek, Slawomir
e5eba8be53 Add setters and getters for coherency type in render surface state
Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
2021-04-13 16:12:46 +02:00
Mateusz Jablonski
8215395401 Simplify Context method
return if context has multiple sub devices related to a given root device

Related-To: NEO-3691
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-03-30 10:22:15 +02:00
Zbigniew Zdanowicz
e36941b171 Change argument type in EncodeMemoryPrefetch class
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-03-25 18:27:07 +01:00
Bartosz Dunajski
f9197d4e0d Improve memoryPrefetch method
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-03-24 15:12:05 +01:00
Igor Venevtsev
3df6110a17 Add extra parameters to setArgStateful()
Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
2021-02-05 12:24:27 +01:00