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5e8fb19e5dcb44eef25055e2faaf47860bece9be
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234 Commits

Author SHA1 Message Date
Venevtsev, Igor
5e8fb19e5d Remove OCL Events concept from EnqueueOperation and dispatchWalker 
Change-Id: Iec55b0be673a2a40b9621212add224a33d4abc5d
 2019-02-12 08:46:18 +01:00
Kamil Diedrich
89410a6733 Add DCFlush before resolving 
Change-Id: Id5f82edc4631aa16baa55b26b8bde69f4a30572c
 2019-02-11 16:33:34 +01:00
Dunajski, Bartosz
dc181defba Use GpuAddress for TimestampPacket programming 
Change-Id: I1303605c33e2e0267a1716e12a0bfcb341fcfbd7
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-11 15:31:17 +01:00
Chodor, Jaroslaw
43856e88b5 Refactor around cache flush and command queue 
Change-Id: I277e27cbc60fbbb015c0024f171697408879ec0b
 2019-02-10 17:59:33 +01:00
Venevtsev, Igor
66e3f3c16c Remove OCL Events concept from command stream receiver 
Change-Id: I4d5a97b41efe601c92c2f3f33e9e24bb7d4fa3d2
 2019-02-08 15:02:40 +01:00
Kamil Diedrich
e1eab521e7 use release for cl-objects instead of delete 
- fix for data race in events
- modification of the addition child event

Change-Id: I6ea3a413f13f13a91d37d20d8b9fad37d0ffafb9
 2019-02-05 14:09:32 +01:00
Mateusz Jablonski
ce4a75e121 Require same allocation type when obtaining reusable allocation 
Change-Id: I829301b83a6214bcfb4fc9f2692f21ae9a002456
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-02-01 16:10:28 +01:00
Koska, Andrzej
395d053f02 Limiting the value of LWS to the value of GWS 
Change-Id: I24e89125e586ed77d396ba9e40dd039f1ab213fe
 2019-02-01 12:49:54 +01:00
Filip Hazubski
d30cc221df Update disabling caching for a resource 
Change-Id: I00eac0add01f75a1b82d04cf42652c15b776a457
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2019-02-01 10:50:21 +01:00
Chodor, Jaroslaw
7d04159f76 Refactor around cache flush 
Change-Id: Iff32af0111375f4ffc804c82e6d753d57fe94e80
 2019-01-31 22:19:06 +01:00
Venevtsev, Igor
303014582a Extend semaphore synchronization for different command stream receivers. 
Change-Id: Ic904b8c1e052adbb7b2ef82a6dec74ec69837f9f
 2019-01-30 09:33:41 +01:00
Milczarek, Slawomir
b11e0825c9 AUB capture with support for allocation dumps 
Change-Id: I90a2b75043c33af92e4557be37cde4b9699582c6
 2019-01-28 21:20:08 +01:00
Mateusz Jablonski
128bf4552f Remove debug flag ForceResourceLockOnTransferCalls 
Unlock locked resoures in freeGraphicsMemory method

Change-Id: I2baae7b7f9d8260f19a4b083849c5bf0d1a764f3
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-01-25 14:03:29 +01:00
Zdanowicz, Zbigniew
158f200476 Add HW commands const definitions 
Change-Id: If2e9d7f7f707b7b8c7bd8dbd3853ab3b6dad0c9a
 2019-01-18 12:13:25 +01:00
Stefanowski, Adam
1001f76085 Add logic for Events in multi-thread scenario 
- inc refCount when enqueue is blocked and dec after flushing

Change-Id: I9e8f8d226897124a7e51f2473939d53868bef7a2
 2019-01-14 19:45:26 +01:00
Mrozek, Michal
6c902faf0b Cleanup around Walker programming. 
- remove redundant methods.
- remove redundant parameters.
- Simplify the logic of programWalker

Change-Id: I6112bb19fd0008530f5e5510238bf42e669379b7
 2019-01-14 10:12:38 +01:00
Mrozek, Michal
15bfdc101f Refactor programWalker. 
- Pass variables computed in upper layers via args.
- declare variables prior to functions.
- Change some names for better verbosity.

Change-Id: I603b9ada1f62a08de5ac0fce177ccd840f2ce98c
 2019-01-14 09:02:14 +01:00
Pawel Wilma
14e8fdd8f8 Fix for incorrect timestamp offset calculation in event profiling info 
Change-Id: I634c29daf4734b24e4075542dc6550c531977f0a
Signed-off-by: Pawel Wilma <pawel.wilma@intel.com>
 2019-01-11 16:39:05 +01:00
Hoppe, Mateusz
64ff9d30b7 Fixes for misaligned hostPtr enqueueReadWrite 
- use getGpuAddress for BuiltinOpParams
- fix read/writeImage

Change-Id: I2e6e9a1d91871fa9f22851f31eb5a7b337b5aecc
 2019-01-11 09:14:47 +01:00
Mrozek, Michal
ef73bb8c11 Move Walker specific code to dedicated method. 
- move cache flushes after the Walker.

Change-Id: I58c5e76bad22ac42da2c466ef008ef5bf96df077
 2019-01-10 16:36:56 +01:00
Hoppe, Mateusz
3381dc258b Fix for ReadWriteBufferRect with misaligned hostPtr 
Change-Id: I026f3512e6501b7e3a4cd5b9b6e9010a0b3b8a72
 2019-01-09 14:57:25 +01:00
Hoppe, Mateusz
cbc4d349a8 Do not align down pointer passed to hostPtr allocation 
- do not align up hostPtr allocation size
- align BaseAddress programmed in SurfaceState to DWORD

Change-Id: Ic6d02e53fd13dda881f8eb845a131bffe4deb45c
 2019-01-08 21:21:34 +01:00
Napiatek, Henryk J
f7e0decf44 Improve capturing profiling timestamps 
Change-Id: I3a568afb664cae5c871e53de2c36fc8be65a4bdf
 2019-01-03 12:35:56 +01:00
Venevtsev, Igor
73a63c7689 Fix Read/WriteBuffer for unaligned offsets 
Change-Id: I08d33e80243f41174f4629c8a611e286629d2e10
 2018-12-31 14:50:07 +01:00
Kamil Diedrich
fad2f8dbd1 Change auxTranslationDirectory 
Change-Id: I5d433d340e945b799dbec25a22fd610312f00c0a
 2018-12-28 16:46:42 +01:00
Artur Harasimiuk
b5f443edc0 Revert commit cc1f4bed60. 
This reverts commit cc1f4bed60.
Revert "Revert "Use GPU instead of CPU address in programming commands
for HwTim(...)""

Change-Id: Iff122612bb46ba80bcc70b07b2609bfd5f0b9653
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
 2018-12-21 13:25:49 +01:00
Artur Harasimiuk
b2c1d68a91 Revert "Revert "Revert "Fix Read/WriteBuffer for unaligned offsets""" 
This reverts commit f6757c02a4.

Change-Id: I239528e7588dc9766b10a7ce7e517d6b2cdd6375
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
 2018-12-21 08:57:45 +01:00
Pawel Wilma
cc1f4bed60 Revert "Use GPU instead of CPU address in programming commands for HwTim(...)" 
This reverts commit 6202b2222b.
"Use GPU instead of CPU address in programming commands for HwTimeStamps"

Change-Id: I085382d95538ae41068a21c628d606039bf9cdf0
 2018-12-21 01:16:46 +01:00
Venevtsev, Igor
f6757c02a4 Revert "Revert "Fix Read/WriteBuffer for unaligned offsets"" 
This reverts commit 71f6524197.

Change-Id: I4f31fb6fa14fb5e3b8d8bf0a1745429bcdacd5af
 2018-12-20 14:16:07 +01:00
Kamil Diedrich
4b1871bf0e Add pipe control before and after buffer translation 
Change-Id: I4ee32c410e1ac2bcdb3ceae203cd461de79146a5
 2018-12-20 09:30:53 +01:00
Zdanowicz, Zbigniew
3dca095ccf Add cache flush command after WALKER command 
Change-Id: I3983dc6c0797047e17cc8189655a22a22e85892b
 2018-12-19 13:15:33 +01:00
Kamil Diedrich
b2e0195663 Change Buffer to MemObj in BufferForAuxTranslation collection 
Change-Id: Icbdb8fecaa3fd8e19e993502f59c76156fe4ad2c
 2018-12-19 08:05:51 +01:00
Piotr Fusik
e8a71132a4 Remove unnecessary casts. 
Change-Id: I2d293d065c7efa006efe7d60a625cba0c6116c86
 2018-12-18 13:42:14 +01:00
Mateusz Jablonski
8ec072d39c Simplify Memory Manager API [3/4] 
- remove method allocateGraphicsMemory(size_t size)
- pass allocation type in allocation properties
- set allocation type in allocateGraphicsMemoryInPreferredPool

Change-Id: Ia9296d0ab2f711b7d78aff615cb56b3a246b60ec
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2018-12-17 10:42:16 +01:00
Pawel Wilma
5094c630f7 Force resource locking on transfer calls 
Add debug variables to force resource locking on memory transfer calls
and to call makeResident() on mapVirtualAddress() call.

Change-Id: Ifa78d951fcb81812b10a98252bd414124dec9c74
 2018-12-14 12:25:28 +01:00
Mateusz Jablonski
74510286a1 Command Queue: Destroy timestamp packet container before releasing context 
Change-Id: I7ee492586ee178bc89c44d5d6663d3ff8fb2e778
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2018-12-14 08:26:46 +01:00
Dunajski, Bartosz
010e1a4738 VFE state programming cleanup 
Change-Id: I38fb47b00211a1d28244369ac417427ada145f61
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2018-12-13 17:44:40 +01:00
Dunajski, Bartosz
6face330fd Select RCS1 for low priority CommandQueue 
Change-Id: I86b5cb19bfbb358c5036fe4027ea82287a5f4e39
 2018-12-13 07:41:56 +01:00
Pawel Wilma
6202b2222b Use GPU instead of CPU address in programming commands for HwTimeStamps 
Change-Id: If9ab4cbd052dfa46b5d901073df4c583c2ae361f
Signed-off-by: Pawel Wilma <pawel.wilma@intel.com>
 2018-12-12 13:27:53 +01:00
Dunajski, Bartosz
d870359434 Revert "Select RCS1 for low priority CommandQueue" 
Change-Id: I8d6a4ed76917c73aad96bbb69ef42ffb7b416eb6
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2018-12-09 17:42:18 +01:00
Dunajski, Bartosz
481b83b436 Add throttle hint to unblocked enqueue path 
Change-Id: Id24e00f0f797d6245e897ba4e709d42f2ef0f5e8
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2018-12-07 14:13:31 +01:00
Dunajski, Bartosz
7f7808fb71 Select RCS1 for low priority CommandQueue 
Change-Id: I1f86b0afedb8f6e76fee896c2751a0bf196996d7
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2018-12-07 13:18:13 +01:00
Dunajski, Bartosz
52fbf6473b Minor refactor of CommandQueue class 
Change-Id: Iab64ad133fe96402d9577b64380472729f0190a8
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2018-12-06 12:45:25 +01:00
Dunajski, Bartosz
0131e66a70 Allow Device creating multiple CSRs [6/n] 
- Introduce default Engine query
- Improve Deferred Deleter usage
- Remove Tag Allocation from Device

Change-Id: Iaa88d8dc0166325acf9a157dcd2217ea408ee285
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2018-11-29 16:20:13 +01:00
Piotr Fusik
87bb6afa56 Move stamps allocators from memory manager to CSR. 
Change-Id: Ib399e462cdddad89fcc470df4c4f0f5e4591a6b2
 2018-11-27 14:52:06 +01:00
Dunajski, Bartosz
2d77b86e70 Allow Device creating multiple CSRs [5/n] 
- Move Engine type to OsContext
- Move OsContext to CSR
- Improve EngineMapper logic
- CompletionStamp cleanup

Change-Id: I935cb7169c8c48cd09837e20e3da06f6dd3437b9
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2018-11-27 14:25:04 +01:00
Pawel Wilma
71f6524197 Revert "Fix Read/WriteBuffer for unaligned offsets" 
This reverts commit 6ea863e440.

Change-Id: Ib58cfe4cffc022b1514c42131914eb2fe64fcbe0
 2018-11-27 12:35:03 +01:00
Mrozek, Michal
a1348f2f94 Remove not needed method. 
Change-Id: Id06991b374b063470a2f69daada23098c1c487d5
 2018-11-23 14:09:30 +01:00
Dunajski, Bartosz
7e72b16aa4 Add processProperties method to CommandQueue constructor 
Change-Id: If5b88de5311e3ab3973e47e70a1027cd7e0e791c
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2018-11-23 13:08:42 +01:00
Mrozek, Michal
61e7ae9280 Refactor pipe control post sync programming. 
Change-Id: I81f4840345494c6d32679e29faaff786677cb4b0
 2018-11-23 11:42:32 +01:00