Commit Graph

202 Commits

Author SHA1 Message Date
Mrozek, Michal
fca7b4e044 Remove Drm32Bit allocator.
- not used anymore.

Change-Id: Ibb7da1758feb67224ac0b172c72f45c2f1c229d9
2019-02-27 14:28:16 +01:00
Filip Hazubski
8b57d28116 clang-format: enable sorting includes
Include files are now grouped and sorted in following order:
1. Header file of the class the current file implements
2. Project files
3. Third party files
4. Standard library

Change-Id: If31af05652184169f7fee1d7ad08f1b2ed602cf0
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2019-02-27 11:50:07 +01:00
Mateusz Hoppe
d5d177dd58 Override AllocateGraphicsMemoryInDevicePool in DrmMemoryManager
Change-Id: I54da682ecb055e71af0968872ddb0ec7726c3adc
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
2019-02-27 10:05:46 +01:00
Zdunowski, Piotr
842fb5dadc [4/n] Log allocation placement.
Change-Id: I300be5f09b6ee77aa89584a6bddf4c7e57aa54f1
2019-02-26 10:21:42 +01:00
Piotr Fusik
378bd28bab Change the signature of MemoryManager::createGraphicsAllocation.
Change-Id: Ia82235ff2831fd5b3436d488a5946bb49d63ce91
2019-02-25 16:08:35 +01:00
dongwonk
b44d434a89 limited GPU range is used for external 32bit allocation
Change-Id: I494ad97fb1ddfa7b3c6b2e7cef2ae04fba571ba0
Signed-off-by: dongwonk <dongwon.kim@intel.com>
2019-02-21 16:26:49 -08:00
dongwonk
56972935ad graphic memory allocation with alignment in limited Range heap
Change-Id: Iccfb0fdc2f161e30bfdd26154110185277f176f5
Signed-off-by: dongwonk <dongwon.kim@intel.com>
2019-02-21 10:10:47 -08:00
Piotr Fusik
4ec5be0c99 Simplify code by removing AllocationOrigin.
Change-Id: Ie73cefc1ae1ee846fb9a5ef1054af01cd1867a4d
2019-02-21 16:29:05 +01:00
Mrozek, Michal
a1d4c07f45 Simplify DRM allocation constructors.
Change-Id: I2c477ce85f4748f0637451a405f7949aa829ba81
2019-02-21 12:06:01 +01:00
Mrozek, Michal
45a0ceecfb Clean drm interfaces.
- all driver allocations are using SoftPin
- remove unneeded methods.
- remove unneeded members.
- remove unneeded code paths.

Change-Id: I3369c0a4d37727210b5a26271d25537ca5218bd4
2019-02-20 16:11:19 +01:00
Dunajski, Bartosz
64fbfb21bf Improve iterating over existing CommandStreamReceivers
Change-Id: I12a10852d43c625ec5521ae91918fcb12e1a6aec
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2019-02-19 11:48:56 +01:00
dongwonk
fb993d6107 limited range and internal 32bit allocators with correct base and size
correct add 1 to the current size, gpuRange as gpuRange
only specifies the end address of the pool, not the actual
size, which causes alignment issue of all the offsets of
allocated objects. Also, a page was added in the beginning
of the limited range memory pool to avoid the base address
of it to be 0x0 that is interpreted as invalid address by
heap allocator (This makes the size reduced by pageSize)

Internal 32bit allocator is also initialized in proper way
with corrected base address.

v2: added 'givenMemoryManagerLimimedRangeAllocator' unit
    test
v3: adjust size to be freed when DrmMemoryManager instance
    is destroyed to 4GB
v4: - defined external 32bit allocator for limited Range
    allocation case.
    - softpinning object on the correct GPU address

Change-Id: Idaa0206d4133a1476cceb5a48ff8c8528742c76a
Signed-off-by: dongwonk <dongwon.kim@intel.com>
2019-02-17 19:19:52 +01:00
dongwonk
c2f5fccfd0 DrmAllocation with correct pair of cpu address and gpu address
correct mapping of cpu and gpu address in memory allocation
in case of NonSVM. Also, used only aligned address since offset
is already calculated and written to "allocationOffset".
gpuBaseAddress is programmed with 0 instead of base address of
heap because it represents GPU's address space.

v2: add allocationOffset to the aligned address in allocation
    data to point to exact starting address of buffer in two
    NonSVM allocation unit tests

Change-Id: I32ef512de64a13459b7c132672f837c5cb210ada
Signed-off-by: dongwonk <dongwon.kim@intel.com>
2019-02-15 19:03:26 +01:00
dongwonk
0240f239ad check if the whole object region is in 32Bit address space boundary
checks the address + size of buffer object to determine
whether the object is located within 32bit address space
boundary.

v2: changed end year to 2019 in ther license term
v3: added unit test for checking of flag when size of
    bo is given.
v4: two different unit tests are created to cover two
    different case separately

Change-Id: Ie2df6025fc116aca679dcfe88d858ff240278c39
Signed-off-by: dongwonk <dongwon.kim@intel.com>
2019-02-15 16:15:06 +01:00
Dunajski, Bartosz
958d931cd9 Allow to create HardwareContextController for multiple Devices
Change-Id: Ib066c937809536196182ca87359c487570cc2e89
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2019-02-14 16:00:00 +01:00
Zdanowicz, Zbigniew
8e1e874a76 Refactor headers and reorder include order
Change-Id: I6b341e2b37e569af7d741bfd7a63804c0b25a4c9
2019-02-14 13:39:01 +01:00
Piotr Fusik
f014f27370 Support the EnableLocalMemory debug variable in CSR.
Change-Id: I902b06ab0b4a3df477d12804ba74b2727d8863f6
2019-02-12 13:09:23 +01:00
Piotr Fusik
6882cf09c1 Avoid manual memory management.
Change-Id: Id29d9ec366e338d519aad5353a15a44ecf5998e4
2019-02-12 09:14:51 +01:00
Kamil Diedrich
62e56d2398 Disable L3cache when resolve argument
Change-Id: I4bb3a18d67254eef8aa4a0ce6b29401726f0b47e
2019-02-06 15:51:31 +01:00
Mateusz Jablonski
f157943610 Allocate internal allocations through preferred pool
Change-Id: Ib17431ceefc1eb72f86625e0998f679baaa7cb0d
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2019-01-30 11:18:15 +01:00
Hoppe, Mateusz
c870628d08 Rename SHARED_RESOURCE allocation type to SHARED_RESOURCE_COPY
Change-Id: Ie846450384730171304788bbb1709d7f088036a8
2019-01-28 16:20:35 +01:00
Zdunowski, Piotr
ecb204f347 [2/n] Log allocation placement.
Change-Id: I1a523b7b7ed8a3fb199e4a216b5c1dc97b83cd44
2019-01-28 12:45:22 +01:00
Hoppe, Mateusz
d7ce6ef8d1 Allocate images through preferred pool call
Change-Id: I79c9c1a0a95a8a3e26ed690530b71ef504cc7ff8
2019-01-25 09:05:25 +01:00
Piotr Fusik
40870f9c7d Retry mmap with a smaller size.
Change-Id: If8ea046af789394c1f58be9cc3a2b8100cee214a
2019-01-22 11:04:16 +01:00
Zdunowski, Piotr
75a635fdc5 [1/n] Log allocation placement.
Change-Id: I9ab61e10dcb0fcbbaf859c077a64ce7a4f2c213c
2019-01-16 16:46:50 +01:00
Mateusz Jablonski
06600f169b Define GPGPU engines per gen
Change-Id: Ie0e565d11184c5355b5bf09f5b10a567deb5c106
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2019-01-15 12:05:19 +01:00
Mrozek, Michal
9cbfa3892d Remove debug flag.
Change-Id: I013e1f27477d67fd33ba6c559dffb26d06a0db8b
2019-01-14 15:19:57 +01:00
Dunajski, Bartosz
8ae7de7b0e Create HardwareContext only when osContext is available
Change-Id: I8bcf2cb20f0e1e6b9da98b477f5be206407a7a57
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2019-01-13 15:12:07 +01:00
Piotr Fusik
30dd15144c Add debug variable to disable host ptr tracking.
Change-Id: Ifc866e06a4519e7590d40d8ad136147ecc80225d
2019-01-11 12:06:52 +01:00
Mateusz Jablonski
aee69779fa Minor renaming in a scope of multi os context allocations:
shareable -> multiOsContextCapable
resetTaskCount -> releaseUsageInOsContext
resetResidencyTaskCount -> releaseResidencyInOsContext
isUsedByContext -> isUsedByOsContext

Change-Id: If824246a0e393b962bd12f8c63d429a0fcfcda25
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2019-01-07 11:42:43 +01:00
Dunajski, Bartosz
8029639898 Pin allocation with specific DrmContextId at creation time
Change-Id: Ic132fb70b1da2cf3b7c70ab899822705adb83edc
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-12-27 09:35:58 +01:00
Kai Chen
1251ccc3c6 Allocate CPU address for Linux internal 32bit allocator base
The internal 32bit allocator sometimes need CPU address to access
or store data when it is in reduced address space scenario.

Change-Id: I6c0b3f9703ae3e124249b41ad7d81f03ad93ad17
Signed-off-by: Kai Chen <kai.chen@intel.com>
2018-12-21 07:11:48 +01:00
Mateusz Jablonski
1e011f9a08 Allow to allocate shareable graphics allocation
Change-Id: I284b03b001e5b67c344d46f34048803ef9a57314
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2018-12-20 20:14:57 +01:00
Mateusz Jablonski
c9e667d601 Simplify Memory Manager API [4/4]
- fill AllocationData in one place
- remove allocateGraphicsMemoryForSVM function
- refactor SVM manager tests

Change-Id: I6f4ecd70503da8031cced50ea98a54162fd8e5d3
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2018-12-20 09:01:33 +01:00
Hoppe, Mateusz
f6790c42cf Refactor Graphics Allocation paths for Images
Change-Id: Ifa3084b18cac95289bbceeaf3669dd31567fbd3e
2018-12-19 13:49:53 +01:00
Mrozek, Michal
d1a80db2f2 Use wrapper instead of manual restore.
Change-Id: If394797132d67c7b36a29d42cf6f6d9809baf2c2
2018-12-17 21:44:56 +01:00
Mateusz Jablonski
8ec072d39c Simplify Memory Manager API [3/4]
- remove method allocateGraphicsMemory(size_t size)
- pass allocation type in allocation properties
- set allocation type in allocateGraphicsMemoryInPreferredPool

Change-Id: Ia9296d0ab2f711b7d78aff615cb56b3a246b60ec
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2018-12-17 10:42:16 +01:00
Dunajski, Bartosz
010e1a4738 VFE state programming cleanup
Change-Id: I38fb47b00211a1d28244369ac417427ada145f61
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-12-13 17:44:40 +01:00
Dunajski, Bartosz
cfafe943eb Use different DRM Context for each OsContext on Linux
Change-Id: I543df4accdeba6c69b7dcf86d4238d12dafe92fe
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-12-12 15:08:23 +01:00
Mateusz Jablonski
a6be6533ea Simplify Memory Manager API [2/n]
- make AllocationData a protected structure
- use AllocationProperties instead of AllocationFlags
- refactor methods: allocateGraphicsMemory64kb, allocateGraphicsMemoryForSVM
- call AllocateGraphicsMemoryInPreferredPool in AllocateGraphicsMemory
  where there is no host ptr

Change-Id: Ie9ca47b1bccacd00f8486e7d1bf6fb3985e5cb12
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2018-12-11 13:12:00 +01:00
Piotr Fusik
0b839722f4 Don't store preemption mode in Wddm.
Change-Id: I6088e5fec65b6910fefb42ec9735181867c44a1b
2018-12-10 14:48:52 +01:00
Dunajski, Bartosz
f5508ed2d7 Simplify preemption control on Linux
Change-Id: Ie0896cc8950f7fbb271b710b8bb221eb41ba0445
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-12-10 13:12:16 +01:00
Mateusz Jablonski
c8748b77a0 Simplify memory manager API [1/n]
pass struct with properties to allocate graphics memory methods:
for protected methods use AllocationData
for public methods use AllocationProperties

Change-Id: Ie1c3cb6b5e330bc4adac2ca8b0bf02d30ec76065
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2018-12-06 15:09:25 +01:00
Dunajski, Bartosz
b728526c4e Allow Device creating multiple CSRs [8/n]
Use OsContextId instead of DeviceIndex for residency

Change-Id: Ib2367b32b5b3e320252d8254f1042f1c3d497068
2018-12-04 15:36:59 +01:00
Dunajski, Bartosz
1f7448425d Allow Device creating multiple CSRs [7/n]
Create and initialize all supported Engines

Change-Id: If0adf1a06b5005ef2698cebc6f1aaa6eacf562ec
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-11-30 15:48:44 +01:00
Dunajski, Bartosz
0131e66a70 Allow Device creating multiple CSRs [6/n]
- Introduce default Engine query
- Improve Deferred Deleter usage
- Remove Tag Allocation from Device

Change-Id: Iaa88d8dc0166325acf9a157dcd2217ea408ee285
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-11-29 16:20:13 +01:00
Katarzyna Cencelewska
3e800d55e6 Add support for dumping cl_cache to specified directory
Change-Id: I782ff17d0d4b17d3d26db543eb7ae222f75ff8a1
2018-11-29 13:59:26 +01:00
Maciej Dziuban
1cd59e927a Store residency status for each osContext separately
Change-Id: I2f17f68dcef6db7b596a69579a435b7ccd24e44b
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
2018-11-29 08:08:25 +01:00
Dunajski, Bartosz
b0de2a11d2 Set OsContext as reference
Change-Id: I3b682fabde9c2ddb2c33a95aef77bf6ce400a21f
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-11-27 15:32:14 +01:00
Piotr Fusik
87bb6afa56 Move stamps allocators from memory manager to CSR.
Change-Id: Ib399e462cdddad89fcc470df4c4f0f5e4591a6b2
2018-11-27 14:52:06 +01:00