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62baf28316c8e37ae1008f5663d69a9719bbd87a
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194 Commits

Author SHA1 Message Date
Jaroslaw Warchulski
62baf28316 fix: remove unnecesarry WA for DG2 compression 
Related-To: NEO-9465
Signed-off-by: Jaroslaw Warchulski <jaroslaw.warchulski@intel.com>
 2025-04-03 08:04:19 +02:00
Aravind Gopalakrishnan
3a7d7e022c fix: Add platform support for reservation on svm heap 
Related-To: GSD-10816

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@intel.com>
 2025-04-02 02:46:30 +02:00
Szymon Morek
bb10290828 fix: make misaligned user memory 2-Way coherent 
Related-To: NEO-9004

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
 2025-03-21 17:56:37 +01:00
Aravind Gopalakrishnan
724ba20e41 fix: Parse CCS mode setting for non PVC platforms 
Related-To: GSD-8785

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@intel.com>
 2025-03-19 12:47:46 +01:00
Kamil Kopryk
2e729bcb4c refactor: move isTimestampWaitSupportedForQueues to productHelper 
Related-to: NEO-13163
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
 2025-03-19 09:31:33 +01:00
Compute-Runtime-Validation
d54b74e8bd Revert "fix: Parse CCS mode setting for non PVC platforms" 
This reverts commit 5ca78dfdd1.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2025-03-17 00:30:44 +01:00
Aravind Gopalakrishnan
5ca78dfdd1 fix: Parse CCS mode setting for non PVC platforms 
Related-To: GSD-8785

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@intel.com>
 2025-03-15 01:39:51 +01:00
Compute-Runtime-Validation
0d5baa2c30 Revert "performance: Cache timestamps on CPU" 
This reverts commit 83637404bf.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2025-03-12 04:41:46 +01:00
Katarzyna Cencelewska
4890150e12 feature: add method adjustMaxThreadsPerThreadGroup to product helper 
Related-To: HSD-18028334016, HSD-14022274275

Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
 2025-03-11 15:47:57 +01:00
Lukasz Jobczyk
83637404bf performance: Cache timestamps on CPU 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2025-03-11 13:40:18 +01:00
Jaroslaw Warchulski
413194bd2a Revert "fix: do not prefer image compression on xe_lpg for linux and WSL" 
This reverts commit 8814b6ac4f.

Resolves: NEO-14286
Signed-off-by: Jaroslaw Warchulski <jaroslaw.warchulski@intel.com>
 2025-03-07 11:38:46 +01:00
Szymon Morek
82fba79d9d performance: set 1ms timeout for ulls controller on LNL and PTL 
Related-To: NEO-13843

Limit scope to Windows only.

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
 2025-03-06 09:13:58 +01:00
Kamil Kopryk
4c795027e3 refactor: add check if event L3 flush is needed 
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
 2025-03-05 18:25:29 +01:00
Jaroslaw Warchulski
8814b6ac4f fix: do not prefer image compression on xe_lpg for linux and WSL 
Related-To: HSD-18034872015
Signed-off-by: Jaroslaw Warchulski <jaroslaw.warchulski@intel.com>
 2025-02-28 14:20:57 +01:00
Fabian Zwoliński
ad968550e8 fix: separate isUsmPoolAllocatorSupported for host and device 
Related-To: NEO-12287, HSD-18041505773

Signed-off-by: Fabian Zwoliński <fabian.zwolinski@intel.com>
 2025-02-17 11:47:34 +01:00
Kamil Kopryk
c2387954e9 fix: disable 3d and media sharing support on PVC 
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
 2025-02-14 17:37:05 +01:00
Mateusz Hoppe
05977f6158 feature: add getMaxLocalSubRegionSize() to product helper 
Related-To: NEO-13954

Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2025-02-06 15:20:34 +01:00
Brandon Yates
635f69e54a fix: Configure scratch pages for debugger 
DG2 requires scratch pages on for debugger. Other platforms do not.

Related-to: NEO-13883

Signed-off-by: Brandon Yates <brandon.yates@intel.com>
 2025-01-31 06:49:49 +01:00
Fabian Zwoliński
7918b44a94 fix: apply 2MB alignment to large local memory allocations 
In this patch, we align up the allocation size to 2MB for all
allocations >= 2MB located in local memory.
2MB alignment support is defined by function:
`is2MBLocalMemAlignmentEnabled`

Related-To: NEO-12287

Signed-off-by: Fabian Zwoliński <fabian.zwolinski@intel.com>
 2025-01-30 22:09:39 +01:00
Maciej Bielski
a8779c2387 fix: report ZE_MEMORY_ACCESS_CAP_FLAG_CONCURRENT correctly 
At the moment the capability is returned only based on the value
returned by the `productHelper`, which is too liberal. The capability
must also consider the support reported by `memoryManager`. Only then
the support reported is aligned with actual logic of handling
USM-allocations.

Related-To: NEO-10040
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
 2025-01-29 00:17:38 +01:00
Mateusz Hoppe
e00da808cb feature: add logic to control secondaryContextsSupport in ProductHelper 
- product helper sets flag in GfxCoreHelper - this allows to control
secondary contexts support per product - not whole core family

Related-To: NEO-13789

Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2025-01-25 06:43:56 +01:00
Lukasz Jobczyk
c0838e1f76 fix: Apply dispatch all for small TG only on BMG 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2025-01-22 13:04:44 +01:00
Mateusz Jablonski
112abeeeef fix: don't adjust programmed per thread scratch size 
when adjusting scratch space size then adjust only allocation size

Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2025-01-10 11:35:50 +01:00
Mateusz Jablonski
a3b6c1fa6d fix: correct thread/eu ratio for scratch to Xe2 
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2025-01-09 22:42:36 +01:00
Bartosz Dunajski
5862cbcb9f refactor: add max local region size query 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2024-11-22 17:33:22 +01:00
Filip Hazubski
8797c326b6 refactor: Move isDummyBlitWaRequired function to release helper 
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2024-11-15 13:22:00 +01:00
Bartosz Dunajski
67581f57a4 refactor: unify local dispatch size query 
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2024-11-15 10:00:53 +01:00
Zbigniew Zdanowicz
cb3b2134ab refactor: unify programming of preferred slm size 4/n 
- remove xe hpg encode preferred slm size
- add dg2/mtl/arl release helper preferred slm array
- drop dg2 preproduction stepping values for preferred slm size
- remove obsolete product helper method

Related-To: NEO-12639

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2024-10-07 14:28:23 +02:00
Zbigniew Zdanowicz
d6016e1b91 refactor: unify programming of preferred slm size 3/n 
- add shared implementation to encode preferred slm size
- add pvc release helper preferred slm array
- drop pvc preproduction steppings values for preferred slm size
- remove obsolete product helper method

Related-To: NEO-12639

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2024-10-07 12:10:27 +02:00
Mateusz Jablonski
bbffbd16a0 refactor: remove not needed code 
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2024-10-04 11:59:45 +02:00
Andrzej Koska
6abc5eb1a1 fix: using releaseHelper to determine MTP enablement 
Related-To: NEO-12466

Signed-off-by: Andrzej Koska <andrzej.koska@intel.com>
 2024-10-01 15:06:07 +02:00
Bartosz Dunajski
b8fd1bda36 feature: use sysInfo helper to detect memory type 
Related-To: NEO-12807

Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
 2024-09-30 18:19:42 +02:00
Dominik Dabek
3bd2befe74 refactor: indirect detection helpers, VC 
Allow for different required version for VC compiled kernels.
Define constant for detection disabled.

Related-To: NEO-12491

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
 2024-09-13 19:42:57 +02:00
Dominik Dabek
571d703135 refactor: indirect detection helpers 
Check indirect detection version from igc header for JIT.
Move required version to its own method.

This allows for different required versions per platform.

Related-To: NEO-12491

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
 2024-09-11 14:49:54 +02:00
Lukasz Jobczyk
a54a3bf624 performance: Optimize heap handling when mitigate dc flush 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-09-06 04:33:41 +02:00
Compute-Runtime-Validation
dc84b163b5 Revert "performance: Optimize heap handling when mitigate dc flush" 
This reverts commit 9249c5c65c.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2024-09-03 08:33:20 +02:00
Lukasz Jobczyk
9249c5c65c performance: Optimize heap handling when mitigate dc flush 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-09-02 18:12:19 +02:00
Compute-Runtime-Validation
d3f32358e9 Revert "performance: Optimize heap handling when mitigate dc flush" 
This reverts commit 452f4b1dd1.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2024-08-31 06:03:18 +02:00
Lukasz Jobczyk
452f4b1dd1 performance: Optimize heap handling when mitigate dc flush 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-08-30 10:54:54 +02:00
Compute-Runtime-Validation
63528e70a7 Revert "performance: Optimize heap handling when mitigate dc flush" 
This reverts commit 1a8149e91c.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2024-08-30 05:59:25 +02:00
Lukasz Jobczyk
1a8149e91c performance: Optimize heap handling when mitigate dc flush 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-08-29 17:03:55 +02:00
Lukasz Jobczyk
496012d82f performance: Use copy buffer rect middle builtin 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-08-28 15:32:00 +02:00
Lukasz Jobczyk
5aa5d40937 performance: Mitigate dc flush on LNL Windows 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-08-28 13:35:17 +02:00
Lukasz Jobczyk
0b848a5fdb fix: Don't use copy buffer rect middle builtin 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-08-27 12:01:58 +02:00
Compute-Runtime-Validation
ad0d6f5435 Revert "refactor: Add dc flush mitigation infrastructure" 
This reverts commit e4412e385a.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2024-08-27 02:35:06 +02:00
Lukasz Jobczyk
e4412e385a refactor: Add dc flush mitigation infrastructure 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-08-26 10:38:56 +02:00
Lukasz Jobczyk
c1a5fb089b performance: Add copy buffer rect middle builtin 
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
 2024-08-22 10:30:17 +02:00
Maciej Bielski
a4060013de refactor: move CLOS-related steps from core- to product-helper 
Future HW will not support cache reservation uniquely for the whole
platform. Implementation of some functions may vary between products.

Related-To: NEO-10158
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
 2024-08-12 09:27:04 +02:00
Compute-Runtime-Validation
e27efd701f Revert "fix: correct calculating max subslice space" 
This reverts commit 67f2500c03.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
 2024-08-02 12:28:13 +02:00
Mateusz Jablonski
67f2500c03 fix: correct calculating max subslice space 
computeMaxNeededSubSliceSpace is no longer needed as getHighestEnabledSubSlice
already determines maximum index from all enabled subslices

Related-To: NEO-12073
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2024-08-01 16:38:24 +02:00