Commit Graph

10 Commits

Author SHA1 Message Date
Maciej Bielski
a7c46b8213 feature: support L2 cache reservation
Related-To: NEO-12837
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
2025-03-17 19:41:55 +01:00
Filip Hazubski
6b6202446b fix: Add asserts to ensure NonCopyable and NonMovable 3/n
Related-To: NEO-14068

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2025-02-18 17:16:03 +01:00
Maciej Bielski
6924a48ca6 refactor: prepare CLOS logic for extension
Prepare cache setup and reservation logic to be extended w.r.t other
cache-levels.

Conceptually this change is like adding a switch-statement, in several
places, in which existing code makes a single (and only) case. This is
caused by splitting larger development to ease the review. Further cases
will be added in following steps. Such approach sometimes creates code
which may seem redundant but it is meant to simplify plugging following
extensions in an easy way.

Related-To: NEO-12837
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
2025-02-17 10:43:08 +01:00
Maciej Bielski
c9726dbb10 refactor: simplify tracking CacheRegion reservations
Leverage features of the mechanism to simplify implementation:
- The maximum number of possible cache-region reservations is a small
value known at compile-time
- Each reservation is unique (described by `CacheRegion`) so can have
a dedicated entry with either zero (free) or non-zero (reserved) value

So, there is no need for a dynamic collection (unordered_map here) to
keep track of reservations. A simple array is enough for that purpose.

Also, add some helper-code to enable array-indexing with the values of
`CacheRegion` enum.

Related-To: NEO-12837
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
2024-12-09 16:50:28 +01:00
Maciej Bielski
790bb84841 refactor: decouple ClosCacheReservation from Drm
The dependency towards `Drm` is unnecessary and only makes testing more
difficult. Instead, dependency towards `IoctlHelper` alone only is
sufficient.

Related-To: NEO-10158
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
2024-07-31 10:38:35 +02:00
Bartosz Dunajski
884d729e4e Improve pat index programming on linux
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-04-12 08:18:20 +02:00
Daniel Chabrowski
4d4ccfd128 Remove cache info base class
There is only one implementation of said class and we don't
even adhere to the interface it provides.

Signed-off-by: Daniel Chabrowski <daniel.chabrowski@intel.com>
2022-04-07 18:15:57 +02:00
Milczarek, Slawomir
afa45bd9e7 Add support for mem advise to set cache policy in buffer object
Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
2021-10-07 22:16:58 +02:00
Slawomir Milczarek
ef3678e005 Add checks for default cache policy
Signed-off-by: Slawomir Milczarek <slawomir.milczarek@intel.com>
2021-02-19 14:16:14 +01:00
Slawomir Milczarek
d399613f25 Add support for L3 cache information
Signed-off-by: Slawomir Milczarek <slawomir.milczarek@intel.com>
2021-02-05 10:28:02 +01:00