Commit Graph

163 Commits

Author SHA1 Message Date
Warchulski, Jaroslaw
be647d42d9 Cleanup includes 12
Related-To: NEO-5548
Signed-off-by: Warchulski, Jaroslaw <jaroslaw.warchulski@intel.com>
2022-12-07 13:14:15 +01:00
Dominik Dabek
7d7ecd50b6 DG2, Enable resolving dependecies by pipecontrol
Enable resolving dependencies by pipecontrol on same CSR, IOQ on DG2 by
default.

Related-To: NEO-7321

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-12-07 12:49:52 +01:00
Dominik Dabek
4adba15dbb Update for resolving dependencies by pipecontrol
Flag ResolveDependenciesViaPipeControls now removes only same csr
dependencies. Still enables pipe controls.

Works through hwInfoConfig method isResolveDependenciesByPipeControlsSupported

Related-To: NEO-7321

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-12-05 15:48:49 +01:00
Kamil Kopryk
785b9eeece Rename CompilerHwInfoConfig -> CompilerProductHelper
Related-To: NEO-6853
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2022-12-05 11:25:49 +01:00
Warchulski, Jaroslaw
dfa65bd358 Cleanup includes 9
Related-to: NEO-5548
Signed-off-by: Warchulski, Jaroslaw <jaroslaw.warchulski@intel.com>
2022-11-30 14:48:50 +01:00
Szymon Morek
bb55d2259e Enable CPU memcpy on DG2
Resolves: NEO-7553

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2022-11-29 12:24:18 +01:00
Warchulski, Jaroslaw
5e2efc4013 Cleanup includes 8
Related-To: NEO-5548
Signed-off-by: Warchulski, Jaroslaw <jaroslaw.warchulski@intel.com>
2022-11-28 12:18:06 +01:00
Zbigniew Zdanowicz
cd17c1e9d2 Add state properties for state base address command
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-11-24 00:33:10 +01:00
Mateusz Jablonski
bb308c04ed Refactor aubstream include interface
set include path to third_party/aub_stream
rename third_party/aub_stream/headers -> third_party/aub_stream/aubstream

Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-11-23 10:30:13 +01:00
Mateusz Jablonski
0b3582a93b Update aubstream interface: use product family from aubstream
don't build aub tests when aubstream is not available
use only mock aub manager in ULTs

Related-To: NEO-4446
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-11-21 15:30:09 +01:00
Warchulski, Jaroslaw
1c03361273 Cleanup includes 6
Related-To: NEO-5548
Signed-off-by: Warchulski, Jaroslaw <jaroslaw.warchulski@intel.com>
2022-11-21 12:02:14 +01:00
Mateusz Jablonski
610480b5aa Refactor: Dont include os_agnostic_hw_info_config_* files in namespace NEO
use namespace NEO explicitly in these files

Related-To: NEO-4446
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-11-16 13:32:19 +01:00
Andrzej Koska
f27dcbfb85 Unify RCS exposure
The goal is to standardize RCS exposure for all types of hardware

Related-To: NEO-7224
Signed-off-by: Andrzej Koska <andrzej.koska@intel.com>
2022-11-14 13:12:08 +01:00
Andrzej Koska
9aeb0116d7 Do not expose RCS on DG2
The RCS is no longer exposed under windows and linux on DG2

Related-To: NEO-7224
Signed-off-by: Andrzej Koska <andrzej.koska@intel.com>
2022-11-10 18:02:10 +01:00
Kamil Kopryk
c82038565e Unify isTimestampWaitSupportedForEvents helper function
Related-To: NEO-6853
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>

No need to keep isTimestampWaitSupportedForEvents function
in hwHelper and in hwInfoConfig helper, move it to hwInfoConfig instead.
2022-11-10 15:24:14 +01:00
Warchulski, Jaroslaw
e4d10e5460 Cleanup includes 4
Related-To: NEO-5548
Signed-off-by: Warchulski, Jaroslaw <jaroslaw.warchulski@intel.com>
2022-11-10 14:22:18 +01:00
Joshua Santosh Ranjan
6a2e016d7f Add support for UUID
Related-To: LOCI-3304

Signed-off-by: Joshua Santosh Ranjan <joshua.santosh.ranjan@intel.com>
2022-11-09 12:29:32 +01:00
Dunajski, Bartosz
918d7b1da4 Helper for MI_SET_PREDICATE programming
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-11-08 14:20:01 +01:00
Kamil Kopryk
eafea5e2fe Move HwInfoConfig ownership to RootDeviceEnvironment 1/n
Related-To: NEO-6853
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>

- Added HwInfoConfig getter in RootDeviceEnvironment,
which temporarily takes HwInfoConfig from the global array
- use HwInfoConfig from RootDeviceEnvironment to
call ConfigureHardwareCustom function
- Added getHwInfoConfig in DeviceFixture
- ConfigureHardwareCustom function and few others changed to const
- Small code cleanup
2022-11-08 10:52:08 +01:00
Warchulski, Jaroslaw
ef95bfb45e Cleanup includes
Related-To: NEO-5548
Signed-off-by: Warchulski, Jaroslaw <jaroslaw.warchulski@intel.com>
2022-11-04 18:04:13 +01:00
Compute-Runtime-Validation
308f54e4eb Revert "Apply basic WA only for multi CCS on DG2"
This reverts commit 5a2f00d295.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-10-31 03:27:29 +01:00
Katarzyna Cencelewska
bbd75959d5 Calculate CS timestamp based on OA timestamp and frequencies ratio
Changes affect cores up to xe_hpg

Resolves: NEO-7346
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-10-28 16:26:53 +02:00
Lukasz Jobczyk
5a2f00d295 Apply basic WA only for multi CCS on DG2
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2022-10-28 11:34:52 +02:00
Dominik Dabek
6cf8b4daca Correct tg dispatch size heuristic
Multiply available thread count by tile count
if implicit scaling is used

Related-To: NEO-6989

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-10-27 17:24:53 +02:00
Dunajski, Bartosz
7ff37cd5fd Ftr/WA flags cleanup
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-10-26 12:11:31 +02:00
Compute-Runtime-Validation
5e36b1fcbf Revert "Calculate CS timestamp based on OA timestamp and frequencies ratio"
This reverts commit 03c528382f.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-10-16 11:14:46 +02:00
Katarzyna Cencelewska
03c528382f Calculate CS timestamp based on OA timestamp and frequencies ratio
Resolves: NEO-7346
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-10-13 17:41:49 +02:00
Yates, Brandon
71bef6094d Use max enabled slice in debugger thread mapping
Signed-off-by: Yates, Brandon <brandon.yates@intel.com>
2022-10-03 18:11:50 +02:00
Maciej Bielski
56cb1f757b programStateBaseAddress: improve code reuse
Another step towards cleaner callers of
StateBaseAddressHelper<>::programStateBaseAddress.

Export programming state base address into a separate function to
improve code reuse and reduce copy-pasted fragments, which make code
modifications or maintenance more and more difficult over time. Use
specialization for gen-specific variations.

Related-To: NEO-6774
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
2022-09-21 11:54:57 +02:00
Mateusz Jablonski
cfe51ff2ba Remove not used isSimulation functions
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-09-20 11:01:55 +02:00
Zbigniew Zdanowicz
cee520b311 simplify systolic mode code and reduce double implementation
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-09-15 11:57:54 +02:00
Zbigniew Zdanowicz
647661e701 add pipeline select hw properties support flags
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-09-14 11:23:44 +02:00
Compute-Runtime-Validation
c2cd1a2698 Revert "Do not expose RCS on DG2"
This reverts commit 69c9a4e86c.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-09-12 01:31:19 +02:00
Andrzej Koska
69c9a4e86c Do not expose RCS on DG2
The RCS is no longer exposed under windows and linux on DG2

Related-To: NEO-7224
Signed-off-by: Andrzej Koska <andrzej.koska@intel.com>
2022-09-09 13:20:31 +02:00
Dominik Dabek
a72213943e Change DG2 l1 cache policy to WB
With compiler LSC WAs this gives better performance.

If debugger is active, policy will not be changed ie.
will be WBP.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-09-08 12:14:52 +02:00
Dominik Dabek
485ba234f3 Revert change DG2 l1 cache policy
This reverts cache policy back to WBP,
due to functional regressions

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-09-02 12:02:14 +02:00
Zbigniew Zdanowicz
c3f7e40a8d Rename special pipeline select mode to systolic
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-31 22:16:26 +02:00
Dominik Dabek
8cc0177f1c Change DG2 l1 cache policy to WB
With compiler LSC WAs this gives better performance.

If debugger is active, policy will not be changed ie.
will be WBP.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-08-31 14:31:23 +02:00
Maciej Plewka
fe73c06b59 Disable overdispatch for specific Arc devices
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2022-08-31 12:09:54 +02:00
Zbigniew Zdanowicz
816e059c66 connect hardware support with front end properties state management
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-31 11:09:10 +02:00
Compute-Runtime-Validation
2621460e80 Revert "Change DG2 l1 cache policy to WB"
This reverts commit a820e73dd7.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-08-27 08:04:19 +02:00
Patryk Wrobel
c0342a0ab5 Optimize binaries' size by adjusting linkage of constants in headers
When header is included for the first time in translation unit,
then preprocessor simply copy-pastes its content. If we define a
constant in a header file and this constant has internal linkage
then each and every translation unit, which includes this header
will have its own copy of this constant.

C++17 introduces inline variables, which are meant to allow creation
of variables in header files, which do not cause multiple instances.

The inline variable has a single instance when:
- constexpr is used without static (constexpr implicitly implies inline)
- inline is used without static
- inline const is used without static (const does not imply internal linkage
when used with inline)

Signed-off-by: Patryk Wrobel <patryk.wrobel@intel.com>
2022-08-26 22:52:04 +02:00
Dominik Dabek
a820e73dd7 Change DG2 l1 cache policy to WB
With compiler LSC WAs this gives better performance.

If debugger is active, policy will not be changed ie.
will be WBP.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-08-26 12:58:45 +02:00
Naklicki, Mateusz
98500ee653 Allow overriding hw config on aub/tbx mode
Signed-off-by: Naklicki, Mateusz <mateusz.naklicki@intel.com>
2022-08-25 10:54:42 +02:00
Zbigniew Zdanowicz
72c3a04bfd connect hardware pipeline properties support flags to stream properties
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-24 14:32:29 +02:00
Compute-Runtime-Validation
54041d0f2f Revert "Add hardware support for each pipeline property"
This reverts commit 02cf62902b.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-08-24 04:54:22 +02:00
Zbigniew Zdanowicz
02cf62902b Add hardware support for each pipeline property
This change is a baseline for tight control over
when dispatch pipeline state commands and which
pipeline state properties can be changed for a
given hardware platform

Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-23 17:29:14 +02:00
Zbigniew Zdanowicz
6c38b36251 Unify getting state base address command space from command buffer
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-17 11:49:02 +02:00
Rafal Maziejuk
ed0c36117e Apply heuristics when setting TG dispatch size on XE_HPC_CORE
The default TG dispatch size can be changed
to a better value based on number of threads in TG or
currently available amount of threads on GPU.
Decision on what TG dispatch size should be are based on
implemented heuristics.

Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
Related-To: NEO-6989
2022-08-08 16:43:10 +02:00
Dunajski, Bartosz
98d776867f Add initial support for KernelArgsBuffer allocation
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-08-03 20:28:21 +02:00