Commit Graph

59 Commits

Author SHA1 Message Date
Kamil Kopryk
410fd7d909 Correct binding table prefetch
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
Related-To: NEO-6075

Binding table entry count was zeroed even when
ForceBtpPrefetchMode debug flag was enabled
2022-09-13 14:34:30 +02:00
Dominik Dabek
8cc0177f1c Change DG2 l1 cache policy to WB
With compiler LSC WAs this gives better performance.

If debugger is active, policy will not be changed ie.
will be WBP.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-08-31 14:31:23 +02:00
Compute-Runtime-Validation
2621460e80 Revert "Change DG2 l1 cache policy to WB"
This reverts commit a820e73dd7.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-08-27 08:04:19 +02:00
Naklicki, Mateusz
54042a191e Implement PauseOnEnqueue for L0
Allow pausing execution before and after enqueuing kernel
using the PauseOnEnqueue and PauseOnGpuMode debug flags.

Related-To: NEO-6570
Signed-off-by: Naklicki, Mateusz <mateusz.naklicki@intel.com>
2022-08-26 14:48:58 +02:00
Dominik Dabek
a820e73dd7 Change DG2 l1 cache policy to WB
With compiler LSC WAs this gives better performance.

If debugger is active, policy will not be changed ie.
will be WBP.

Related-To: NEO-7003

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-08-26 12:58:45 +02:00
Zbigniew Zdanowicz
0011368775 Add parameter to set surface state base address value
This change introduces capability to set surface state base address
when surface state heap or global base address are not available

Related-To: NEO-7187

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-18 15:36:43 +02:00
Zbigniew Zdanowicz
acac5ea0d5 Use correct engine group type when programming state base address
Command lists and their helper classes should use engine group type
assigned to the particular command list to check if it is RCS group
and not use default CSR class assigned to the device, since default
and current in command list might be different.

Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-17 20:38:23 +02:00
Zbigniew Zdanowicz
6c38b36251 Unify getting state base address command space from command buffer
Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-17 11:49:02 +02:00
Zbigniew Zdanowicz
ceb9d81f87 Add struct argument for input/output in StateBaseAddressHelper
This refactor makes future interface changes easier

Related-To: NEO-5019

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-17 10:28:49 +02:00
Rafal Maziejuk
ed0c36117e Apply heuristics when setting TG dispatch size on XE_HPC_CORE
The default TG dispatch size can be changed
to a better value based on number of threads in TG or
currently available amount of threads on GPU.
Decision on what TG dispatch size should be are based on
implemented heuristics.

Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
Related-To: NEO-6989
2022-08-08 16:43:10 +02:00
Dunajski, Bartosz
98d776867f Add initial support for KernelArgsBuffer allocation
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-08-03 20:28:21 +02:00
Dunajski, Bartosz
c200c6e2dd Pass LSH to EncodeDispatchKernel
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-07-26 15:37:28 +02:00
Dunajski, Bartosz
a3903c385e Remove HW types from synchronization interface
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-07-25 13:59:26 +02:00
Jim Snow
f4879f064f Allocate per-tile RTDispatchGlobals, handle ray tracing patch tokens.
Related-to: NEO-6711

Signed-off-by: Raiyan Latif <raiyan.latif@intel.com>
2022-07-22 06:29:29 +02:00
Bartosz Dunajski
76d905b1f2 Pass LogicalStateHelper to SBA helper
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-07-01 14:52:20 +02:00
Katarzyna Cencelewska
615fd4c37a Add programming of Dispatch Walk Order in COMPUTE_WALKER for xe_hpg
- update xe_hpg generated commands
- add method isAdjustWalkOrderAvailable

Related-To: NEO-7065
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-06-17 10:42:15 +02:00
Zbigniew Zdanowicz
f5b1a0e45b Use internal event object in command lists methods
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-06-14 21:23:43 +02:00
Katarzyna Cencelewska
b2021498e2 Create method adjustWalkOrder
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-05-27 16:05:31 +02:00
Zbigniew Zdanowicz
8431234845 Change interface to method programing additional fields of command
Related-To: NEO-6959

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-05-26 21:32:59 +02:00
Artur Harasimiuk
a6490062a9 fix code issues reported by clang 14
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2022-04-29 10:43:34 +02:00
Filip Hazubski
3900c9d24a Report to StreamProperties whether large grf should be programmed with SCM
Add helper method to UnitTestHelper to query programmed grf values.

Related-To: NEO-6659

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-04-27 13:20:14 +02:00
Filip Hazubski
944319b3d9 Correct media compression format for blitter operations on planar images
Set most significant bit for chroma planes.
Move common logic to helper function.

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-04-22 17:02:16 +02:00
Mateusz Hoppe
5911515ed0 Refactor debugger code
- helper sets all SbaAddresses for debugger in
EncodeStateBaseAddress<GfxFamily>::setSbaAddressesForDebugger()
- change DebuggerL0::captureStateBaseAddress() to take
LinearStream
- move getSbaTrackingCommandsSize() to Debugger class

Related-To: NEO-6845

Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
2022-04-21 13:04:34 +02:00
Zbigniew Zdanowicz
fd45ac133d Unify append calls
Related-To: NEO-6242

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-04-07 10:18:55 +02:00
Mateusz Hoppe
4374197c9d Fixes for bindless configuration
- enhance ults code, do not inject memory manager
- fix some issues related to bindless global heap

Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
2022-04-01 15:08:43 +02:00
Mateusz Jablonski
e11eb46bff Unify logic for programming mocs in post sync struct
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-03-25 17:01:51 +01:00
Krzysztof Gibala
ebc006ad53 Move SBA related WAs logic from CSR to EncodeWA
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
2022-03-24 12:24:56 +01:00
Filip Hazubski
cd95572443 Reuse common logic of programming SCM fields for gen 9 and gen 11
Logic related to programming non coherent and thread arbitration policy for
gens 9 and 11 has been moved to EncodeComputeMode object, where similar
logic for gens gen12lp and newer is located.

Functions PreambleHelper::programThreadArbitration and
PreambleHelper::getThreadArbitrationCommandsSize have been removed.

Redundant setForceNonCoherent call has been removed from XE HPG

Related-To: NEO-6728

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-03-16 10:04:32 +01:00
Filip Hazubski
3eab7009ac Move SCM related WAs logic from CSR to EncodeComputeMode
This will help with unifying the logic between APIs and GENs.

Related-To: NEO-6728

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-03-11 14:00:53 +01:00
Bartosz Dunajski
e24322f266 Debug flag to control MI_ARB_CHECK prefetcher
Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-03-10 12:50:05 +01:00
Mateusz Jablonski
82e3b10c5a Fix typo
Related-To: NEO-5081
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-02-25 18:10:41 +01:00
Mateusz Jablonski
a2386ad216 Correct programming of implicit args on pre-XeHp platforms
On pre-XeHp platforms implicit args aren't at the beginning of indirect data,
GPU address of implicit args buffer is programmed within cross thread data

Related-To: NEO-5081, IGC-4710
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-02-24 20:52:04 +01:00
Mateusz Jablonski
ea6f089e17 Unify implicit args programming across APIs
Related-To: NEO-5081
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-02-23 11:52:47 +01:00
Mateusz Jablonski
b697d75695 Correct dimension order in local ids generated for implicit args
when local ids are generated by HW, use same dim order for runtime generation
move common logic to separated file

Related-To: NEO-5081
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-02-04 12:46:59 +01:00
Maciej Plewka
9d8ce7aace Command container appends BB_END on cmd buffer allocation end
When linear stream created for command container has not enough space
for command and BB_END it will program BB_END and allocate new command
buffer allocation. Pointer returned from getSpace in this case will
return storage from new command buffer allocation.

Related-To: NEO-5707

Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2022-01-31 16:15:37 +01:00
Mateusz Jablonski
fbc0666d1b Move setGrfInfo from HardwareCommandsHelper to EncodeDispatchKernel
unify grf info programming across APIs

Related-To: NEO-6466
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-01-20 15:42:06 +01:00
Zbigniew Zdanowicz
b78bb26cbf Refactor partitioning of state base address
Related-To: NEO-6589

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-01-14 19:06:24 +01:00
Zbigniew Zdanowicz
9c4f05387b Refactor partitioning of dispatched kernels
Related-To: NEO-6589

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-01-13 22:54:07 +01:00
Zbigniew Zdanowicz
9785ab7828 Refactor encode dispatch kernel class interface
Related-To: NEO-6589

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-01-13 12:08:38 +01:00
Filip Hazubski
5be4d89b73 Rename function
Rename MemorySynchronizationCommands::isDcFlushAllowed
to MemorySynchronizationCommands::getDcFlushEnable

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-30 17:03:22 +01:00
Filip Hazubski
f4c151cce5 Refactor PipeControlArgs struct
Remove struct PipeControlArgsBase

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-22 17:13:16 +01:00
Filip Hazubski
9a450d1b74 Pass hwInfo to appendMiFlushDw
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-22 15:22:47 +01:00
Filip Hazubski
0fd685541d Add isDcFlushAllowed function to HwInfoConfig
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-21 18:29:43 +01:00
Filip Hazubski
6d439f88bb Explicitly set dcFlushEnable value
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-21 12:21:11 +01:00
Filip Hazubski
1107fdfe55 Rename function and remove unused parameter
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-08 22:47:40 +01:00
Rafal Maziejuk
d5f3ac37bf Add KernelExecutionType argument to encodeAdditionalWalkerFields method
Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
2021-12-08 12:00:42 +01:00
Zbigniew Zdanowicz
47dbe359bf Add command encoder for store data command
Related-To: NEO-6262

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-12-02 20:56:07 +01:00
Mateusz Hoppe
8b233f7f45 Support for bindless mode in L0 - improvements
Related-To: NEO-6448

- add new IGC compilation flag when bindless mode used
- fix SBA programming of BindlessSurfaceStateSize -
always set maximum surface state count
- fix residency of global DSH heap on gen9 - gen12lp
in bindless mode
- add L0 aub test with bindless kernel - disabled
- partial fixes in OCL aub tests


Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
2021-12-02 16:30:58 +01:00
Zbigniew Zdanowicz
9d56939980 Refactor creation of buffer surface state 1/n
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-10-21 13:11:31 +02:00
Mateusz Jablonski
5d2d81b2d1 Use uint64_t instead of void * in indirect dispatch programming
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-10-06 18:37:36 +02:00