intel/compute-runtime
1
0
Fork 0
mirror of https://github.com/intel/compute-runtime.git synced 2025-12-24 20:39:56 +08:00
Code Issues Packages Projects Releases Wiki Activity
1,959 Commits 42 Branches 655 Tags
af2dc200c52ba65089a34e0136db39d374b32dd0
Commit Graph

1275 Commits

Author SHA1 Message Date
Dunajski, Bartosz
af2dc200c5 Improve creating HwContextController 
Change-Id: If81ec18793a5af7fb58d66bb26a3bc476eaf94e0
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-18 08:57:35 +01:00
Piotr Fusik
9af011809f Make HeapIndex and GraphicsAllocation::origin not specific to Windows. 
Change-Id: Ie5a26b45c0b5eff0daf047361d8c992bd3c65ba7
 2019-02-18 08:47:49 +01:00
dongwonk
fb993d6107 limited range and internal 32bit allocators with correct base and size 
correct add 1 to the current size, gpuRange as gpuRange
only specifies the end address of the pool, not the actual
size, which causes alignment issue of all the offsets of
allocated objects. Also, a page was added in the beginning
of the limited range memory pool to avoid the base address
of it to be 0x0 that is interpreted as invalid address by
heap allocator (This makes the size reduced by pageSize)

Internal 32bit allocator is also initialized in proper way
with corrected base address.

v2: added 'givenMemoryManagerLimimedRangeAllocator' unit
    test
v3: adjust size to be freed when DrmMemoryManager instance
    is destroyed to 4GB
v4: - defined external 32bit allocator for limited Range
    allocation case.
    - softpinning object on the correct GPU address

Change-Id: Idaa0206d4133a1476cceb5a48ff8c8528742c76a
Signed-off-by: dongwonk <dongwon.kim@intel.com>
 2019-02-17 19:19:52 +01:00
Pawel Wilma
8272b3f3de Add missing numGrfRequired in blocked kernel DispatchFlags 
Change-Id: Ic1ddd532d8420c9a797a561cc5cb8ee74831eeaa
 2019-02-16 11:37:48 +01:00
dongwonk
c2f5fccfd0 DrmAllocation with correct pair of cpu address and gpu address 
correct mapping of cpu and gpu address in memory allocation
in case of NonSVM. Also, used only aligned address since offset
is already calculated and written to "allocationOffset".
gpuBaseAddress is programmed with 0 instead of base address of
heap because it represents GPU's address space.

v2: add allocationOffset to the aligned address in allocation
    data to point to exact starting address of buffer in two
    NonSVM allocation unit tests

Change-Id: I32ef512de64a13459b7c132672f837c5cb210ada
Signed-off-by: dongwonk <dongwon.kim@intel.com>
 2019-02-15 19:03:26 +01:00
dongwonk
0240f239ad check if the whole object region is in 32Bit address space boundary 
checks the address + size of buffer object to determine
whether the object is located within 32bit address space
boundary.

v2: changed end year to 2019 in ther license term
v3: added unit test for checking of flag when size of
    bo is given.
v4: two different unit tests are created to cover two
    different case separately

Change-Id: Ie2df6025fc116aca679dcfe88d858ff240278c39
Signed-off-by: dongwonk <dongwon.kim@intel.com>
 2019-02-15 16:15:06 +01:00
Zdanowicz, Zbigniew
51d34da7ec Add multiEngineQueue field to DispatchFlags and modify interfaces 
Change-Id: Iaa4754a22e9b88201aed7df01c7d6e5fd06c84a9
 2019-02-14 17:12:15 +01:00
Maciej Dziuban
12245bc88d Pass hwInfo to AubHelper::getMemBankSize() 
Change-Id: If77775cb5fb10dc82e0c7bef06a71e4292ceb6f9
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2019-02-14 16:52:10 +01:00
Dunajski, Bartosz
958d931cd9 Allow to create HardwareContextController for multiple Devices 
Change-Id: Ib066c937809536196182ca87359c487570cc2e89
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-14 16:00:00 +01:00
Zdanowicz, Zbigniew
8e1e874a76 Refactor headers and reorder include order 
Change-Id: I6b341e2b37e569af7d741bfd7a63804c0b25a4c9
 2019-02-14 13:39:01 +01:00
Kamil Diedrich
76276d4c23 Add unit test for events 
Change-Id: I13d74626a244d234a5bbaff369ed09fb59d6e33f
 2019-02-14 12:42:44 +01:00
Jablonski, Mateusz
e74b31691c Remove redundant parameter of createWddmAllocation method 
Change-Id: I1c1014eacbdee4ab6b83ea7d7b5257f25f2b46dd
Signed-off-by: Jablonski, Mateusz <mateusz.jablonski@intel.com>
 2019-02-14 07:33:45 +01:00
Jobczyk, Lukasz
b44c60ddc0 Use GPU addresses when setting up scheduler kernel's SVM args 
Change-Id: Ia2d67d031ffce2413dd8c73d87c9d3d8f3d71ede
Signed-off-by: Jobczyk, Lukasz <lukasz.jobczyk@intel.com>
 2019-02-14 07:21:31 +01:00
Hoppe, Mateusz
0f36265f55 Pass CsrType to initAubCenter 
- create AubManager with correct mode

Change-Id: I89c9c3c7edf553854b8b82788cec3dec53a62d79
 2019-02-13 09:48:05 +01:00
Mrozek, Michal
4ef67479e4 Add const keyword. 
Change-Id: I52a7e2f81c12ef29fd9c57740a21b9e68608181f
 2019-02-12 15:02:24 +01:00
Jablonski, Mateusz
db8c2bc57e Unify write memory in simulated csr when aub manager is available 
Change-Id: I28d0496b1b1fb973af4869e5626082142b5818dd
Signed-off-by: Jablonski, Mateusz <mateusz.jablonski@intel.com>
 2019-02-12 14:43:26 +01:00
Milczarek, Slawomir
e318156d9d Create AubManager with product family in parameter 
Change-Id: I3d5a2b04278d3dcec75eb2a787ec98d1ca2304ea
 2019-02-12 14:01:23 +01:00
Piotr Fusik
f014f27370 Support the EnableLocalMemory debug variable in CSR. 
Change-Id: I902b06ab0b4a3df477d12804ba74b2727d8863f6
 2019-02-12 13:09:23 +01:00
Dunajski, Bartosz
b5050db158 Remove AUBDumpConcurrentCS 
Change-Id: Ib5f2b73f918db778609922eb10710700589b21ad
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-12 12:36:07 +01:00
Mrozek, Michal
0e7fd2ffed Add multiEngine field to command queue with debug variable to override it. 
Change-Id: I3c1e424a7ad545e166e178d1726595e6d9502ca7
 2019-02-12 12:22:24 +01:00
Kamil Diedrich
a7b46ccdbd Add RAII for cl_objects 
- add removeVirtualEvent to cmdQueue fixture
- add const keyword in event functions

Change-Id: I11354eb8fceb15ae2c58bddd327863a15aab6393
 2019-02-12 11:19:35 +01:00
Dunajski, Bartosz
9f6eab0689 Change allocation properties for TIMESTAMP_PACKET_TAG_BUFFER type 
Change-Id: Ied1c0d4d7ecd27104421a5cde6c79c04c4222265
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-12 10:30:34 +01:00
Filip Hazubski
a8d4733802 Replace MemObj::flags with MemoryProperties 
Change-Id: I886cd775d1eca55964b7c4b05f6c977558a73922
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2019-02-12 10:16:09 +01:00
Mrozek, Michal
2cb3181359 Remove OCLRT name space from helpers. 
Change-Id: Ia33aa7ce93a8f3ee8b2b5609de9ac3e32e206ca1
 2019-02-12 09:55:30 +01:00
Piotr Fusik
6882cf09c1 Avoid manual memory management. 
Change-Id: Id29d9ec366e338d519aad5353a15a44ecf5998e4
 2019-02-12 09:14:51 +01:00
Venevtsev, Igor
5e8fb19e5d Remove OCL Events concept from EnqueueOperation and dispatchWalker 
Change-Id: Iec55b0be673a2a40b9621212add224a33d4abc5d
 2019-02-12 08:46:18 +01:00
Kamil Diedrich
89410a6733 Add DCFlush before resolving 
Change-Id: Id5f82edc4631aa16baa55b26b8bde69f4a30572c
 2019-02-11 16:33:34 +01:00
Maciej Plewka
5abda619a1 Set pitch and qPitch for unified multisample images 
Change-Id: I4eaf8678077f7ecd7f5f9ec860a3e59b7e89e78c
 2019-02-11 15:52:18 +01:00
Dunajski, Bartosz
12da1b0616 Remove osContextCount parameter from GraphicsAllocation 
Change-Id: I23b650e97f107008b1122a1ecea48722fe129863
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-11 15:44:37 +01:00
Dunajski, Bartosz
dc181defba Use GpuAddress for TimestampPacket programming 
Change-Id: I1303605c33e2e0267a1716e12a0bfcb341fcfbd7
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-11 15:31:17 +01:00
Dunajski, Bartosz
75fe358e5d Add HardwareContextController to use multiple Contexts in single AubCsr 
Change-Id: Ica0f1c8c4e0f55310f4650788e468640406abf51
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-11 15:22:50 +01:00
Jablonski, Mateusz
356259b865 Use .spv as IR extension on Linux 
Change-Id: If88dc0a698b02036b48e161fe82c0f594447adb6
Signed-off-by: Jablonski, Mateusz <mateusz.jablonski@intel.com>
 2019-02-11 07:51:33 +01:00
Chodor, Jaroslaw
43856e88b5 Refactor around cache flush and command queue 
Change-Id: I277e27cbc60fbbb015c0024f171697408879ec0b
 2019-02-10 17:59:33 +01:00
Venevtsev, Igor
66e3f3c16c Remove OCL Events concept from command stream receiver 
Change-Id: I4d5a97b41efe601c92c2f3f33e9e24bb7d4fa3d2
 2019-02-08 15:02:40 +01:00
Koska, Andrzej
e8771e8c2a Preparing the correct signature of WaitForSynchronizationObject 
Change-Id: I3689791ab0335009d79a3484379945f8741ba32b
 2019-02-08 14:38:31 +01:00
Mateusz Jablonski
0e55fe0801 Fix lock usage in wddm 
Change-Id: I3532b97a1b57747621e106b03263bfb070b7b05a
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-02-08 13:05:09 +01:00
Kamil Diedrich
371eef3895 Lock csr instead of device 
- replace device lock to csr lock
- add missing lock CSR in event

Change-Id: I869e46232c919a80da619c44c08e9cd78188afac
 2019-02-08 12:33:37 +01:00
Hoppe, Mateusz
cb37f2a779 Add /we4189 switch to CMAKE_CXX_FLAGS for MSVC. 
- treat unused local variables warnings as error in Debug

Change-Id: I2da08b72e0f0083d3cdf932fbf92ef4981a88615
 2019-02-08 12:06:04 +01:00
Chodor, Jaroslaw
6e0d04e25a Adding debug flag to disable DC flush in epilogue 
Change-Id: I1784be279ee9f837a0994997bec49c1925a68390
 2019-02-08 11:04:25 +01:00
Pawel Wilma
947794f166 Fix for setting context flags in AubDump 
Change-Id: Ia5fba17aac19fbcbfa6676557d1af0889f538b90
 2019-02-07 16:28:53 +01:00
Hoppe, Mateusz
4d9acf3352 Pass aubfile name to TbxCommandStreamReceiver::create and CSRWithAubDump 
Change-Id: Ib10c017ce4ed2a572815053dae3f517e0dfd9eb3
 2019-02-07 15:05:54 +01:00
Dunajski, Bartosz
30c57fd507 Simplify Device creation 
Change-Id: Iac07194db73d7f0a6914bc3550c6cba67135c24c
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-07 10:41:00 +01:00
Zdanowicz, Zbigniew
44491a111c Use MemoryManager retrieved from ExecutionEnvironment in Kernel dtor 
Change-Id: I5f3880e1a95b3cbd262847d97776b0b92a580181
 2019-02-06 17:08:51 +01:00
Kamil Diedrich
62e56d2398 Disable L3cache when resolve argument 
Change-Id: I4bb3a18d67254eef8aa4a0ce6b29401726f0b47e
 2019-02-06 15:51:31 +01:00
Dunajski, Bartosz
4733ce32cf Move pollForCompletionMask for TBX to new method 
Change-Id: I1ce760ea185064ec9122eb5bf11d9b99c9c700e2
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-06 11:18:33 +01:00
Chodor, Jaroslaw
048098ce66 Refactor around cache flush after walker 
Change-Id: If5c7399df91bd076b684bcab83f50b4852e53429
 2019-02-06 11:12:55 +01:00
Jablonski, Mateusz
e095ac834d Windows: use HEAP_INTERNAL in 32bit scenarios 
Change-Id: I652727303eec45cd3547bd98bec42f276000d9b4
Signed-off-by: Jablonski, Mateusz <mateusz.jablonski@intel.com>
 2019-02-05 19:04:06 +01:00
Hoppe, Mateusz
4943c102cd Add streamMode parameter passed to AubManager 
Change-Id: If074579fdf17c7709c33d08ccdfbf9dc80e3adc8
 2019-02-05 18:31:16 +01:00
Maciej Dziuban
ea8aa29e12 Change pollForCompletion() insertion locations 
Poll is done on:
- Aub CSR destruction
- expectMemory
- blocking calls

Poll is not done on flush

Change-Id: I1a776a932cb608c01f0de249e7cef26b00147f31
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2019-02-05 14:33:42 +01:00
Kamil Diedrich
e1eab521e7 use release for cl-objects instead of delete 
- fix for data race in events
- modification of the addition child event

Change-Id: I6ea3a413f13f13a91d37d20d8b9fad37d0ffafb9
 2019-02-05 14:09:32 +01:00