732 Commits

Author	SHA1	Message	Date
Naklicki, Mateusz	2c3b6a8760	feature: add 64-bit semaphore command ... Related-To: NEO-15636 Signed-off-by: Naklicki, Mateusz <mateusz.naklicki@intel.com>	2025-12-08 13:59:29 +01:00
Maciej Bielski	147bd894ec	refactor: use PRINT_STRING macro for most diagnostics ... Related-To: NEO-14742 Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>	2025-11-28 13:28:29 +01:00
Mateusz Jablonski	405b39f722	fix: move getting scratchPtr offset method to ImplicitArgs class ... Related-To: NEO-16649 Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>	2025-11-27 16:06:44 +01:00
Compute-Runtime-Validation	194b969ffe	Revert "feature: add 64-bit semaphore command" ... This reverts commit 4dc2945060. Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>	2025-11-27 15:38:15 +01:00
Naklicki, Mateusz	4dc2945060	feature: add 64-bit semaphore command ... Related-To: NEO-15636 Signed-off-by: Naklicki, Mateusz <mateusz.naklicki@intel.com>	2025-11-27 12:03:54 +01:00
Szymon Morek	861ea7200d	performance: increase heap size to 4MB on OCL ... Related-To: NEO-16348 Signed-off-by: Szymon Morek <szymon.morek@intel.com>	2025-11-25 09:58:16 +01:00
Jaroslaw Warchulski	f50ca4432d	refactor: cleanup includes ... Signed-off-by: Jaroslaw Warchulski <jaroslaw.warchulski@intel.com>	2025-11-20 08:24:13 +01:00
Jaroslaw Warchulski	24055f553d	refactor: cleanup includes ... Signed-off-by: Jaroslaw Warchulski <jaroslaw.warchulski@intel.com>	2025-11-14 14:54:51 +01:00
Mateusz Jablonski	a59ca3d5e8	build: add missing includes ... Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>	2025-10-24 08:41:42 +02:00
Mateusz Jablonski	3cd135e165	refactor: reduce including gmmlib headers ... Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>	2025-10-21 19:06:38 +02:00
Mateusz Jablonski	bc71b2f685	refactor: reduce usage of gmmlib headers ... use own ImagePlane wrapper Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>	2025-10-21 17:03:25 +02:00
Compute-Runtime-Validation	2eb8928ec5	Revert "performance: increase heap size to 4MB" ... This reverts commit f41bb3517a. Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>	2025-10-10 22:23:23 +02:00
Jack Myers	f06bb256c7	refactor: sba type helper ... Signed-off-by: Jack Myers <jack.myers@intel.com>	2025-10-10 11:36:36 +02:00
Szymon Morek	f41bb3517a	performance: increase heap size to 4MB ... Related-To: NEO-16348 Signed-off-by: Szymon Morek <szymon.morek@intel.com>	2025-10-09 13:03:53 +02:00
Radoslaw Jablonski	54de14a9dc	refactor: apply clang-format's InsertBraces rule ... Formats code before InsertBraces rule is enabled. Signed-off-by: Radoslaw Jablonski <radoslaw.jablonski@intel.com>	2025-10-06 15:32:46 +02:00
Bartosz Dunajski	42371ee7bd	fix: decanonize prefetch gpu va ... Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>	2025-10-06 12:54:42 +02:00
Marcel Skierkowski	047f6851f7	refactor: correct programming of SLM size ... Unify reading hw avaialble slm size: Pre-Xe2 SLMSizeInKb stores total SLM size across all DSS Xe2+ SLMSizeInKb stores SLM size per SS apply restrictions for preferred/programmable SLM size Related-To: NEO-12949 Signed-off-by: Marcel Skierkowski <marcel.skierkowski@intel.com>	2025-09-30 17:57:18 +02:00
Kamil Kopryk	f3ba701a9b	refactor: host function data programming ... Related-To: NEO-14577 Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>	2025-09-23 11:27:35 +02:00
Jaroslaw Warchulski	195bf66a49	refactor: fix typos ... Signed-off-by: Jaroslaw Warchulski <jaroslaw.warchulski@intel.com>	2025-09-22 12:46:41 +02:00
Lukasz Jobczyk	aa74555682	refactor: remove unused variable ... Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>	2025-09-11 12:01:32 +02:00
Zbigniew Zdanowicz	d8557ff2d3	feature: add scratch address programing to patch preamble ... Related-To: NEO-15376 Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>	2025-08-19 00:41:01 +02:00
Damian Tomczak	4b663e7b60	fix: use heapless helpers when heapless enabled ... Related-to: NEO-14489 Signed-off-by: Damian Tomczak <damian.tomczak@intel.com>	2025-08-18 14:36:58 +02:00
Tomasz Biernacik	28ca00fa1b	feature: adjust max threads per EU count ... Related-To: NEO-14998 Signed-off-by: Tomasz Biernacik <tomasz.biernacik@intel.com>	2025-08-06 09:02:54 +02:00
Zbigniew Zdanowicz	049bb10ce0	fix: correct encoding when destination gpu address is qword misaligned ... Related-To: NEO-15376 Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>	2025-08-01 12:08:55 +02:00
Zbigniew Zdanowicz	b57d0b2544	refactor: add method to arb check encoder to program buffer pointer directly ... Related-To: NEO-15376 Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>	2025-07-31 16:01:00 +02:00
Zbigniew Zdanowicz	08c34968f8	feature: add method to get command buffer gpu address of ending command ... Related-To: NEO-15376 Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>	2025-07-30 15:17:08 +02:00
Alicja Lukaszewicz	3f7887dc6a	refactor: add function for setting additional cache ... Related-To: NEO-15072, HSD-14024701488 Signed-off-by: Alicja Lukaszewicz <alicja.lukaszewicz@intel.com>	2025-07-30 14:45:08 +02:00
Zbigniew Zdanowicz	b5646b45e9	refactor: change interface to pass command buffer pointer as reference ... Related-To: NEO-15376 Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>	2025-07-30 11:25:53 +02:00
Zbigniew Zdanowicz	1fc0826394	feature: add encoder to program hw commands in data buffers on gpu ... Related-To: NEO-15376 Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>	2025-07-29 20:27:10 +02:00
Zbigniew Zdanowicz	f51ef2beae	feature: add encoder to dispatch commands programming data buffers on gpu ... Related-To: NEO-15376 Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>	2025-07-29 12:18:31 +02:00
Mateusz Hoppe	be483491bf	feature: extract indirect access buffer major version from ELF's notes ... - use version from ELF to create correct layout of implcit args Related-To: NEO-15574 Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>	2025-07-25 14:50:49 +02:00
Mateusz Hoppe	b17ed79618	fix: update implicitArgs versions ... - fix layout of implicit args - add enqueued local size and sync buffer ptr Related-To: NEO-15160 Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>	2025-07-22 15:12:55 +02:00
Szymon Morek	86b5660c23	performance: introduce staging copy in L0 ... Related-To: NEO-14026 Signed-off-by: Szymon Morek <szymon.morek@intel.com>	2025-07-21 08:50:43 +02:00
Zbigniew Zdanowicz	71659807c4	refactor: add new parameter to use dedicated memory to initialize surface state ... Related-To: NEO-15374 Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>	2025-07-19 03:10:51 +02:00
Maciej Bielski	35ecde70df	refactor: extract parts of KernelImp data for easier capturing ... `KernelImp` is virtual class so capturing the current kernel state cannot be done by a simple copy-instance of the class. However, this can be done by extracting the relevant data to a separate class and capturing a copy of its instance. Related-To: NEO-15374 Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>	2025-07-17 23:00:22 +02:00
Szymon Morek	0db5ce22a1	performance: use resource_barrier on Xe2 and PTL ... Related-To: NEO-14943 Signed-off-by: Szymon Morek <szymon.morek@intel.com>	2025-06-24 14:24:47 +02:00
Damian Tomczak	5cd1423bab	feature: packed surface format ... Resolves: NEO-13669 Signed-off-by: Damian Tomczak <damian.tomczak@intel.com>	2025-06-12 17:32:16 +02:00
Bartosz Dunajski	a015188166	refactor: unify prefetch encode methods ... Related-To: NEO-14703 Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>	2025-06-03 10:07:26 +02:00
Compute-Runtime-Validation	1a50e8e7c0	Revert "performance: use RESOURCE_BARRIER as stalling barrier" ... This reverts commit 556c0b64c6. Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>	2025-05-30 18:00:34 +02:00
Grochowski, Stanislaw	2d9108f8b6	refactor: change DefaultComputeWalker ... Related-To: NEO-14537 Signed-off-by: Grochowski, Stanislaw <stanislaw.grochowski@intel.com>	2025-05-29 18:05:29 +02:00
Szymon Morek	556c0b64c6	performance: use RESOURCE_BARRIER as stalling barrier ... Related-To: NEO-14943 Signed-off-by: Szymon Morek <szymon.morek@intel.com>	2025-05-28 12:30:01 +02:00
Maciej Plewka	e6f3ebce5d	fix: add pc with stall before barrier with post sync on bmg ... Related-To: NEO-14491 Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>	2025-05-28 09:24:21 +02:00
Lukasz Jobczyk	86e7d5b276	performance: Skip fence after PC when no post sync write ... Related-To: NEO-14642 Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>	2025-05-23 10:33:28 +02:00
Mateusz Hoppe	8e5b29f55e	feature: optimize local ids generation ... - only emit local ids for required dimensions Related-To: NEO-15007 Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>	2025-05-23 09:59:31 +02:00
Vysochyn, Illia	f99a4c2193	feature: Define thread group dispatch size according to kernel metadata ... Related-To: NEO-10945 Signed-off-by: Vysochyn, Illia <illia.vysochyn@intel.com>	2025-05-19 16:02:21 +02:00
Compute-Runtime-Validation	8839d62c79	Revert "performance: use RESOURCE_BARRIER as stalling barrier" ... This reverts commit 2a63853349. Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>	2025-05-16 20:19:06 +02:00
Szymon Morek	2a63853349	performance: use RESOURCE_BARRIER as stalling barrier ... Related-To: NEO-14943 Signed-off-by: Szymon Morek <szymon.morek@intel.com>	2025-05-16 14:12:18 +02:00
Szymon Morek	bff8f74de7	refactor: remove unused parameter ... Signed-off-by: Szymon Morek <szymon.morek@intel.com>	2025-05-15 12:23:27 +02:00
Young Jin Yoon	5221b5b00e	fix: patch counter values with additional blit properties ... Modified BlitCommandsHelper and CommandListHw to patch counter values when using additional blit properties and in order command list is enabled. Related-To: NEO-13003 Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>	2025-05-13 04:32:31 +02:00
Lukasz Jobczyk	1d1414febc	refactor: remove unused dc flush mitigation ... Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>	2025-05-09 08:26:26 +02:00