Setter in HardwareCommandsHelper
Getter in UnitTestHelper
Change-Id: I26610d0ccf0113b2b3d3c8ba2d1edd5bf8b41175
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
- When resource is uncached for surface state and not used in stateless manner
then it doesn't need to flush cache
- Minor cleanup
Change-Id: I4cfe5a6fe3e666200407d9acdd89e6f64b2b3eed
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
- Change kernel to properly detect true stateless resources
- do not turn of stateless l3 if arg is used in pure stateful manner
- refactor variable names to better reflect what they do
- improve mock kernel with internal to have setKernelArg capabilties
Change-Id: I2cdde04f2144d9b86dc1486126632db0fd7cad49
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
- With this flag resource will not be cached in L3 for stateful accesses.
Change-Id: Icf9a393ab92d55c2cdf30444420ea40da0d5630c
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
Add isL3Configurable() method to HwHelper to query if L3 is
configurable using an HwHelper instance.
Change-Id: I0f350ae292f12980611a250301293378dbd8dd91
Signed-off-by: Sebastian Sanchez <sebastian.sanchez@intel.com>
- when ISA is being destroyed , check what are the users of it and register
instruction cache flushes there.
- For subsequent enqueue commands this would result in properly flushed
instruction cache.
Change-Id: I3791cd77ee42da9f87508c64a65cdc6238950858
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
- remove default value from synchronousDestroy param in
DrmMemoryManager::unreference
- unreference BufferObject in synchronous mode before release
GPU and CPU memory
- add ULTs
Related-To: NEO-2877
Change-Id: I8065c27923cf4259a0fcd0f6d8d6d5b7c4b810c0
Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
- With this mechanism csr with add pipe control with instruction cache flush
prior to enqueue, to make sure that this cache is flushed.
Change-Id: I664f212427686e9957027c7cf6c0dab17d2a3cac
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
- add new policy to select L1 caching
- this is when kernel doesn't have any stateless writes
Change-Id: I3948e652797420976159bbfec2c2a154eb9e18ee
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
- After this change we start using real MOCS index as an argument to sba
programming
- We also start tracking real MOCS index in Command Stream Receiver.
Change-Id: Id34cffd7e58cb7363df02ac76f82bf377f4bbd77
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
- no need for virtual functions and helpers, this is just a constant that
is the same everywhere.
Change-Id: Id0ebfd2eed26e26f90f104ec456dcc997be70211
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
- currently no compiler support yet, hence it returns true.
- minor cleanup of kernel tests.
Change-Id: Ic153810b1a6062d0bae22d6faab5db601764dd98
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
Wire in MemoryPropertiesFlags support to:
-isLinearStorageForced
Related-To: NEO-3132
Change-Id: Ib29c4b1c8a30f2449d7fcb2778cb827baf61915e
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
Wire in MemoryPropertiesFlags support to:
Image functions:
-validate
-validatePackedYUV
-validateImageTraits
Related-To: NEO-3132
Change-Id: I4d71d4170704d2117d6d17602f5f2ad0f30ab1f8
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
