Previous change regarding NEO-6785 added encoding of number of barriers
to specific value representation depending on hardware that we program for.
In patch token format encoding of number of barriers is sent via
hasBarriers field in a token.
In zebin true number of barriers is sent via barrier_count field in
zeInfo.
To remove this discrepancy, translate encoded number of barriers into
true number of barriers in legacy format.
Resolves: NEO-6785
Signed-off-by: Krystian Chmielewski <krystian.chmielewski@intel.com>
Change modifies the encoding entry in fatbinary for platforms.
If numbering in -device is used, the value PRODUCT_CONFIG will be encoded.
The functionality that returns the correct product config values has
also been added.
Related-To: NEO-6744
Signed-off-by: Daria Hinz <daria.hinz@intel.com>
When programming number of barriers use BARRIER_SIZE enumeration.
Resolves: NEO-6785
Signed-off-by: Krystian Chmielewski <krystian.chmielewski@intel.com>
require 48bit resource for ring/semaphore buffer
for multi tile allocations select first tile
for single tile allocation select preferred tile
Related-To: NEO-6698
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
For different platforms based on number of available threads
and debug surface layout, calculate max debug surface size.
Related-To: NEO-6676
Signed-off-by: Jitendra Sharma <jitendra.sharma@intel.com>
In direct submission scenario command/ring/semaphore buffer allocations
are placed in the same memory bank to ensure that their memory is updated in
correct order
Related-To: NEO-6698
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
Change ThreadArbitrationPolicy::NotPresent value to -1
Update initial values to ThreadArbitrationPolicy::NotPresent
Related-To: NEO-6728
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
Rename:
- debug flag ProgramPipeControlPriorToNonPipelinedStateCommand
to ProgramExtendedPipeControlPriorToNonPipelinedStateCommand
- local variables
Related-To: NEO-6615
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
Add pipe control before state base address, state compute
mode and state sip commands on DG2 and PVC when CCS flow is used.
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
OCL image surface state programming for Xe Hp core is now reusing logic
of EncodeSurfaceState helper
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
Program Multi Gpu params in surface state only on Xe Hp Sdv
Respect zero-size image scenario when programming surface state
Move XeHp-only tests to dedicated subdir
Related-To: NEO-6466
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
Separate unit test helper definitions bdw_and_later / xe_hp_and_later
Related-To: NEO-6466
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
First step to separate dispatch blit commands for buffers
from dispatch blit commands for images.
Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
Related-To: NEO-6134
PVC will support buffers greater than 4GB, hence we have to
use stateless accessing mode as default.
Signed-off-by: Kopryk, Kamil <kamil.kopryk@intel.com>
