Commit Graph

63 Commits

Author SHA1 Message Date
Lukasz Jobczyk
f0bf8ade4d performance: Enable async builtin init xe2+, linux and windows
Related-To: NEO-14821

Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2025-06-11 11:25:26 +02:00
Bartosz Dunajski
9647612f98 fix: update prefetch mocs settings
Related-To: NEO-14703

Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2025-06-02 13:22:42 +02:00
Dominik Dabek
6d8188bc56 fix: enable usm device pool api wise
For OCL usm device pool enabled on MTL, LNL, PTL
For L0 usm device pool enabled on PTL, disabled on MTL, LNL

Related-To: NEO-6893

Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2025-06-02 10:28:15 +02:00
Lukasz Jobczyk
332340b02b refactor: Prework for release fence removal leaving acquire fence
Related-To: NEO-14642

Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2025-05-30 12:01:28 +02:00
Katarzyna Cencelewska
e357e7e404 fix: correct limitation for num threads per thread group
taking into account the max work group limit
when simd1 don't use the same limitation as for simd32

Resolves: NEO-14922
Related-To: NEO-11881
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2025-05-29 16:34:40 +02:00
Vysochyn, Illia
3989471ffc fix: Use round robin after stall as a default arbitration mode
Related-To: NEO-14251,HSD-18042035684,HSD-18041638491,HSD-18042040816

Signed-off-by: Vysochyn, Illia <illia.vysochyn@intel.com>
2025-05-28 17:47:48 +02:00
Lukasz Jobczyk
2e9643f46c performance: Enable small buffer pool allocator on PTL
Resolves: NEO-14817

Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2025-05-26 22:07:50 +02:00
Compute-Runtime-Validation
593c9e76f2 Revert "fix: correct limitation for num threads per thread group"
This reverts commit 6ad4ad41b1.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2025-05-23 02:51:17 +02:00
Katarzyna Cencelewska
6ad4ad41b1 fix: correct limitation for num threads per thread group
taking into account the max work group limit

Resolves: NEO-14922
Related-To: NEO-11881
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2025-05-22 00:06:21 +02:00
Vysochyn, Illia
f99a4c2193 feature: Define thread group dispatch size according to kernel metadata
Related-To: NEO-10945

Signed-off-by: Vysochyn, Illia <illia.vysochyn@intel.com>
2025-05-19 16:02:21 +02:00
Tomasz Biernacik
e376e738f3 fix: disable deferring MOCS on WSL for LNL
Related-To: NEO-14643

Signed-off-by: Tomasz Biernacik <tomasz.biernacik@intel.com>
2025-05-15 16:50:43 +02:00
Szymon Morek
ef9eb2f703 performance: enable staging buffers on PTL
Related-To: NEO-14820

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2025-05-09 12:56:21 +02:00
Lukasz Jobczyk
1d1414febc refactor: remove unused dc flush mitigation
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2025-05-09 08:26:26 +02:00
Szymon Morek
2f5c6613d0 performance: resolve dependencies by PC on PTL linux
Related-To: NEO-14818

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2025-05-08 20:19:21 +02:00
Szymon Morek
6ae43123f6 fix: correct usages of ULLS-related resources
Related-To: NEO-14360

Current gmm usage type of these resources is causing
them to be cached, which is incorrect.

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2025-05-08 12:12:45 +02:00
Tomasz Biernacik
f03decfc25 performance: disable coherency for buffers on PTL
Related-To: NEO-9421

Signed-off-by: Tomasz Biernacik <tomasz.biernacik@intel.com>
2025-05-05 13:47:23 +02:00
Young Jin Yoon
55e7b6a209 feature: support copy function post-sync [3/n]
Refactored EncodePostSync to use more generic terms by renaming
variables.
Added some helper functions in EncodePostSync.

Related-To: NEO-13003
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
2025-05-01 19:20:01 +02:00
Compute-Runtime-Validation
0c3b765942 Revert "refactor: add BlitSyncPropertiesExt to BlitSyncProperties"
This reverts commit b5a259aded.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2025-05-01 03:23:53 +02:00
Young Jin Yoon
b5a259aded refactor: add BlitSyncPropertiesExt to BlitSyncProperties
Added BlitSyncPropertiesExt to provide additional information for
different platform and/or blitter commands.

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@intel.com>
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
2025-04-30 19:11:34 +02:00
Lukasz Jobczyk
6f4a56d440 refactor: pass product helper to isFenceAllocationRequired
Related-To: NEO-14642

Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2025-04-28 14:09:02 +02:00
Szymon Morek
8ec5688ca1 Revert "performance: extend usage of staging buffers"
This reverts commit 6a4ddf5dfb.

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2025-04-24 11:02:27 +02:00
Szymon Morek
6a4ddf5dfb performance: extend usage of staging buffers
Related-To: NEO-14026

Move enabling from xe2 to xe2_and_later

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2025-04-22 16:46:52 +02:00
Young Jin Yoon
05c6612386 refactor: add EncodePostSyncArgs to EncodeDispatchKernelArgs
Refactored various member variables in EncodeDispatchKernel to directly
include EncodePostSync
Changed command encoder and command list to use the modified
EncodeDispatchKernel.

Related-To: NEO-13003
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
2025-04-17 20:55:40 +02:00
Young Jin Yoon
5a2a792c34 Revert "refactor: add EncodePostSyncArgs to EncodeDispatchKernelArgs"
This reverts commit 40aef1555e.

Related-To: NEO-13003
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
2025-04-17 15:37:05 +02:00
Young Jin Yoon
40aef1555e refactor: add EncodePostSyncArgs to EncodeDispatchKernelArgs
Refactored various member variables in EncodeDispatchKernel to directly
include EncodePostSync
Changed command encoder and command list to use the modified
EncodeDispatchKernel.

Related-To: NEO-13003
Signed-off-by: Young Jin Yoon <young.jin.yoon@intel.com>
2025-04-16 17:46:07 +02:00
Mateusz Jablonski
f6b92aa5d5 build: update default PTL revision to B0
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2025-04-16 09:44:58 +02:00
Lukasz Jobczyk
455209aadc refactor: Simplify fence selection in ULLS
Related-To: NEO-14642

Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2025-04-15 14:04:47 +02:00
Marcel Skierkowski
31f0fd4672 refactor: rename variable slmSize
Max programmable slm size is stored in RuntimeCapabilityTable as slmSize.
That is misleading name
Rename the variable slmSize to better reflect the actual meaning of the member.

Related-To: NEO-12949
Signed-off-by: Marcel Skierkowski <marcel.skierkowski@intel.com>
2025-04-14 20:00:29 +02:00
Kamil Kopryk
dd3d294f87 performance: cache MOCS values
This change caches the most used MOCS values:

* getMOCS(GMM_RESOURCE_USAGE_OCL_BUFFER_CONST);
* getMOCS(GMM_RESOURCE_USAGE_OCL_BUFFER);
* getMOCS(GMM_RESOURCE_USAGE_OCL_BUFFER_CACHELINE_MISALIGNED);
inside gmmHelper class during initialization to avoid repeated
calls of virtual functions, branches and/or gmm lib access.

and adds more readably corresponding getters:
* getL1EnabledMOCS
* getL3EnabledMOCS
* getUncachedMOCS

If force all resources uncached is called,
these 3 cached mocs values are reinitialized

It also changes the order of gmmHelper members, to avoid
not needed padding after addressWidth
and simplifies logic in getMocsIndex function
for xehp and later products.

Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2025-04-14 14:12:48 +02:00
Szymon Morek
5b20450162 performance: enable compression on PTL
Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2025-04-11 17:26:29 +02:00
Lukasz Jobczyk
8978ea5e5a performance: Do not create global fence allocation on integrated
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2025-04-07 11:22:04 +02:00
Compute-Runtime-Validation
f332571d96 Revert "performance: Do not create global fence allocation on integrated"
This reverts commit ecf8a07d26.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2025-04-04 16:26:19 +02:00
Lukasz Jobczyk
ecf8a07d26 performance: Do not create global fence allocation on integrated
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2025-04-04 11:45:22 +02:00
Filip Hazubski
504440fc4d feature: Add ftrHeaplessMode flag
Pass hwInfo to isHeaplessModeEnabled and isForceBindlessRequired functions.

Related-To: NEO-14526

Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2025-04-02 21:06:05 +02:00
Mateusz Jablonski
4bc13fa0dc fix: correct MetricsLibraryGenId for Xe3
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2025-03-26 16:35:10 +01:00
Tomasz Biernacik
f4f13dfeec Revert "performance: disable cpu caching for buffers on PTL"
This reverts commit c3f0c4e4ac.

Signed-off-by: Tomasz Biernacik <tomasz.biernacik@intel.com>
2025-03-24 10:23:07 +01:00
Kamil Kopryk
2e729bcb4c refactor: move isTimestampWaitSupportedForQueues to productHelper
Related-to: NEO-13163
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2025-03-19 09:31:33 +01:00
Tomasz Biernacik
c3f0c4e4ac performance: disable cpu caching for buffers on PTL
Related-To: NEO-9421

Signed-off-by: Tomasz Biernacik <tomasz.biernacik@intel.com>
2025-03-13 18:34:42 +01:00
Compute-Runtime-Validation
0d5baa2c30 Revert "performance: Cache timestamps on CPU"
This reverts commit 83637404bf.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2025-03-12 04:41:46 +01:00
Lukasz Jobczyk
83637404bf performance: Cache timestamps on CPU
Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2025-03-11 13:40:18 +01:00
Tomasz Biernacik
e644b09433 performance: override allocation caching on integrated platforms
Related-To: NEO-9421

Signed-off-by: Tomasz Biernacik <tomasz.biernacik@intel.com>
2025-03-07 15:44:00 +01:00
Szymon Morek
82fba79d9d performance: set 1ms timeout for ulls controller on LNL and PTL
Related-To: NEO-13843

Limit scope to Windows only.

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2025-03-06 09:13:58 +01:00
Vysochyn, Illia
1eafbc30f8 feature: Enable eu thread scheduling mode override via IDD
Enables eu thread scheduling mode override via the
INTERFACE_DESCRIPTOR_DATA and COMPUTE_WALKER.

Defines encodeEuSchedulingPolicy operating on INTERFACE_DESCRIPTOR_DATA
or Xe3 platform.

Adds tests verifying that thread scheduling mode can be overridden via
COMPUTE_WALKER.

Related-To: NEO-13771, HSD-18041256338, HSD-14013056398

Signed-off-by: Vysochyn, Illia <illia.vysochyn@intel.com>
2025-02-26 17:04:43 +01:00
Compute-Runtime-Validation
f64fd7fc42 Revert "performance: disable cpu caching for buffers on PTL"
This reverts commit 681ef3693a.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2025-02-24 10:07:15 +01:00
Szymon Morek
681ef3693a performance: disable cpu caching for buffers on PTL
Related-To: NEO-14168

Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2025-02-21 13:07:04 +01:00
Filip Hazubski
794b21a3fa refactor: Add extra parameters to computeSlmValues function
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2025-02-20 15:35:52 +01:00
Filip Hazubski
cf8b6435b2 test: fix typo
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2025-02-07 18:11:45 +01:00
Mateusz Jablonski
81227cedd1 feature: enable WMTP on PTL
Related-To: NEO-13706
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2025-02-05 16:59:23 +01:00
Maciej Plewka
aace15d6bc fix: remove msaa w/a for xe3
Related-To: NEO-13290, NEO-12587
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2025-02-03 10:38:01 +01:00
Kamil Kopryk
ef896cc799 refactor: introduce ImageSurfaceState helper class
Moved global functions to the ImageSurfaceStateHelper class,
with declarations in the header file and definitions in the base .inl
file.
This change reduces compilation time by:
- removing unnecessary includes from the header file
- adding explicit template instantiations, which are faster than
implicit template instantiations.

Additionally, the image_skl_and_later.inl file has been removed as it
is no longer needed, and its implementation has been moved to the base .inl

Related-To: NEO-12149

Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2025-01-30 19:20:31 +01:00