rename private scratch space into scratch space slot 1 as it can be generic
Related-To: NEO-9944
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
rename private scratch space into scratch space slot 1 as it can be generic
Related-To: NEO-9944
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
Add mechanism to preallocate cmd buffer allocations in command stream
receiver reusable allocations list per command queue initialized.
This should limit additional allocations during hot loop.
Needs to be enabled in subsequent commits by setting product helper
method.
Related-To: NEO-8152
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
- use testTaskCountReady method to check TaskCount value
- download all allocations when TaskCount is ready
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
If waitForBarrier is not passed outEvent then do
dcFlush on the next synchronize call.
Related-To: NEO-8147
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
Use flushStamp=taskCount when passed flushStamp==0.
This will cause driver to busy wait for a short while before falling
back to use kmd notify.
Related-To: GSD-3612
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
This is number of small tweaks to state cache invalidation:
1. Invalidate if heap was actually created.
2. Check if os context was actually initialized.
3. Heap allocation was actually submitted, as it might attain zero task count
value, when allocation is stored in csr internal storage, as csr wasn't used,
but the csr task count being zero is assigned to heap allocation when stored.
Related-To: NEO-5055
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
- 3D btd command should be programed only once per context
- Add conditional pipe control command prior dispatching 3D btd command
- share 3D btd state between immediate and regular command lists
- add pipe control after ray tracing kernel to invalidate state cache
Related-To: NEO-5055
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
- full properties update is time intesive task and must be done only once
- selective update can be done after initial update
- dirty flag will allow to distinguish initial update is done
Related-To: NEO-5055
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
This is small optimization to replace virtual call and retrieved struct with
cached value.
Related-To: NEO-5055
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
- updates coming from regular list are updated in csr last sent variables
- all per context and per kernel transitions kept in single place
- state updates from intermediate to regular are set in csr properties
- global atomics support duplicates removed
Related-To: NEO-5055
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
multi storage memory migration needs to wait until memory is no longer used
Related-To: NEO-5735
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
This change has two issues fixed.
First fix assures event must not download all allocations sent to GPU
when event is not ready.
Second fix performs page walk on event allocation before event allocation
can be downloaded, as download before page walk is not supported scenario
in TBX mode.
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
