Maciej Plewka 1cd00b5b89 fix: use per product cache line size to align heaps ...

Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>

2024-07-24 17:29:20 +02:00

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api

refactor: collate ze_structure_type_t macros

2024-07-19 23:17:42 +02:00

cmake

CMake: adjust testing flags based on TESTS_* flags

2022-10-28 10:32:22 +02:00

core

fix: use per product cache line size to align heaps

2024-07-24 17:29:20 +02:00

ddi

fix: correct filling ddi table entries 1/n

2024-04-09 14:23:15 +02:00

doc

documentation: Update L0 Core release version to v1.5

2024-06-27 19:07:48 +02:00

experimental

refactor: make spdlog optional

2024-06-07 14:14:12 +02:00

include

fix: correct stype enum value for queue copy offload hint

2024-07-23 09:59:16 +02:00

source

feature: Add extensions to expose dot product capabilities

2023-10-31 21:54:39 +01:00

sysman

refactor(sysman): Remove Pmt tile aggregator from Memory Module

2024-07-24 08:47:17 +02:00

tools

refactor: correct the naming of some topology-related variables

2024-07-24 08:39:12 +02:00

.config

ci: add initial configs

2023-12-12 16:00:46 +01:00

CMakeLists.txt

refactor: add L0 include dir to solution

2024-07-12 15:34:56 +02:00

os_release_info.cmake

build: unify minimum required cmake version

2024-05-21 13:10:17 +02:00

ze_intel_gpu_version.h.in

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