Files
compute-runtime/unit_tests/command_stream
Mrozek, Michal e7a4635dd6 Add mechanism to register instruction cache flushes.
- With this mechanism csr with add pipe control with instruction cache flush
prior to enqueue, to make sure that this cache is flushed.

Change-Id: I664f212427686e9957027c7cf6c0dab17d2a3cac
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-28 07:56:41 +02:00
..
2018-11-14 19:25:13 +01:00