Dunajski, Bartosz 2102117e12 Fix data race for TLB flush check ...

Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>

2022-08-31 12:27:48 +02:00

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create_direct_submission_drm

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create_direct_submission_drm_or_wddm

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create_direct_submission_wddm

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dispatchers

Refactor PIPE_CONTROL programming

2022-08-23 13:55:25 +02:00

linux

Fix data race for TLB flush check

2022-08-31 12:27:48 +02:00

windows

Allocate new ring buffer if all are in use

2022-06-10 12:45:49 +02:00

CMakeLists.txt

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direct_submission_bdw_and_later.inl

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direct_submission_controller.cpp

Track ccs count per subdevice in direct submission controller

2022-06-20 11:52:01 +02:00

direct_submission_controller.h

Set the default value of the controller timeout divisor to 1

2022-08-05 09:52:58 +02:00

direct_submission_hw_diagnostic_mode.cpp

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direct_submission_hw_diagnostic_mode.h

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direct_submission_hw.cpp

Use LogicalStateHelper to encode SystemMemoryFence

2022-06-24 13:29:58 +02:00

direct_submission_hw.h

Add flag to control prefetcher disabling behaviour

2022-08-16 16:01:30 +02:00

direct_submission_hw.inl

Add flag to control prefetcher disabling behaviour

2022-08-16 16:01:30 +02:00

direct_submission_prefetch_mitigation_base.inl

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direct_submission_prefetch_mitigation_xe_hp_core_and_later.inl

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direct_submission_prefetcher_base.inl

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direct_submission_prefetcher_pvc_and_later.inl

Add flag to control prefetcher disabling behaviour

2022-08-16 16:01:30 +02:00

direct_submission_prefetcher_xe_hp_core_and_later.inl

Add flag to control prefetcher disabling behaviour

2022-08-16 16:01:30 +02:00

direct_submission_properties.h

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direct_submission_xe_hp_core_and_later.inl

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