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40146291ad
Updating files modified in 2018 only. Older files remain with old style copyright header Change-Id: Ic99f2e190ad74b4b7f2bd79dd7b9fa5fbe36ec92 Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
92 lines
3.3 KiB
C++
92 lines
3.3 KiB
C++
/*
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* Copyright (C) 2017-2018 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "runtime/helpers/hw_info.h"
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#include "runtime/os_interface/hw_info_config.h"
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#include "runtime/os_interface/linux/drm_neo.h"
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#include "runtime/os_interface/linux/os_interface.h"
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namespace OCLRT {
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template <>
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int HwInfoConfigHw<IGFX_GEMINILAKE>::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) {
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Drm *drm = osIface->get()->getDrm();
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FeatureTable *pSkuTable = const_cast<FeatureTable *>(hwInfo->pSkuTable);
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GT_SYSTEM_INFO *pSysInfo = const_cast<GT_SYSTEM_INFO *>(hwInfo->pSysInfo);
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WorkaroundTable *pWaTable = const_cast<WorkaroundTable *>(hwInfo->pWaTable);
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pSysInfo->VEBoxInfo.Instances.Bits.VEBox0Enabled = 1;
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pSysInfo->VEBoxInfo.IsValid = true;
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pSkuTable->ftrGpGpuMidBatchPreempt = 1;
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pSkuTable->ftrGpGpuThreadGroupLevelPreempt = 1;
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pSkuTable->ftrGpGpuMidThreadLevelPreempt = 0;
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pSkuTable->ftr3dMidBatchPreempt = 1;
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pSkuTable->ftr3dObjectLevelPreempt = 1;
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pSkuTable->ftrPerCtxtPreemptionGranularityControl = 1;
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pSkuTable->ftrLCIA = 1;
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pSkuTable->ftrPPGTT = 1;
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pSkuTable->ftrL3IACoherency = 1;
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pSkuTable->ftrIA32eGfxPTEs = 1;
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pSkuTable->ftrTranslationTable = 1;
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pSkuTable->ftrUserModeTranslationTable = 1;
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pSkuTable->ftrEnableGuC = 1;
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pSkuTable->ftrTileMappedResource = 1;
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pSkuTable->ftrULT = 1;
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pSkuTable->ftrAstcHdr2D = 1;
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pSkuTable->ftrAstcLdr2D = 1;
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pWaTable->waLLCCachingUnsupported = 1;
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pWaTable->waMsaa8xTileYDepthPitchAlignment = 1;
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pWaTable->waFbcLinearSurfaceStride = 1;
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pWaTable->wa4kAlignUVOffsetNV12LinearSurface = 1;
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pWaTable->waEnablePreemptionGranularityControlByUMD = 1;
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pWaTable->waSendMIFLUSHBeforeVFE = 1;
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pWaTable->waForcePcBbFullCfgRestore = 1;
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pWaTable->waReportPerfCountUseGlobalContextID = 1;
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pWaTable->waSamplerCacheFlushBetweenRedescribedSurfaceReads = 1;
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int enabled = 0;
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int retVal = drm->getEnabledPooledEu(enabled);
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if (retVal == 0) {
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pSkuTable->ftrPooledEuEnabled = (enabled != 0) ? 1 : 0;
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}
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if (enabled) {
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int num = 0;
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retVal = drm->getMinEuInPool(num);
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if (retVal == 0 && ((num == 3) || (num == 6) || (num == 9))) {
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pSysInfo->EuCountPerPoolMin = static_cast<uint32_t>(num);
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}
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//in case of failure or not getting right values, fallback to default
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else {
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if (pSysInfo->SubSliceCount == 3) {
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// Native 3x6, PooledEU 2x9
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pSysInfo->EuCountPerPoolMin = 9;
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} else {
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// Native 3x6 fused down to 2x6, PooledEU worst case 3+9
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pSysInfo->EuCountPerPoolMin = 3;
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}
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}
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pSysInfo->EuCountPerPoolMax = pSysInfo->EUCount - pSysInfo->EuCountPerPoolMin;
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}
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auto &kmdNotifyProperties = hwInfo->capabilityTable.kmdNotifyProperties;
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kmdNotifyProperties.enableKmdNotify = true;
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kmdNotifyProperties.enableQuickKmdSleep = true;
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kmdNotifyProperties.enableQuickKmdSleepForSporadicWaits = true;
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kmdNotifyProperties.delayKmdNotifyMicroseconds = 50000;
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kmdNotifyProperties.delayQuickKmdSleepMicroseconds = 5000;
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kmdNotifyProperties.delayQuickKmdSleepForSporadicWaitsMicroseconds = 200000;
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return 0;
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}
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template class HwInfoConfigHw<IGFX_GEMINILAKE>;
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} // namespace OCLRT
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