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ef4cc0e685
Related-To: NEO-4751 Change-Id: I430a354314e0f3d7a042505c377f3b7d9e9d588b Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
42 lines
1.5 KiB
C++
42 lines
1.5 KiB
C++
/*
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* Copyright (C) 2019-2020 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include "shared/source/gen12lp/hw_cmds_base.h"
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namespace AubMemDump {
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struct AubStream;
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}
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struct AubGTTData;
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namespace NEO {
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class CommandStreamReceiver;
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class GraphicsAllocation;
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struct PipelineSelectArgs;
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class Image;
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namespace Gen12LPHelpers {
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bool pipeControlWaRequired(PRODUCT_FAMILY productFamily);
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bool workaroundRequired(uint32_t lowestSteppingWithBug, uint32_t steppingWithFix, const HardwareInfo &hwInfo);
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bool imagePitchAlignmentWaRequired(PRODUCT_FAMILY productFamily);
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void adjustCoherencyFlag(PRODUCT_FAMILY productFamily, bool &coherencyFlag);
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bool isLocalMemoryEnabled(const HardwareInfo &hwInfo);
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void initAdditionalGlobalMMIO(const CommandStreamReceiver &commandStreamReceiver, AubMemDump::AubStream &stream);
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uint64_t getPPGTTAdditionalBits(GraphicsAllocation *graphicsAllocation);
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void adjustAubGTTData(const CommandStreamReceiver &commandStreamReceiver, AubGTTData &data);
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void setAdditionalPipelineSelectFields(void *pipelineSelectCmd,
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const PipelineSelectArgs &pipelineSelectArgs,
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const HardwareInfo &hwInfo);
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bool isOffsetToSkipSetFFIDGPWARequired(const HardwareInfo &hwInfo);
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bool isForceDefaultRCSEngineWARequired(const HardwareInfo &hwInfo);
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bool isForceEmuInt32DivRemSPWARequired(const HardwareInfo &hwInfo);
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bool is3DPipelineSelectWARequired(const HardwareInfo &hwInfo);
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} // namespace Gen12LPHelpers
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} // namespace NEO
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