Files
compute-runtime/unit_tests/helpers
Mrozek, Michal e7a4635dd6 Add mechanism to register instruction cache flushes.
- With this mechanism csr with add pipe control with instruction cache flush
prior to enqueue, to make sure that this cache is flushed.

Change-Id: I664f212427686e9957027c7cf6c0dab17d2a3cac
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
2019-08-28 07:56:41 +02:00
..
2017-12-21 00:45:38 +01:00
2019-08-26 17:00:53 +02:00
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2017-12-21 00:45:38 +01:00
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