mirror of
https://github.com/intel/compute-runtime.git
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94 lines
3.5 KiB
C++
94 lines
3.5 KiB
C++
/*
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* Copyright (c) 2017 - 2018, Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "runtime/helpers/hw_info.h"
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#include "runtime/os_interface/hw_info_config.h"
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namespace OCLRT {
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template <>
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int HwInfoConfigHw<IGFX_CANNONLAKE>::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) {
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FeatureTable *pSkuTable = const_cast<FeatureTable *>(hwInfo->pSkuTable);
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GT_SYSTEM_INFO *pSysInfo = const_cast<GT_SYSTEM_INFO *>(hwInfo->pSysInfo);
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WorkaroundTable *pWaTable = const_cast<WorkaroundTable *>(hwInfo->pWaTable);
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if (pSysInfo->SubSliceCount == 9) {
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pSysInfo->SliceCount = 4;
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} else if (pSysInfo->SubSliceCount > 5) {
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pSysInfo->SliceCount = 3;
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} else if (pSysInfo->SubSliceCount > 3) {
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pSysInfo->SliceCount = 2;
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} else {
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pSysInfo->SliceCount = 1;
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}
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if ((pSysInfo->SliceCount > 1) && (pSysInfo->IsL3HashModeEnabled)) {
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pSysInfo->L3BankCount--;
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pSysInfo->L3CacheSizeInKb -= 256;
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}
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pSkuTable->ftrGpGpuMidBatchPreempt = 1;
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pSkuTable->ftrGpGpuThreadGroupLevelPreempt = 1;
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pSkuTable->ftrGpGpuMidThreadLevelPreempt = 0;
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pSkuTable->ftr3dMidBatchPreempt = 1;
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pSkuTable->ftr3dObjectLevelPreempt = 1;
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pSkuTable->ftr3dMidBatchPreempt = 1;
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pSkuTable->ftrGpGpuThreadGroupLevelPreempt = 1;
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pSkuTable->ftrPerCtxtPreemptionGranularityControl = 1;
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pSkuTable->ftrPPGTT = 1;
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pSkuTable->ftrSVM = 1;
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pSkuTable->ftrL3IACoherency = 1;
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pSkuTable->ftrIA32eGfxPTEs = 1;
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pSkuTable->ftrStandardMipTailFormat = 1;
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pSkuTable->ftrDisplayYTiling = 1;
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pSkuTable->ftrTranslationTable = 1;
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pSkuTable->ftrUserModeTranslationTable = 1;
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pSkuTable->ftrTileMappedResource = 1;
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pSkuTable->ftrEnableGuC = 1;
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pSkuTable->ftrFbc = 1;
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pSkuTable->ftrFbc2AddressTranslation = 1;
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pSkuTable->ftrFbcBlitterTracking = 1;
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pSkuTable->ftrFbcCpuTracking = 1;
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pSkuTable->ftrAstcHdr2D = 1;
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pSkuTable->ftrAstcLdr2D = 1;
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pWaTable->wa4kAlignUVOffsetNV12LinearSurface = 1;
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pWaTable->waSendMIFLUSHBeforeVFE = 1;
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pWaTable->waReportPerfCountUseGlobalContextID = 1;
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pWaTable->waSamplerCacheFlushBetweenRedescribedSurfaceReads = 1;
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if ((1 << hwInfo->pPlatform->usRevId) & 0x3) {
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pWaTable->waFbcLinearSurfaceStride = 1;
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}
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if ((1 << hwInfo->pPlatform->usRevId) & 0x1) {
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pWaTable->waEncryptedEdramOnlyPartials = 1;
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}
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return 0;
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}
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template class HwInfoConfigHw<IGFX_CANNONLAKE>;
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} // namespace OCLRT
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