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6994106c1f
Storing config space during sysman init might result in providing inappropriate properties as config space can be modified. Read config space whenever properties are queried. Related-To: LOCI-4513 Signed-off-by: Bellekallu Rajkiran <bellekallu.rajkiran@intel.com>
70 lines
2.4 KiB
C++
70 lines
2.4 KiB
C++
/*
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* Copyright (C) 2023 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include <cstdint>
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namespace L0 {
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// Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
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// configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
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// configuration space.
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#define PCI_CFG_SPACE_SIZE 256 // Conventional PCI and PCI-X Mode 1 devices
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#define PCI_CFG_SPACE_EXP_SIZE 4096 // PCI-X Mode 2 and PCIe devices
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// PCI device status register
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#define PCI_STATUS 0x06 // 16 bit status register of PCI device
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#define PCI_STATUS_CAP_LIST 0x10 // Support Capability List
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// Capability lists
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#define PCI_CAPABILITY_LIST 0x34 // Offset of first capability list entry
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#define PCI_CAP_LIST_ID 0 // Capability ID
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#define PCI_CAP_ID_EXP 0x10 // PCI Express
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#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
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#define PCI_CAP_FLAGS 2 // Capability defined flags (16 bits)
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// Express Capabilities
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#define PCI_EXP_TYPE_RC_END 0x9 // Root Complex Integrated Endpoint
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#define PCI_EXP_TYPE_RC_EC 0xa // Root Complex Event Collector
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#define PCI_EXP_SLTCTL 24 // Slot Control
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#define PCI_EXP_SLTCTL_HPIE 0x0020 // Hot-Plug Interrupt Enable
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#define PCI_BRIDGE_CONTROL 0x3e // Bridge control register
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#define PCI_BRIDGE_CTL_BUS_RESET 0x40 // Secondary bus reset
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// Link Capabilities
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#define PCI_EXP_LNKCAP 12 // offset to link capabilities
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// Resizable BARs
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#define PCI_REBAR_CAP 4 // capability register
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#define PCI_REBAR_CAP_SIZES 0x00FFFFF0 // supported BAR sizes
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#define PCI_REBAR_CTRL 8 // control register
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// Extended Capabilities
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#define PCI_EXT_CAP_ID_REBAR 0x15 // Resizable BAR
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#define PCI_EXT_CAP_ID_VF_REBAR 0x24 // VF Resizable BAR
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#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
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#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
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#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
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class PciUtil {
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public:
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static inline uint32_t getDwordFromConfig(uint32_t pos, uint8_t *configMemory) {
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return configMemory[pos] | (configMemory[pos + 1] << 8) |
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(configMemory[pos + 2] << 16) | (configMemory[pos + 3] << 24);
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}
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static inline uint16_t getWordFromConfig(uint32_t pos, uint8_t *configMem) {
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return configMem[pos] | (configMem[pos + 1] << 8);
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}
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static inline uint8_t getByteFromConfig(uint32_t pos, uint8_t *configMem) {
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return configMem[pos];
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}
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};
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} // namespace L0
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