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9e52684f5b
Change-Id: If965c79d70392db26597aea4c2f3b7ae2820fe96 Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
55 lines
1.7 KiB
C++
55 lines
1.7 KiB
C++
/*
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* Copyright (C) 2017-2019 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "runtime/helpers/hw_info.h"
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#include "runtime/os_interface/hw_info_config.h"
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namespace NEO {
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template <>
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int HwInfoConfigHw<IGFX_BROADWELL>::configureHardwareCustom(HardwareInfo *hwInfo, OSInterface *osIface) {
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FeatureTable *pSkuTable = const_cast<FeatureTable *>(hwInfo->pSkuTable);
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GT_SYSTEM_INFO *pSysInfo = const_cast<GT_SYSTEM_INFO *>(hwInfo->pSysInfo);
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WorkaroundTable *pWaTable = const_cast<WorkaroundTable *>(hwInfo->pWaTable);
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// There is no interface to read total slice count from drm/i915, so we
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// derive this from the number of EUs and subslices.
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// otherwise there is one slice.
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if (pSysInfo->SubSliceCount > 3) {
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pSysInfo->SliceCount = 2;
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} else {
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pSysInfo->SliceCount = 1;
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}
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pSkuTable->ftrPPGTT = true;
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pSkuTable->ftrSVM = true;
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pSkuTable->ftrL3IACoherency = true;
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pSkuTable->ftrIA32eGfxPTEs = true;
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pSkuTable->ftrFbc = true;
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pSkuTable->ftrFbc2AddressTranslation = true;
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pSkuTable->ftrFbcBlitterTracking = true;
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pSkuTable->ftrFbcCpuTracking = true;
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pSkuTable->ftrTileY = true;
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pWaTable->waDisableLSQCROPERFforOCL = true;
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pWaTable->waReportPerfCountUseGlobalContextID = true;
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pWaTable->waUseVAlign16OnTileXYBpp816 = true;
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pWaTable->waModifyVFEStateAfterGPGPUPreemption = true;
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pWaTable->waSamplerCacheFlushBetweenRedescribedSurfaceReads = true;
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if (hwInfo->pPlatform->usDeviceID == IBDW_GT3_HALO_MOBL_DEVICE_F0_ID ||
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hwInfo->pPlatform->usDeviceID == IBDW_GT3_SERV_DEVICE_F0_ID) {
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pSysInfo->EdramSizeInKb = 128 * 1024;
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}
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return 0;
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}
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template class HwInfoConfigHw<IGFX_BROADWELL>;
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} // namespace NEO
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