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https://github.com/intel/compute-runtime.git
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186 lines
7.1 KiB
C++
186 lines
7.1 KiB
C++
/*
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* Copyright (C) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "shared/source/command_container/command_encoder.h"
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#include "shared/source/helpers/register_offsets.h"
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#include "opencl/test/unit_test/fixtures/device_fixture.h"
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#include "opencl/test/unit_test/gen_common/gen_cmd_parse.h"
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#include "test.h"
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using namespace NEO;
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using EncodeMathMMIOTest = testing::Test;
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HWTEST_F(EncodeMathMMIOTest, encodeAluAddHasCorrectOpcodesOperands) {
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using MI_MATH_ALU_INST_INLINE = typename FamilyType::MI_MATH_ALU_INST_INLINE;
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MI_MATH_ALU_INST_INLINE aluParam[5];
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uint32_t regA = ALU_REGISTER_R_0;
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uint32_t regB = ALU_REGISTER_R_1;
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memset(aluParam, 0, sizeof(MI_MATH_ALU_INST_INLINE) * 5);
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EncodeMathMMIO<FamilyType>::encodeAluAdd(aluParam, regA, regB);
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EXPECT_EQ(aluParam[0].DW0.BitField.ALUOpcode, ALU_OPCODE_LOAD);
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EXPECT_EQ(aluParam[0].DW0.BitField.Operand1, ALU_REGISTER_R_SRCA);
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EXPECT_EQ(aluParam[0].DW0.BitField.Operand2, regA);
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EXPECT_EQ(aluParam[1].DW0.BitField.ALUOpcode, ALU_OPCODE_LOAD);
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EXPECT_EQ(aluParam[1].DW0.BitField.Operand1, ALU_REGISTER_R_SRCB);
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EXPECT_EQ(aluParam[1].DW0.BitField.Operand2, regB);
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EXPECT_EQ(aluParam[2].DW0.BitField.ALUOpcode, ALU_OPCODE_ADD);
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EXPECT_EQ(aluParam[2].DW0.BitField.Operand1, 0u);
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EXPECT_EQ(aluParam[2].DW0.BitField.Operand2, 0u);
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EXPECT_EQ(aluParam[3].DW0.BitField.ALUOpcode, ALU_OPCODE_STORE);
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EXPECT_EQ(aluParam[3].DW0.BitField.Operand1, ALU_REGISTER_R_0);
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EXPECT_EQ(aluParam[3].DW0.BitField.Operand2, ALU_REGISTER_R_ACCU);
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EXPECT_EQ(aluParam[4].DW0.Value, 0u);
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}
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HWTEST_F(EncodeMathMMIOTest, encodeAluSubStoreCarryHasCorrectOpcodesOperands) {
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using MI_MATH_ALU_INST_INLINE = typename FamilyType::MI_MATH_ALU_INST_INLINE;
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MI_MATH_ALU_INST_INLINE aluParam[5];
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uint32_t regA = ALU_REGISTER_R_0;
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uint32_t regB = ALU_REGISTER_R_1;
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uint32_t finalResultRegister = ALU_REGISTER_R_2;
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memset(aluParam, 0, sizeof(MI_MATH_ALU_INST_INLINE) * 5);
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EncodeMathMMIO<FamilyType>::encodeAluSubStoreCarry(aluParam, regA, regB,
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finalResultRegister);
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EXPECT_EQ(aluParam[0].DW0.BitField.ALUOpcode, ALU_OPCODE_LOAD);
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EXPECT_EQ(aluParam[0].DW0.BitField.Operand1, ALU_REGISTER_R_SRCA);
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EXPECT_EQ(aluParam[0].DW0.BitField.Operand2, regA);
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EXPECT_EQ(aluParam[1].DW0.BitField.ALUOpcode, ALU_OPCODE_LOAD);
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EXPECT_EQ(aluParam[1].DW0.BitField.Operand1, ALU_REGISTER_R_SRCB);
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EXPECT_EQ(aluParam[1].DW0.BitField.Operand2, regB);
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EXPECT_EQ(aluParam[2].DW0.BitField.ALUOpcode, ALU_OPCODE_SUB);
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EXPECT_EQ(aluParam[2].DW0.BitField.Operand1, 0u);
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EXPECT_EQ(aluParam[2].DW0.BitField.Operand2, 0u);
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EXPECT_EQ(aluParam[3].DW0.BitField.ALUOpcode, ALU_OPCODE_STORE);
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EXPECT_EQ(aluParam[3].DW0.BitField.Operand1, ALU_REGISTER_R_2);
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EXPECT_EQ(aluParam[3].DW0.BitField.Operand2, ALU_REGISTER_R_CF);
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EXPECT_EQ(aluParam[4].DW0.Value, 0u);
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}
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using CommandEncoderMathTest = Test<DeviceFixture>;
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HWTEST_F(CommandEncoderMathTest, appendsAGreaterThanPredicate) {
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using MI_LOAD_REGISTER_MEM = typename FamilyType::MI_LOAD_REGISTER_MEM;
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using MI_LOAD_REGISTER_IMM = typename FamilyType::MI_LOAD_REGISTER_IMM;
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using MI_LOAD_REGISTER_REG = typename FamilyType::MI_LOAD_REGISTER_REG;
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using MI_MATH = typename FamilyType::MI_MATH;
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using MI_MATH_ALU_INST_INLINE = typename FamilyType::MI_MATH_ALU_INST_INLINE;
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CommandContainer cmdContainer;
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cmdContainer.initialize(pDevice);
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EncodeMathMMIO<FamilyType>::encodeGreaterThanPredicate(cmdContainer, 0xDEADBEEFCAF0u, 17u);
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GenCmdList commands;
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CmdParse<FamilyType>::parseCommandBuffer(commands, ptrOffset(cmdContainer.getCommandStream()->getCpuBase(), 0), cmdContainer.getCommandStream()->getUsed());
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auto itor = commands.begin();
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itor = find<MI_LOAD_REGISTER_IMM *>(itor, commands.end());
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ASSERT_NE(itor, commands.end());
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auto cmdIMM = genCmdCast<MI_LOAD_REGISTER_IMM *>(*itor);
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EXPECT_EQ(cmdIMM->getRegisterOffset(), CS_GPR_R0);
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EXPECT_EQ(cmdIMM->getDataDword(), 17u);
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itor = find<MI_LOAD_REGISTER_MEM *>(itor, commands.end());
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ASSERT_NE(itor, commands.end());
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auto cmdMEM = genCmdCast<MI_LOAD_REGISTER_MEM *>(*itor);
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EXPECT_EQ(cmdMEM->getRegisterAddress(), CS_GPR_R1);
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EXPECT_EQ(cmdMEM->getMemoryAddress(), 0xDEADBEEFCAF0u);
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itor = find<MI_MATH *>(itor, commands.end());
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ASSERT_NE(itor, commands.end());
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auto cmdMATH = genCmdCast<MI_MATH *>(*itor);
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EXPECT_EQ(cmdMATH->DW0.BitField.DwordLength, 3u);
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itor = find<MI_LOAD_REGISTER_REG *>(itor, commands.end());
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ASSERT_NE(itor, commands.end());
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auto cmdREG = genCmdCast<MI_LOAD_REGISTER_REG *>(*itor);
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EXPECT_EQ(cmdREG->getSourceRegisterAddress(), CS_GPR_R2);
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EXPECT_EQ(cmdREG->getDestinationRegisterAddress(), CS_PREDICATE_RESULT);
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auto cmdALU = reinterpret_cast<MI_MATH_ALU_INST_INLINE *>(cmdMATH + 3);
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EXPECT_EQ(cmdALU->DW0.BitField.ALUOpcode, ALU_OPCODE_SUB);
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}
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HWTEST_F(CommandEncoderMathTest, setGroupSizeIndirect) {
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using MI_MATH = typename FamilyType::MI_MATH;
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using MI_MATH_ALU_INST_INLINE = typename FamilyType::MI_MATH_ALU_INST_INLINE;
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using MI_STORE_REGISTER_MEM = typename FamilyType::MI_STORE_REGISTER_MEM;
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CommandContainer cmdContainer;
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cmdContainer.initialize(pDevice);
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uint32_t offsets[3] = {0, sizeof(uint32_t), 2 * sizeof(uint32_t)};
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uint32_t crossThreadAdress[3] = {};
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uint32_t lws[3] = {2, 1, 1};
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EncodeIndirectParams<FamilyType>::setGroupSizeIndirect(cmdContainer, offsets, crossThreadAdress, lws);
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GenCmdList commands;
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CmdParse<FamilyType>::parseCommandBuffer(commands, ptrOffset(cmdContainer.getCommandStream()->getCpuBase(), 0), cmdContainer.getCommandStream()->getUsed());
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auto itor = commands.begin();
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itor = find<MI_MATH *>(itor, commands.end());
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ASSERT_NE(itor, commands.end());
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itor = find<MI_STORE_REGISTER_MEM *>(itor, commands.end());
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ASSERT_NE(itor, commands.end());
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}
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HWTEST_F(CommandEncoderMathTest, setGroupCountIndirect) {
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using MI_MATH = typename FamilyType::MI_MATH;
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using MI_MATH_ALU_INST_INLINE = typename FamilyType::MI_MATH_ALU_INST_INLINE;
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using MI_STORE_REGISTER_MEM = typename FamilyType::MI_STORE_REGISTER_MEM;
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CommandContainer cmdContainer;
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cmdContainer.initialize(pDevice);
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uint32_t offsets[3] = {0, sizeof(uint32_t), 2 * sizeof(uint32_t)};
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uint32_t crossThreadAdress[3] = {};
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EncodeIndirectParams<FamilyType>::setGroupCountIndirect(cmdContainer, offsets, crossThreadAdress);
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GenCmdList commands;
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CmdParse<FamilyType>::parseCommandBuffer(commands, ptrOffset(cmdContainer.getCommandStream()->getCpuBase(), 0), cmdContainer.getCommandStream()->getUsed());
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auto itor = commands.begin();
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itor = find<MI_STORE_REGISTER_MEM *>(itor, commands.end());
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ASSERT_NE(itor, commands.end());
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itor = find<MI_STORE_REGISTER_MEM *>(++itor, commands.end());
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ASSERT_NE(itor, commands.end());
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itor = find<MI_STORE_REGISTER_MEM *>(++itor, commands.end());
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ASSERT_NE(itor, commands.end());
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itor = find<MI_STORE_REGISTER_MEM *>(++itor, commands.end());
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ASSERT_EQ(itor, commands.end());
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}
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