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https://github.com/intel/compute-runtime.git
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ed0c36117e
The default TG dispatch size can be changed to a better value based on number of threads in TG or currently available amount of threads on GPU. Decision on what TG dispatch size should be are based on implemented heuristics. Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com> Related-To: NEO-6989
77 lines
3.5 KiB
C++
77 lines
3.5 KiB
C++
/*
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* Copyright (C) 2021-2022 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#include "shared/source/command_container/cmdcontainer.h"
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#include "shared/source/command_container/command_encoder.h"
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#include "shared/source/os_interface/hw_info_config.h"
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#include "shared/test/common/fixtures/device_fixture.h"
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#include "shared/test/common/helpers/debug_manager_state_restore.h"
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#include "shared/test/common/test_macros/hw_test.h"
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using namespace NEO;
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using DG2CommandEncoderTest = Test<DeviceFixture>;
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HWTEST_EXCLUDE_PRODUCT(XeHPAndLaterCommandEncoderTest, whenGettingRequiredSizeForStateBaseAddressCommandThenCorrectSizeIsReturned_IsAtLeastXeHpCore, IGFX_DG2);
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HWTEST_EXCLUDE_PRODUCT(CommandEncoderTest, whenGettingRequiredSizeForStateBaseAddressCommandThenCorrectSizeIsReturned_Platforms, IGFX_DG2);
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HWTEST_EXCLUDE_PRODUCT(XeHPAndLaterCommandEncoderTest, givenCommandContainerWithDirtyHeapWhenGettingRequiredSizeForStateBaseAddressCommandThenCorrectSizeIsReturned_IsAtLeastXeHpCore, IGFX_DG2);
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HWTEST2_F(DG2CommandEncoderTest, givenDG2WhenGettingRequiredSizeForStateBaseAddressCommandThenCorrectSizeIsReturned, IsDG2) {
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class MockCommandContainer : public CommandContainer {
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public:
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MockCommandContainer() : CommandContainer() {}
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void clearHeaps() {
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dirtyHeaps = 0;
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}
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};
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auto container = MockCommandContainer();
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container.clearHeaps();
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size_t size = EncodeStateBaseAddress<FamilyType>::getRequiredSizeForStateBaseAddress(*pDevice, container);
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EXPECT_EQ(size, 176ul);
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}
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HWTEST2_F(DG2CommandEncoderTest, givenDG2AndCommandContainerWithDirtyHeapWhenGettingRequiredSizeForStateBaseAddressCommandThenCorrectSizeIsReturned, IsDG2) {
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auto container = CommandContainer();
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container.setHeapDirty(HeapType::SURFACE_STATE);
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size_t size = EncodeStateBaseAddress<FamilyType>::getRequiredSizeForStateBaseAddress(*pDevice, container);
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EXPECT_EQ(size, 192ul);
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}
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HWTEST2_F(DG2CommandEncoderTest, givenInterfaceDescriptorDataWhenForceThreadGroupDispatchSizeVariableIsDefaultThenThreadGroupDispatchSizeIsNotChanged, IsDG2) {
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using INTERFACE_DESCRIPTOR_DATA = typename FamilyType::INTERFACE_DESCRIPTOR_DATA;
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INTERFACE_DESCRIPTOR_DATA iddArg;
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iddArg = FamilyType::cmdInitInterfaceDescriptorData;
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const uint32_t forceThreadGroupDispatchSize = -1;
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auto hwInfo = pDevice->getHardwareInfo();
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const auto &hwInfoConfig = *HwInfoConfig::get(productFamily);
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DebugManagerStateRestore restorer;
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DebugManager.flags.ForceThreadGroupDispatchSize.set(forceThreadGroupDispatchSize);
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uint32_t revisions[] = {REVISION_A0, REVISION_B};
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for (auto revision : revisions) {
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hwInfo.platform.usRevId = hwInfoConfig.getHwRevIdFromStepping(revision, hwInfo);
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for (auto numberOfThreadsInGroup : {1u, 4u, 16u}) {
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iddArg.setNumberOfThreadsInGpgpuThreadGroup(numberOfThreadsInGroup);
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EncodeDispatchKernel<FamilyType>::adjustInterfaceDescriptorData(iddArg, hwInfo, 0, 0);
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if (hwInfoConfig.isDisableOverdispatchAvailable(hwInfo)) {
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if (numberOfThreadsInGroup == 1) {
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EXPECT_EQ(INTERFACE_DESCRIPTOR_DATA::THREAD_GROUP_DISPATCH_SIZE_TG_SIZE_2, iddArg.getThreadGroupDispatchSize());
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} else {
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EXPECT_EQ(INTERFACE_DESCRIPTOR_DATA::THREAD_GROUP_DISPATCH_SIZE_TG_SIZE_1, iddArg.getThreadGroupDispatchSize());
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}
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} else {
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EXPECT_EQ(INTERFACE_DESCRIPTOR_DATA::THREAD_GROUP_DISPATCH_SIZE_TG_SIZE_8, iddArg.getThreadGroupDispatchSize());
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}
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}
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}
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}
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