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7ada522fa2
Related-To: NEO-4344 Change-Id: I356b46bdfac7c943b95ee6dc41d3416bd880f9cb Signed-off-by: Konstanty Misiak <konstanty.misiak@intel.com>
50 lines
1.1 KiB
C++
50 lines
1.1 KiB
C++
/*
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* Copyright (C) 2018-2020 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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*/
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#pragma once
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#include "shared/source/helpers/preamble.h"
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namespace NEO {
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struct ICLFamily;
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template <>
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struct L3CNTLREGConfig<IGFX_ICELAKE_LP> {
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static const uint32_t valueForSLM = 0xA0000720u;
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static const uint32_t valueForNoSLM = 0xA0000720u;
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};
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template <>
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struct L3CNTLRegisterOffset<ICLFamily> {
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static const uint32_t registerOffset = 0x7034;
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};
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template <>
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struct DebugModeRegisterOffset<ICLFamily> {
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enum {
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registerOffset = 0x20d8,
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debugEnabledValue = (1 << 5) | (1 << 21)
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};
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};
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namespace gen11HdcModeRegister {
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const uint32_t address = 0xE5F4;
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const uint32_t forceNonCoherentEnableBit = 4;
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} // namespace gen11HdcModeRegister
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namespace gen11PowerClockStateRegister {
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const uint32_t address = 0x20C8;
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const uint32_t minEuCountShift = 0;
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const uint32_t maxEuCountShift = 4;
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const uint32_t subSliceCountShift = 8;
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const uint32_t sliceCountShift = 12;
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const uint32_t vmeSliceCount = 1;
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const uint32_t enabledValue = 0x80040800u;
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const uint32_t disabledValue = 0x80040800u;
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} // namespace gen11PowerClockStateRegister
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} // namespace NEO
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