Files
compute-runtime/shared/source/helpers/compiler_hw_info_config_base.inl
Compute-Runtime-Validation 2621460e80 Revert "Change DG2 l1 cache policy to WB"
This reverts commit a820e73dd7.

Signed-off-by: Compute-Runtime-Validation <compute-runtime-validation@intel.com>
2022-08-27 08:04:19 +02:00

34 lines
864 B
C++

/*
* Copyright (C) 2021-2022 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "shared/source/helpers/cache_policy.h"
#include "shared/source/helpers/compiler_hw_info_config.h"
namespace NEO {
template <PRODUCT_FAMILY gfxProduct>
bool CompilerHwInfoConfigHw<gfxProduct>::isForceEmuInt32DivRemSPRequired() const {
return false;
}
template <PRODUCT_FAMILY gfxProduct>
bool CompilerHwInfoConfigHw<gfxProduct>::isStatelessToStatefulBufferOffsetSupported() const {
return true;
}
template <PRODUCT_FAMILY gfxProduct>
void CompilerHwInfoConfigHw<gfxProduct>::adjustHwInfoForIgc(HardwareInfo &hwInfo) const {
}
template <PRODUCT_FAMILY gfxProduct>
const char *CompilerHwInfoConfigHw<gfxProduct>::getCachingPolicyOptions() const {
return L1CachePolicyHelper<gfxProduct>::getCachingPolicyOptions();
};
} // namespace NEO