Cleanup SuperVectorization dialect printing and parsing.
On the read side,
```
%3 = vector_transfer_read %arg0, %i2, %i1, %i0 {permutation_map: (d0, d1, d2)->(d2, d0)} : (memref<?x?x?xf32>, index, index, index) -> vector<32x256xf32>
```
becomes:
```
%3 = vector_transfer_read %arg0[%i2, %i1, %i0] {permutation_map: (d0, d1, d2)->(d2, d0)} : memref<?x?x?xf32>, vector<32x256xf32>
```
On the write side,
```
vector_transfer_write %0, %arg0, %c3, %c3 {permutation_map: (d0, d1)->(d0)} : vector<128xf32>, memref<?x?xf32>, index, index
```
becomes
```
vector_transfer_write %0, %arg0[%c3, %c3] {permutation_map: (d0, d1)->(d0)} : vector<128xf32>, memref<?x?xf32>
```
Documentation will be cleaned up in a followup commit that also extracts a proper .md from the top of the file comments.
PiperOrigin-RevId: 241021879
2019-03-29 11:48:20 -07:00
|
|
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//===- VectorOps.cpp - MLIR Super Vectorizer Operations -------------------===//
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2018-12-14 09:31:17 -08:00
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//
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2020-01-26 03:58:30 +00:00
|
|
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
2019-12-23 09:35:36 -08:00
|
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
2018-12-14 09:31:17 -08:00
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//
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2019-12-23 09:35:36 -08:00
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//===----------------------------------------------------------------------===//
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2018-12-14 09:31:17 -08:00
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//
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|
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// This file implements convenience types for working with super-vectorization
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// operations, in particular super-vector loads and stores.
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//
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//===----------------------------------------------------------------------===//
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2019-08-19 17:11:12 -07:00
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#include "mlir/Dialect/VectorOps/VectorOps.h"
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2019-12-04 13:00:14 -08:00
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#include "mlir/Dialect/StandardOps/Ops.h"
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2019-12-09 11:00:53 -08:00
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#include "mlir/Dialect/Utils/StructuredOpsUtils.h"
|
[mlir] [VectorOps] consolidate all vector utilities to one header/cc file
Reviewers: nicolasvasilache, andydavis1, dcaballe
Reviewed By: andydavis1, dcaballe
Subscribers: dcaballe, merge_guards_bot, mgorny, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, liufengdb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73593
2020-01-29 15:21:30 -08:00
|
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#include "mlir/Dialect/VectorOps/VectorUtils.h"
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2018-12-14 09:31:17 -08:00
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#include "mlir/IR/AffineExpr.h"
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#include "mlir/IR/AffineMap.h"
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#include "mlir/IR/Builders.h"
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#include "mlir/IR/OpImplementation.h"
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2019-12-04 13:00:14 -08:00
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#include "mlir/IR/PatternMatch.h"
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2019-08-09 05:58:19 -07:00
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#include "mlir/IR/TypeUtilities.h"
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2019-11-25 15:36:45 -08:00
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#include "mlir/Support/Functional.h"
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2018-12-14 09:31:17 -08:00
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#include "mlir/Support/LLVM.h"
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2019-12-16 06:38:33 -08:00
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#include "mlir/Support/MathExtras.h"
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#include "mlir/Support/STLExtras.h"
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2019-11-25 12:39:30 -08:00
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#include "llvm/ADT/StringSet.h"
|
[mlir][VectorOps] Add ShapeCastOp to the vector ops dialect.
Summary:
Add ShapeCastOp to the vector ops dialect.
The shape_cast operation casts between an n-D source vector shape and a k-D result vector shape (the element type remains the same).
Reviewers: nicolasvasilache, aartbik
Reviewed By: nicolasvasilache
Subscribers: Joonsoo, merge_guards_bot, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, liufengdb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73635
2020-02-05 15:35:50 -08:00
|
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#include <numeric>
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2019-08-09 05:58:19 -07:00
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2018-12-14 09:31:17 -08:00
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using namespace mlir;
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2019-08-09 05:58:19 -07:00
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using namespace mlir::vector;
|
2018-12-14 09:31:17 -08:00
|
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|
|
|
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//===----------------------------------------------------------------------===//
|
Cleanup SuperVectorization dialect printing and parsing.
On the read side,
```
%3 = vector_transfer_read %arg0, %i2, %i1, %i0 {permutation_map: (d0, d1, d2)->(d2, d0)} : (memref<?x?x?xf32>, index, index, index) -> vector<32x256xf32>
```
becomes:
```
%3 = vector_transfer_read %arg0[%i2, %i1, %i0] {permutation_map: (d0, d1, d2)->(d2, d0)} : memref<?x?x?xf32>, vector<32x256xf32>
```
On the write side,
```
vector_transfer_write %0, %arg0, %c3, %c3 {permutation_map: (d0, d1)->(d0)} : vector<128xf32>, memref<?x?xf32>, index, index
```
becomes
```
vector_transfer_write %0, %arg0[%c3, %c3] {permutation_map: (d0, d1)->(d0)} : vector<128xf32>, memref<?x?xf32>
```
Documentation will be cleaned up in a followup commit that also extracts a proper .md from the top of the file comments.
PiperOrigin-RevId: 241021879
2019-03-29 11:48:20 -07:00
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// VectorOpsDialect
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2018-12-14 09:31:17 -08:00
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//===----------------------------------------------------------------------===//
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2019-12-13 12:21:42 -08:00
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VectorOpsDialect::VectorOpsDialect(MLIRContext *context)
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2019-08-09 05:58:19 -07:00
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: Dialect(getDialectNamespace(), context) {
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addOperations<
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#define GET_OP_LIST
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2019-08-19 17:11:12 -07:00
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#include "mlir/Dialect/VectorOps/VectorOps.cpp.inc"
|
2019-08-09 05:58:19 -07:00
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>();
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}
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2019-12-13 12:21:42 -08:00
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/// Materialize a single constant operation from a given attribute value with
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/// the desired resultant type.
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Operation *VectorOpsDialect::materializeConstant(OpBuilder &builder,
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Attribute value, Type type,
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Location loc) {
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return builder.create<ConstantOp>(loc, type, value);
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}
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2019-12-19 11:47:45 -08:00
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IntegerType vector::getVectorSubscriptType(Builder &builder) {
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2019-12-20 15:32:31 -08:00
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return builder.getIntegerType(64);
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2019-12-19 11:47:45 -08:00
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}
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ArrayAttr vector::getVectorSubscriptAttr(Builder &builder,
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2019-12-20 15:32:31 -08:00
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ArrayRef<int64_t> values) {
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return builder.getI64ArrayAttr(values);
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2019-12-19 11:47:45 -08:00
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}
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2019-11-20 14:43:15 -08:00
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//===----------------------------------------------------------------------===//
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2019-11-22 07:52:02 -08:00
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// ContractionOp
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2019-11-20 14:43:15 -08:00
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//===----------------------------------------------------------------------===//
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2019-12-09 09:14:05 -08:00
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void vector::ContractionOp::build(Builder *builder, OperationState &result,
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2019-12-23 14:45:01 -08:00
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Value lhs, Value rhs, Value acc,
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2019-12-09 09:14:05 -08:00
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ArrayAttr indexingMaps,
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ArrayAttr iteratorTypes) {
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result.addOperands({lhs, rhs, acc});
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2020-01-11 08:54:04 -08:00
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result.addTypes(acc.getType());
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2019-12-09 09:14:05 -08:00
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result.addAttribute(getIndexingMapsAttrName(), indexingMaps);
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result.addAttribute(getIteratorTypesAttrName(), iteratorTypes);
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}
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2019-11-22 07:52:02 -08:00
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static ParseResult parseContractionOp(OpAsmParser &parser,
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OperationState &result) {
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2019-11-20 14:43:15 -08:00
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OpAsmParser::OperandType lhsInfo;
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OpAsmParser::OperandType rhsInfo;
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OpAsmParser::OperandType accInfo;
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SmallVector<OpAsmParser::OperandType, 2> masksInfo;
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SmallVector<Type, 2> types;
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Type resultVectorType;
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auto loc = parser.getCurrentLocation();
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2019-11-25 12:39:30 -08:00
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DictionaryAttr dictAttr;
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// TODO(andydavis, ntv) Unify linalg op attribute parsing.
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if (parser.parseAttribute(dictAttr, "_", result.attributes) ||
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parser.parseOperand(lhsInfo) || parser.parseComma() ||
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2019-11-20 14:43:15 -08:00
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parser.parseOperand(rhsInfo) || parser.parseComma() ||
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parser.parseOperand(accInfo) ||
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parser.parseTrailingOperandList(masksInfo) ||
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parser.parseOptionalAttrDict(result.attributes) ||
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parser.parseColonTypeList(types) ||
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parser.parseKeywordType("into", resultVectorType) ||
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parser.resolveOperand(lhsInfo, types[0], result.operands) ||
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parser.resolveOperand(rhsInfo, types[1], result.operands) ||
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parser.resolveOperand(accInfo, resultVectorType, result.operands) ||
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parser.addTypeToList(resultVectorType, result.types))
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return failure();
|
2019-11-25 12:39:30 -08:00
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result.attributes.assign(dictAttr.getValue().begin(),
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dictAttr.getValue().end());
|
2019-11-20 14:43:15 -08:00
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if (masksInfo.empty())
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return success();
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if (masksInfo.size() != 2)
|
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return parser.emitError(parser.getNameLoc(),
|
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|
"expected zero or exactly 2 vector mask operands");
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auto lhsType = types[0].cast<VectorType>();
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auto rhsType = types[1].cast<VectorType>();
|
2019-12-06 07:36:55 -08:00
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auto maskElementType = parser.getBuilder().getI1Type();
|
2019-11-20 14:43:15 -08:00
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SmallVector<Type, 2> maskTypes;
|
2019-12-06 07:36:55 -08:00
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maskTypes.push_back(VectorType::get(lhsType.getShape(), maskElementType));
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maskTypes.push_back(VectorType::get(rhsType.getShape(), maskElementType));
|
2019-11-20 14:43:15 -08:00
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if (parser.resolveOperands(masksInfo, maskTypes, loc, result.operands))
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return failure();
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return success();
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}
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2019-11-22 07:52:02 -08:00
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static void print(OpAsmPrinter &p, ContractionOp op) {
|
2019-11-25 12:39:30 -08:00
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|
// TODO(andydavis, ntv) Unify printing code with linalg ops.
|
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auto attrNames = op.getTraitAttrNames();
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llvm::StringSet<> traitAttrsSet;
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traitAttrsSet.insert(attrNames.begin(), attrNames.end());
|
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SmallVector<NamedAttribute, 8> attrs;
|
2019-12-12 15:31:39 -08:00
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for (auto attr : op.getAttrs())
|
2019-11-25 12:39:30 -08:00
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|
if (traitAttrsSet.count(attr.first.strref()) > 0)
|
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attrs.push_back(attr);
|
2019-12-12 15:31:39 -08:00
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|
2019-11-25 12:39:30 -08:00
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|
auto dictAttr = DictionaryAttr::get(attrs, op.getContext());
|
2020-01-11 08:54:04 -08:00
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|
p << op.getOperationName() << " " << dictAttr << " " << op.lhs() << ", ";
|
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|
p << op.rhs() << ", " << op.acc();
|
2019-12-12 15:31:39 -08:00
|
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|
if (op.masks().size() == 2)
|
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|
p << ", " << op.masks();
|
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|
2019-11-25 12:39:30 -08:00
|
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|
p.printOptionalAttrDict(op.getAttrs(), attrNames);
|
2020-01-11 08:54:04 -08:00
|
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|
p << " : " << op.lhs().getType() << ", " << op.rhs().getType() << " into "
|
2019-11-20 14:43:15 -08:00
|
|
|
<< op.getResultType();
|
|
|
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|
}
|
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|
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|
|
static bool verifyDimMap(VectorType lhsType, VectorType rhsType,
|
|
|
|
|
const std::vector<std::pair<int64_t, int64_t>> &map) {
|
|
|
|
|
for (auto &dimPair : map) {
|
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|
|
|
if (dimPair.first < 0 || dimPair.first >= lhsType.getRank() ||
|
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|
dimPair.second < 0 || dimPair.second >= rhsType.getRank() ||
|
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|
lhsType.getDimSize(dimPair.first) != rhsType.getDimSize(dimPair.second))
|
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|
return false;
|
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|
}
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|
return true;
|
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|
}
|
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|
static bool verifyOutputShape(
|
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|
VectorType lhsType, VectorType rhsType, VectorType accType,
|
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|
|
VectorType resType,
|
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|
|
const std::vector<std::pair<int64_t, int64_t>> &contractingDimMap,
|
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|
|
const std::vector<std::pair<int64_t, int64_t>> &batchDimMap) {
|
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|
DenseSet<int64_t> lhsContractingDimSet;
|
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|
|
DenseSet<int64_t> rhsContractingDimSet;
|
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|
|
|
for (auto &dimPair : contractingDimMap) {
|
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|
lhsContractingDimSet.insert(dimPair.first);
|
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|
|
rhsContractingDimSet.insert(dimPair.second);
|
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|
}
|
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|
DenseSet<int64_t> rhsBatchDimSet;
|
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|
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|
for (auto &dimPair : batchDimMap)
|
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|
rhsBatchDimSet.insert(dimPair.second);
|
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|
|
|
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|
// Add free and batch dimensions from 'lhsType' to 'expectedResultDims'.
|
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|
SmallVector<int64_t, 4> expectedResultDims;
|
|
|
|
|
for (int64_t i = 0, e = lhsType.getRank(); i < e; ++i) {
|
|
|
|
|
if (lhsContractingDimSet.count(i) > 0)
|
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|
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|
continue;
|
|
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|
expectedResultDims.push_back(lhsType.getDimSize(i));
|
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|
}
|
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|
|
// Add free dimensions from 'rhsType' to 'expectedResultDims'.
|
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|
for (int64_t i = 0, e = rhsType.getRank(); i < e; ++i) {
|
|
|
|
|
if (rhsContractingDimSet.count(i) > 0 || rhsBatchDimSet.count(i) > 0)
|
|
|
|
|
continue;
|
|
|
|
|
expectedResultDims.push_back(rhsType.getDimSize(i));
|
|
|
|
|
}
|
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|
|
|
|
|
|
|
|
// Verify dimension from 'resType' against 'expectedResultDims'.
|
|
|
|
|
if (resType.getShape().size() != expectedResultDims.size() ||
|
|
|
|
|
accType.getShape().size() != expectedResultDims.size())
|
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|
|
return false;
|
|
|
|
|
for (int64_t i = 0, e = resType.getRank(); i < e; ++i) {
|
|
|
|
|
if (resType.getDimSize(i) != expectedResultDims[i] ||
|
|
|
|
|
accType.getDimSize(i) != expectedResultDims[i])
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2019-11-22 07:52:02 -08:00
|
|
|
static LogicalResult verify(ContractionOp op) {
|
2019-11-20 14:43:15 -08:00
|
|
|
auto lhsType = op.getLhsType();
|
|
|
|
|
auto rhsType = op.getRhsType();
|
|
|
|
|
auto accType = op.getAccType();
|
|
|
|
|
auto resType = op.getResultType();
|
2019-11-25 12:39:30 -08:00
|
|
|
|
|
|
|
|
// Verify that an indexing map was specified for each vector operand.
|
|
|
|
|
if (op.indexing_maps().size() != 3)
|
|
|
|
|
return op.emitOpError("expected an indexing map for each vector operand");
|
|
|
|
|
|
|
|
|
|
// Verify that each index map has 'numIterators' inputs, no symbols, and
|
|
|
|
|
// that the number of map outputs equals the rank of its associated
|
|
|
|
|
// vector operand.
|
|
|
|
|
unsigned numIterators = op.iterator_types().getValue().size();
|
|
|
|
|
for (auto it : llvm::enumerate(op.indexing_maps())) {
|
|
|
|
|
auto index = it.index();
|
|
|
|
|
auto map = it.value().cast<AffineMapAttr>().getValue();
|
|
|
|
|
if (map.getNumSymbols() != 0)
|
|
|
|
|
return op.emitOpError("expected indexing map ")
|
|
|
|
|
<< index << " to have no symbols";
|
|
|
|
|
if (map.getNumDims() != numIterators)
|
|
|
|
|
return op.emitOpError("expected indexing map ")
|
|
|
|
|
<< index << " to have " << numIterators << " number of inputs";
|
2020-01-11 08:54:04 -08:00
|
|
|
auto operandType = op.getOperand(index).getType().cast<VectorType>();
|
2019-11-25 12:39:30 -08:00
|
|
|
unsigned rank = operandType.getShape().size();
|
|
|
|
|
if (map.getNumResults() != rank)
|
|
|
|
|
return op.emitOpError("expected indexing map ")
|
|
|
|
|
<< index << " to have " << rank << " number of outputs";
|
|
|
|
|
if (!map.isProjectedPermutation())
|
|
|
|
|
return op.emitOpError("expected indexing map ")
|
|
|
|
|
<< index << " to be a projected permutation of its inputs";
|
|
|
|
|
}
|
|
|
|
|
|
2019-11-20 14:43:15 -08:00
|
|
|
auto contractingDimMap = op.getContractingDimMap();
|
|
|
|
|
auto batchDimMap = op.getBatchDimMap();
|
|
|
|
|
|
|
|
|
|
// Verify at least one contracting dimension pair was specified.
|
|
|
|
|
if (contractingDimMap.empty())
|
|
|
|
|
return op.emitOpError("expected at least one contracting dimension pair");
|
|
|
|
|
|
|
|
|
|
// Verify contracting dimension map was properly constructed.
|
|
|
|
|
if (!verifyDimMap(lhsType, rhsType, contractingDimMap))
|
|
|
|
|
return op.emitOpError("invalid contracting dimension map");
|
|
|
|
|
|
|
|
|
|
// Verify batch dimension map was properly constructed.
|
|
|
|
|
if (!verifyDimMap(lhsType, rhsType, batchDimMap))
|
|
|
|
|
return op.emitOpError("invalid batch dimension map");
|
|
|
|
|
|
|
|
|
|
// Verify 'accType' and 'resType' shape.
|
|
|
|
|
if (!verifyOutputShape(lhsType, rhsType, accType, resType, contractingDimMap,
|
|
|
|
|
batchDimMap))
|
|
|
|
|
return op.emitOpError("invalid accumulator/result vector shape");
|
|
|
|
|
|
|
|
|
|
// Verify that either two vector masks are set or none are set.
|
|
|
|
|
auto lhsMaskType = op.getLHSVectorMaskType();
|
|
|
|
|
auto rhsMaskType = op.getRHSVectorMaskType();
|
|
|
|
|
if ((lhsMaskType && !rhsMaskType) || (!lhsMaskType && rhsMaskType))
|
|
|
|
|
return op.emitOpError("invalid number of vector masks specified");
|
|
|
|
|
if (lhsMaskType && rhsMaskType) {
|
2019-12-06 07:36:55 -08:00
|
|
|
// Verify mask rank == argument rank.
|
|
|
|
|
if (lhsMaskType.getShape().size() != lhsType.getShape().size() ||
|
|
|
|
|
rhsMaskType.getShape().size() != rhsType.getShape().size())
|
|
|
|
|
return op.emitOpError("invalid vector mask rank");
|
2019-11-20 14:43:15 -08:00
|
|
|
}
|
|
|
|
|
return success();
|
|
|
|
|
}
|
|
|
|
|
|
2019-12-09 09:14:05 -08:00
|
|
|
ArrayRef<StringRef> ContractionOp::getTraitAttrNames() {
|
2019-12-09 11:00:53 -08:00
|
|
|
static constexpr StringLiteral names[2] = {getIndexingMapsAttrName(),
|
|
|
|
|
getIteratorTypesAttrName()};
|
|
|
|
|
ArrayRef<StringLiteral> res{names};
|
|
|
|
|
return ArrayRef<StringRef>{res.begin(), res.end()};
|
2019-11-25 12:39:30 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int64_t getResultIndex(AffineMap map, AffineExpr targetExpr) {
|
|
|
|
|
for (int64_t i = 0, e = map.getNumResults(); i < e; ++i)
|
|
|
|
|
if (targetExpr == map.getResult(i))
|
|
|
|
|
return i;
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static std::vector<std::pair<int64_t, int64_t>>
|
|
|
|
|
getDimMap(ArrayRef<AffineMap> indexingMaps, ArrayAttr iteratorTypes,
|
|
|
|
|
StringRef targetIteratorTypeName, MLIRContext *context) {
|
2019-11-20 14:43:15 -08:00
|
|
|
std::vector<std::pair<int64_t, int64_t>> dimMap;
|
2019-11-25 12:39:30 -08:00
|
|
|
for (auto it : llvm::enumerate(iteratorTypes)) {
|
|
|
|
|
auto iteratorTypeName = it.value().cast<StringAttr>().getValue();
|
|
|
|
|
if (iteratorTypeName != targetIteratorTypeName)
|
|
|
|
|
continue;
|
|
|
|
|
// Search lhs/rhs map results for 'targetExpr'.
|
|
|
|
|
auto targetExpr = getAffineDimExpr(it.index(), context);
|
|
|
|
|
int64_t lhsDim = getResultIndex(indexingMaps[0], targetExpr);
|
|
|
|
|
int64_t rhsDim = getResultIndex(indexingMaps[1], targetExpr);
|
|
|
|
|
if (lhsDim >= 0 && rhsDim >= 0)
|
|
|
|
|
dimMap.push_back({lhsDim, rhsDim});
|
2019-11-20 14:43:15 -08:00
|
|
|
}
|
|
|
|
|
return dimMap;
|
|
|
|
|
}
|
|
|
|
|
|
2019-12-04 06:53:07 -08:00
|
|
|
void ContractionOp::getIterationBounds(
|
|
|
|
|
SmallVectorImpl<int64_t> &iterationBounds) {
|
|
|
|
|
auto lhsShape = getLhsType().getShape();
|
|
|
|
|
auto resShape = getResultType().getShape();
|
|
|
|
|
SmallVector<AffineMap, 4> indexingMaps(getIndexingMaps());
|
|
|
|
|
SmallVector<int64_t, 2> iterationShape;
|
|
|
|
|
for (auto it : llvm::enumerate(iterator_types())) {
|
|
|
|
|
// Search lhs/rhs map results for 'targetExpr'.
|
|
|
|
|
auto targetExpr = getAffineDimExpr(it.index(), getContext());
|
|
|
|
|
auto iteratorTypeName = it.value().cast<StringAttr>().getValue();
|
|
|
|
|
if (iteratorTypeName == getReductionIteratorTypeName()) {
|
|
|
|
|
// Get reduction dim size from lhs shape (same size in rhsShape).
|
|
|
|
|
int64_t lhsDimIndex = getResultIndex(indexingMaps[0], targetExpr);
|
|
|
|
|
assert(lhsDimIndex >= 0);
|
|
|
|
|
iterationBounds.push_back(lhsShape[lhsDimIndex]);
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
// Get parallel dimension size from result shape.
|
|
|
|
|
int64_t resDimIndex = getResultIndex(indexingMaps[2], targetExpr);
|
|
|
|
|
assert(resDimIndex >= 0);
|
|
|
|
|
iterationBounds.push_back(resShape[resDimIndex]);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ContractionOp::getIterationIndexMap(
|
|
|
|
|
std::vector<DenseMap<int64_t, int64_t>> &iterationIndexMap) {
|
|
|
|
|
unsigned numMaps = indexing_maps().getValue().size();
|
|
|
|
|
iterationIndexMap.resize(numMaps);
|
|
|
|
|
for (auto it : llvm::enumerate(indexing_maps())) {
|
|
|
|
|
auto index = it.index();
|
|
|
|
|
auto map = it.value().cast<AffineMapAttr>().getValue();
|
|
|
|
|
for (unsigned i = 0, e = map.getNumResults(); i < e; ++i) {
|
|
|
|
|
auto dim = map.getResult(i).cast<AffineDimExpr>();
|
|
|
|
|
iterationIndexMap[index][dim.getPosition()] = i;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2019-11-22 07:52:02 -08:00
|
|
|
std::vector<std::pair<int64_t, int64_t>> ContractionOp::getContractingDimMap() {
|
2019-11-25 12:39:30 -08:00
|
|
|
SmallVector<AffineMap, 4> indexingMaps(getIndexingMaps());
|
|
|
|
|
return getDimMap(indexingMaps, iterator_types(),
|
|
|
|
|
getReductionIteratorTypeName(), getContext());
|
2019-11-20 14:43:15 -08:00
|
|
|
}
|
|
|
|
|
|
2019-11-22 07:52:02 -08:00
|
|
|
std::vector<std::pair<int64_t, int64_t>> ContractionOp::getBatchDimMap() {
|
2019-11-25 12:39:30 -08:00
|
|
|
SmallVector<AffineMap, 4> indexingMaps(getIndexingMaps());
|
|
|
|
|
return getDimMap(indexingMaps, iterator_types(),
|
|
|
|
|
getParallelIteratorTypeName(), getContext());
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
SmallVector<AffineMap, 4> ContractionOp::getIndexingMaps() {
|
|
|
|
|
SmallVector<AffineMap, 4> res;
|
|
|
|
|
auto mapAttrs = indexing_maps().getValue();
|
|
|
|
|
res.reserve(mapAttrs.size());
|
|
|
|
|
for (auto mapAttr : mapAttrs)
|
|
|
|
|
res.push_back(mapAttr.cast<AffineMapAttr>().getValue());
|
|
|
|
|
return res;
|
2019-11-20 14:43:15 -08:00
|
|
|
}
|
|
|
|
|
|
2019-12-16 09:52:13 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// ExtractElementOp
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
static void print(OpAsmPrinter &p, vector::ExtractElementOp op) {
|
2020-01-11 08:54:04 -08:00
|
|
|
p << op.getOperationName() << " " << op.vector() << "[" << op.position()
|
|
|
|
|
<< " : " << op.position().getType() << "]";
|
2019-12-16 09:52:13 -08:00
|
|
|
p.printOptionalAttrDict(op.getAttrs());
|
2020-01-11 08:54:04 -08:00
|
|
|
p << " : " << op.vector().getType();
|
2019-12-16 09:52:13 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static ParseResult parseExtractElementOp(OpAsmParser &parser,
|
|
|
|
|
OperationState &result) {
|
|
|
|
|
OpAsmParser::OperandType vector, position;
|
|
|
|
|
Type positionType;
|
|
|
|
|
VectorType vectorType;
|
|
|
|
|
if (parser.parseOperand(vector) || parser.parseLSquare() ||
|
|
|
|
|
parser.parseOperand(position) || parser.parseColonType(positionType) ||
|
|
|
|
|
parser.parseRSquare() ||
|
|
|
|
|
parser.parseOptionalAttrDict(result.attributes) ||
|
|
|
|
|
parser.parseColonType(vectorType))
|
|
|
|
|
return failure();
|
|
|
|
|
Type resultType = vectorType.getElementType();
|
|
|
|
|
return failure(
|
|
|
|
|
parser.resolveOperand(vector, vectorType, result.operands) ||
|
|
|
|
|
parser.resolveOperand(position, positionType, result.operands) ||
|
|
|
|
|
parser.addTypeToList(resultType, result.types));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static LogicalResult verify(vector::ExtractElementOp op) {
|
|
|
|
|
VectorType vectorType = op.getVectorType();
|
|
|
|
|
if (vectorType.getRank() != 1)
|
|
|
|
|
return op.emitOpError("expected 1-D vector");
|
|
|
|
|
return success();
|
|
|
|
|
}
|
|
|
|
|
|
2019-08-09 05:58:19 -07:00
|
|
|
//===----------------------------------------------------------------------===//
|
2019-12-06 12:38:52 -08:00
|
|
|
// ExtractOp
|
2019-08-09 05:58:19 -07:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2019-12-06 12:38:52 -08:00
|
|
|
static Type inferExtractOpResultType(VectorType vectorType,
|
|
|
|
|
ArrayAttr position) {
|
2019-11-18 10:38:35 -08:00
|
|
|
if (static_cast<int64_t>(position.size()) == vectorType.getRank())
|
|
|
|
|
return vectorType.getElementType();
|
|
|
|
|
return VectorType::get(vectorType.getShape().drop_front(position.size()),
|
|
|
|
|
vectorType.getElementType());
|
|
|
|
|
}
|
|
|
|
|
|
2019-12-06 12:38:52 -08:00
|
|
|
void vector::ExtractOp::build(Builder *builder, OperationState &result,
|
2019-12-23 14:45:01 -08:00
|
|
|
Value source, ArrayRef<int64_t> position) {
|
2019-11-18 10:38:35 -08:00
|
|
|
result.addOperands(source);
|
2019-12-19 11:47:45 -08:00
|
|
|
auto positionAttr = getVectorSubscriptAttr(*builder, position);
|
2020-01-11 08:54:04 -08:00
|
|
|
result.addTypes(inferExtractOpResultType(source.getType().cast<VectorType>(),
|
2019-12-06 12:38:52 -08:00
|
|
|
positionAttr));
|
2019-11-18 10:38:35 -08:00
|
|
|
result.addAttribute(getPositionAttrName(), positionAttr);
|
|
|
|
|
}
|
|
|
|
|
|
2019-12-06 12:38:52 -08:00
|
|
|
static void print(OpAsmPrinter &p, vector::ExtractOp op) {
|
2020-01-11 08:54:04 -08:00
|
|
|
p << op.getOperationName() << " " << op.vector() << op.position();
|
2019-09-20 20:43:02 -07:00
|
|
|
p.printOptionalAttrDict(op.getAttrs(), {"position"});
|
2020-01-11 08:54:04 -08:00
|
|
|
p << " : " << op.vector().getType();
|
2019-08-09 05:58:19 -07:00
|
|
|
}
|
|
|
|
|
|
2019-12-06 12:38:52 -08:00
|
|
|
static ParseResult parseExtractOp(OpAsmParser &parser, OperationState &result) {
|
2019-08-09 05:58:19 -07:00
|
|
|
llvm::SMLoc attributeLoc, typeLoc;
|
|
|
|
|
SmallVector<NamedAttribute, 4> attrs;
|
|
|
|
|
OpAsmParser::OperandType vector;
|
|
|
|
|
Type type;
|
|
|
|
|
Attribute attr;
|
2019-09-20 11:36:49 -07:00
|
|
|
if (parser.parseOperand(vector) || parser.getCurrentLocation(&attributeLoc) ||
|
|
|
|
|
parser.parseAttribute(attr, "position", attrs) ||
|
2019-11-05 13:32:07 -08:00
|
|
|
parser.parseOptionalAttrDict(attrs) ||
|
2019-09-20 11:36:49 -07:00
|
|
|
parser.getCurrentLocation(&typeLoc) || parser.parseColonType(type))
|
2019-08-09 05:58:19 -07:00
|
|
|
return failure();
|
|
|
|
|
|
|
|
|
|
auto vectorType = type.dyn_cast<VectorType>();
|
|
|
|
|
if (!vectorType)
|
2019-09-20 11:36:49 -07:00
|
|
|
return parser.emitError(typeLoc, "expected vector type");
|
2019-08-09 05:58:19 -07:00
|
|
|
|
|
|
|
|
auto positionAttr = attr.dyn_cast<ArrayAttr>();
|
|
|
|
|
if (!positionAttr ||
|
|
|
|
|
static_cast<int64_t>(positionAttr.size()) > vectorType.getRank())
|
2019-09-20 11:36:49 -07:00
|
|
|
return parser.emitError(
|
2019-08-09 05:58:19 -07:00
|
|
|
attributeLoc,
|
2019-11-19 12:22:00 -08:00
|
|
|
"expected position attribute of rank smaller than vector rank");
|
2019-08-09 05:58:19 -07:00
|
|
|
|
2019-12-06 12:38:52 -08:00
|
|
|
Type resType = inferExtractOpResultType(vectorType, positionAttr);
|
2019-09-20 19:47:05 -07:00
|
|
|
result.attributes = attrs;
|
|
|
|
|
return failure(parser.resolveOperand(vector, type, result.operands) ||
|
|
|
|
|
parser.addTypeToList(resType, result.types));
|
2019-08-09 05:58:19 -07:00
|
|
|
}
|
|
|
|
|
|
2019-12-06 12:38:52 -08:00
|
|
|
static LogicalResult verify(vector::ExtractOp op) {
|
2019-08-09 05:58:19 -07:00
|
|
|
auto positionAttr = op.position().getValue();
|
|
|
|
|
if (positionAttr.empty())
|
|
|
|
|
return op.emitOpError("expected non-empty position attribute");
|
|
|
|
|
if (positionAttr.size() > static_cast<unsigned>(op.getVectorType().getRank()))
|
|
|
|
|
return op.emitOpError(
|
2019-11-19 12:22:00 -08:00
|
|
|
"expected position attribute of rank smaller than vector rank");
|
2019-08-09 05:58:19 -07:00
|
|
|
for (auto en : llvm::enumerate(positionAttr)) {
|
|
|
|
|
auto attr = en.value().dyn_cast<IntegerAttr>();
|
|
|
|
|
if (!attr || attr.getInt() < 0 ||
|
2019-12-09 15:53:50 -08:00
|
|
|
attr.getInt() >= op.getVectorType().getDimSize(en.index()))
|
2019-08-09 05:58:19 -07:00
|
|
|
return op.emitOpError("expected position attribute #")
|
|
|
|
|
<< (en.index() + 1)
|
2019-11-25 08:46:37 -08:00
|
|
|
<< " to be a non-negative integer smaller than the corresponding "
|
2019-08-09 05:58:19 -07:00
|
|
|
"vector dimension";
|
|
|
|
|
}
|
|
|
|
|
return success();
|
2018-12-14 09:31:17 -08:00
|
|
|
}
|
2019-11-18 10:38:35 -08:00
|
|
|
|
2019-12-16 06:38:33 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// ExtractSlicesOp
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
void ExtractSlicesOp::build(Builder *builder, OperationState &result,
|
2019-12-23 14:45:01 -08:00
|
|
|
TupleType tupleType, Value vector,
|
2019-12-16 06:38:33 -08:00
|
|
|
ArrayRef<int64_t> sizes,
|
|
|
|
|
ArrayRef<int64_t> strides) {
|
|
|
|
|
result.addOperands(vector);
|
2019-12-20 15:32:31 -08:00
|
|
|
auto sizesAttr = getVectorSubscriptAttr(*builder, sizes);
|
|
|
|
|
auto stridesAttr = getVectorSubscriptAttr(*builder, strides);
|
2019-12-16 06:38:33 -08:00
|
|
|
result.addTypes(tupleType);
|
|
|
|
|
result.addAttribute(getSizesAttrName(), sizesAttr);
|
|
|
|
|
result.addAttribute(getStridesAttrName(), stridesAttr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static LogicalResult
|
|
|
|
|
isValidExtractOrInsertSlicesType(Operation *op, VectorType vectorType,
|
|
|
|
|
TupleType tupleType, ArrayRef<int64_t> sizes,
|
|
|
|
|
ArrayRef<int64_t> strides) {
|
|
|
|
|
// Check for non-unit strides.
|
|
|
|
|
// TODO(b/144845578) Support non-1 strides.
|
|
|
|
|
if (llvm::any_of(strides, [](int64_t s) { return s != 1; }))
|
|
|
|
|
return op->emitError("requires unit strides");
|
|
|
|
|
// Check that 'vectorType' rank matches rank of tuple element vectors.
|
|
|
|
|
unsigned rank = vectorType.getRank();
|
|
|
|
|
auto is_vector_type_of_rank = [&](Type t) {
|
|
|
|
|
return t.isa<VectorType>() && t.cast<VectorType>().getRank() == rank;
|
|
|
|
|
};
|
|
|
|
|
if (!llvm::all_of(tupleType.getTypes(), is_vector_type_of_rank))
|
|
|
|
|
return op->emitError("requires vector tuple elements of rank ") << rank;
|
|
|
|
|
// Check that 'sizes' and 'strides' are of size == 'rank'.
|
|
|
|
|
if (sizes.size() != rank || strides.size() != rank)
|
|
|
|
|
return op->emitError("requires sizes and strides of rank ") << rank;
|
|
|
|
|
|
|
|
|
|
// Generate each slice shape based on 'sizes', 'strides' and 'vectorType',
|
[mlir] [VectorOps] fixed typo in verifier of slice op
Reviewers: nicolasvasilache, andydavis1, rriddle
Reviewed By: nicolasvasilache, rriddle
Subscribers: merge_guards_bot, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72664
2020-01-13 15:58:49 -08:00
|
|
|
// and verify that the same matches the corresponding tuple element 'i'.
|
[mlir] [VectorOps] consolidate all vector utilities to one header/cc file
Reviewers: nicolasvasilache, andydavis1, dcaballe
Reviewed By: andydavis1, dcaballe
Subscribers: dcaballe, merge_guards_bot, mgorny, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, liufengdb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73593
2020-01-29 15:21:30 -08:00
|
|
|
auto shape = vectorType.getShape();
|
|
|
|
|
auto sliceStrides = computeStrides(shape, sizes);
|
2019-12-16 06:38:33 -08:00
|
|
|
for (int64_t i = 0, e = tupleType.size(); i < e; ++i) {
|
[mlir] [VectorOps] consolidate all vector utilities to one header/cc file
Reviewers: nicolasvasilache, andydavis1, dcaballe
Reviewed By: andydavis1, dcaballe
Subscribers: dcaballe, merge_guards_bot, mgorny, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, liufengdb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73593
2020-01-29 15:21:30 -08:00
|
|
|
auto vectorOffsets = delinearize(sliceStrides, i);
|
|
|
|
|
auto elementOffsets =
|
|
|
|
|
computeElementOffsetsFromVectorSliceOffsets(sizes, vectorOffsets);
|
|
|
|
|
auto sliceSizes = computeSliceSizes(shape, sizes, elementOffsets);
|
2019-12-16 06:38:33 -08:00
|
|
|
// Create slice VectorType type.
|
|
|
|
|
auto sliceVectorType =
|
|
|
|
|
VectorType::get(sliceSizes, vectorType.getElementType());
|
|
|
|
|
// Verify that 'sliceVectorType' matches tupleType.getTypes(i)
|
|
|
|
|
if (sliceVectorType != tupleType.getType(i))
|
|
|
|
|
return op->emitError("invalid tuple element type ") << sliceVectorType;
|
|
|
|
|
}
|
|
|
|
|
return success();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static LogicalResult verify(ExtractSlicesOp op) {
|
|
|
|
|
SmallVector<int64_t, 4> sizes;
|
|
|
|
|
op.getSizes(sizes);
|
|
|
|
|
SmallVector<int64_t, 4> strides;
|
|
|
|
|
op.getStrides(strides);
|
|
|
|
|
return isValidExtractOrInsertSlicesType(
|
|
|
|
|
op.getOperation(), op.getSourceVectorType(), op.getResultTupleType(),
|
|
|
|
|
sizes, strides);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void populateFromInt64AttrArray(ArrayAttr arrayAttr,
|
|
|
|
|
SmallVectorImpl<int64_t> &results) {
|
|
|
|
|
for (auto attr : arrayAttr)
|
|
|
|
|
results.push_back(attr.cast<IntegerAttr>().getInt());
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ExtractSlicesOp::getSizes(SmallVectorImpl<int64_t> &results) {
|
|
|
|
|
populateFromInt64AttrArray(sizes(), results);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ExtractSlicesOp::getStrides(SmallVectorImpl<int64_t> &results) {
|
|
|
|
|
populateFromInt64AttrArray(strides(), results);
|
|
|
|
|
}
|
|
|
|
|
|
2019-11-26 14:43:03 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// BroadcastOp
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
static LogicalResult verify(BroadcastOp op) {
|
|
|
|
|
VectorType srcVectorType = op.getSourceType().dyn_cast<VectorType>();
|
2019-11-26 19:52:02 -08:00
|
|
|
VectorType dstVectorType = op.getVectorType();
|
2019-11-26 14:43:03 -08:00
|
|
|
// Scalar to vector broadcast is always valid. A vector
|
|
|
|
|
// to vector broadcast needs some additional checking.
|
|
|
|
|
if (srcVectorType) {
|
[VectorOps] Add lowering of vector.broadcast to LLVM IR
For example, a scalar broadcast
%0 = vector.broadcast %x : f32 to vector<2xf32>
return %0 : vector<2xf32>
which expands scalar x into vector [x,x] by lowering
to the following LLVM IR dialect to implement the
duplication over the leading dimension.
%0 = llvm.mlir.undef : !llvm<"<2 x float>">
%1 = llvm.mlir.constant(0 : index) : !llvm.i64
%2 = llvm.insertelement %x, %0[%1 : !llvm.i64] : !llvm<"<2 x float>">
%3 = llvm.shufflevector %2, %0 [0 : i32, 0 : i32] : !llvm<"<2 x float>">, !llvm<"<2 x float>">
return %3 : vector<2xf32>
In the trailing dimensions, the operand is simply
"passed through", unless a more elaborate "stretch"
is required.
For example
%0 = vector.broadcast %arg0 : vector<1xf32> to vector<4xf32>
return %0 : vector<4xf32>
becomes
%0 = llvm.mlir.undef : !llvm<"<4 x float>">
%1 = llvm.mlir.constant(0 : index) : !llvm.i64
%2 = llvm.extractelement %arg0[%1 : !llvm.i64] : !llvm<"<1 x float>">
%3 = llvm.mlir.constant(0 : index) : !llvm.i64
%4 = llvm.insertelement %2, %0[%3 : !llvm.i64] : !llvm<"<4 x float>">
%5 = llvm.shufflevector %4, %0 [0 : i32, 0 : i32, 0 : i32, 0 : i32] : !llvm<"<4 x float>">, !llvm<"<4 x float>">
llvm.return %5 : !llvm<"<4 x float>">
PiperOrigin-RevId: 284219926
2019-12-06 11:01:54 -08:00
|
|
|
int64_t srcRank = srcVectorType.getRank();
|
|
|
|
|
int64_t dstRank = dstVectorType.getRank();
|
2019-12-02 09:56:58 -08:00
|
|
|
if (srcRank > dstRank)
|
2019-11-26 14:43:03 -08:00
|
|
|
return op.emitOpError("source rank higher than destination rank");
|
2019-12-02 09:56:58 -08:00
|
|
|
// Source has an exact match or singleton value for all trailing dimensions
|
|
|
|
|
// (all leading dimensions are simply duplicated).
|
[VectorOps] Add lowering of vector.broadcast to LLVM IR
For example, a scalar broadcast
%0 = vector.broadcast %x : f32 to vector<2xf32>
return %0 : vector<2xf32>
which expands scalar x into vector [x,x] by lowering
to the following LLVM IR dialect to implement the
duplication over the leading dimension.
%0 = llvm.mlir.undef : !llvm<"<2 x float>">
%1 = llvm.mlir.constant(0 : index) : !llvm.i64
%2 = llvm.insertelement %x, %0[%1 : !llvm.i64] : !llvm<"<2 x float>">
%3 = llvm.shufflevector %2, %0 [0 : i32, 0 : i32] : !llvm<"<2 x float>">, !llvm<"<2 x float>">
return %3 : vector<2xf32>
In the trailing dimensions, the operand is simply
"passed through", unless a more elaborate "stretch"
is required.
For example
%0 = vector.broadcast %arg0 : vector<1xf32> to vector<4xf32>
return %0 : vector<4xf32>
becomes
%0 = llvm.mlir.undef : !llvm<"<4 x float>">
%1 = llvm.mlir.constant(0 : index) : !llvm.i64
%2 = llvm.extractelement %arg0[%1 : !llvm.i64] : !llvm<"<1 x float>">
%3 = llvm.mlir.constant(0 : index) : !llvm.i64
%4 = llvm.insertelement %2, %0[%3 : !llvm.i64] : !llvm<"<4 x float>">
%5 = llvm.shufflevector %4, %0 [0 : i32, 0 : i32, 0 : i32, 0 : i32] : !llvm<"<4 x float>">, !llvm<"<4 x float>">
llvm.return %5 : !llvm<"<4 x float>">
PiperOrigin-RevId: 284219926
2019-12-06 11:01:54 -08:00
|
|
|
int64_t lead = dstRank - srcRank;
|
|
|
|
|
for (int64_t r = 0; r < srcRank; ++r) {
|
|
|
|
|
int64_t srcDim = srcVectorType.getDimSize(r);
|
|
|
|
|
int64_t dstDim = dstVectorType.getDimSize(lead + r);
|
2019-12-02 09:56:58 -08:00
|
|
|
if (srcDim != 1 && srcDim != dstDim)
|
|
|
|
|
return op.emitOpError("dimension mismatch (")
|
|
|
|
|
<< srcDim << " vs. " << dstDim << ")";
|
2019-11-26 14:43:03 -08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return success();
|
|
|
|
|
}
|
|
|
|
|
|
2019-12-09 16:15:02 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// ShuffleOp
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2019-12-23 14:45:01 -08:00
|
|
|
void ShuffleOp::build(Builder *builder, OperationState &result, Value v1,
|
|
|
|
|
Value v2, ArrayRef<int64_t> mask) {
|
2019-12-09 16:15:02 -08:00
|
|
|
result.addOperands({v1, v2});
|
2019-12-19 11:47:45 -08:00
|
|
|
auto maskAttr = getVectorSubscriptAttr(*builder, mask);
|
2020-01-11 08:54:04 -08:00
|
|
|
result.addTypes(v1.getType());
|
2019-12-09 16:15:02 -08:00
|
|
|
result.addAttribute(getMaskAttrName(), maskAttr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void print(OpAsmPrinter &p, ShuffleOp op) {
|
2020-01-11 08:54:04 -08:00
|
|
|
p << op.getOperationName() << " " << op.v1() << ", " << op.v2() << " "
|
2019-12-09 16:15:02 -08:00
|
|
|
<< op.mask();
|
|
|
|
|
p.printOptionalAttrDict(op.getAttrs(), {ShuffleOp::getMaskAttrName()});
|
2020-01-11 08:54:04 -08:00
|
|
|
p << " : " << op.v1().getType() << ", " << op.v2().getType();
|
2019-12-09 16:15:02 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static LogicalResult verify(ShuffleOp op) {
|
|
|
|
|
VectorType resultType = op.getVectorType();
|
|
|
|
|
VectorType v1Type = op.getV1VectorType();
|
|
|
|
|
VectorType v2Type = op.getV2VectorType();
|
|
|
|
|
// Verify ranks.
|
|
|
|
|
int64_t resRank = resultType.getRank();
|
|
|
|
|
int64_t v1Rank = v1Type.getRank();
|
|
|
|
|
int64_t v2Rank = v2Type.getRank();
|
|
|
|
|
if (resRank != v1Rank || v1Rank != v2Rank)
|
|
|
|
|
return op.emitOpError("rank mismatch");
|
|
|
|
|
// Verify all but leading dimension sizes.
|
|
|
|
|
for (int64_t r = 1; r < v1Rank; ++r) {
|
|
|
|
|
int64_t resDim = resultType.getDimSize(r);
|
|
|
|
|
int64_t v1Dim = v1Type.getDimSize(r);
|
|
|
|
|
int64_t v2Dim = v2Type.getDimSize(r);
|
|
|
|
|
if (resDim != v1Dim || v1Dim != v2Dim)
|
|
|
|
|
return op.emitOpError("dimension mismatch");
|
|
|
|
|
}
|
|
|
|
|
// Verify mask length.
|
|
|
|
|
auto maskAttr = op.mask().getValue();
|
|
|
|
|
int64_t maskLength = maskAttr.size();
|
|
|
|
|
if (maskLength != resultType.getDimSize(0))
|
|
|
|
|
return op.emitOpError("mask length mismatch");
|
|
|
|
|
// Verify all indices.
|
|
|
|
|
int64_t indexSize = v1Type.getDimSize(0) + v2Type.getDimSize(0);
|
|
|
|
|
for (auto en : llvm::enumerate(maskAttr)) {
|
|
|
|
|
auto attr = en.value().dyn_cast<IntegerAttr>();
|
|
|
|
|
if (!attr || attr.getInt() < 0 || attr.getInt() >= indexSize)
|
|
|
|
|
return op.emitOpError("mask index #")
|
|
|
|
|
<< (en.index() + 1) << " out of range";
|
|
|
|
|
}
|
|
|
|
|
return success();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static ParseResult parseShuffleOp(OpAsmParser &parser, OperationState &result) {
|
|
|
|
|
OpAsmParser::OperandType v1, v2;
|
|
|
|
|
Attribute attr;
|
|
|
|
|
VectorType v1Type, v2Type;
|
|
|
|
|
if (parser.parseOperand(v1) || parser.parseComma() ||
|
|
|
|
|
parser.parseOperand(v2) ||
|
|
|
|
|
parser.parseAttribute(attr, ShuffleOp::getMaskAttrName(),
|
|
|
|
|
result.attributes) ||
|
|
|
|
|
parser.parseOptionalAttrDict(result.attributes) ||
|
|
|
|
|
parser.parseColonType(v1Type) || parser.parseComma() ||
|
|
|
|
|
parser.parseType(v2Type) ||
|
|
|
|
|
parser.resolveOperand(v1, v1Type, result.operands) ||
|
|
|
|
|
parser.resolveOperand(v2, v2Type, result.operands))
|
|
|
|
|
return failure();
|
|
|
|
|
// Construct resulting type: leading dimension matches mask length,
|
|
|
|
|
// all trailing dimensions match the operands.
|
|
|
|
|
auto maskAttr = attr.dyn_cast<ArrayAttr>();
|
|
|
|
|
if (!maskAttr)
|
|
|
|
|
return parser.emitError(parser.getNameLoc(), "missing mask attribute");
|
|
|
|
|
int64_t maskLength = maskAttr.size();
|
|
|
|
|
if (maskLength <= 0)
|
|
|
|
|
return parser.emitError(parser.getNameLoc(), "invalid mask length");
|
|
|
|
|
int64_t v1Rank = v1Type.getRank();
|
|
|
|
|
SmallVector<int64_t, 4> shape;
|
|
|
|
|
shape.reserve(v1Rank);
|
|
|
|
|
shape.push_back(maskLength);
|
|
|
|
|
for (int64_t r = 1; r < v1Rank; ++r)
|
|
|
|
|
shape.push_back(v1Type.getDimSize(r));
|
|
|
|
|
VectorType resType = VectorType::get(shape, v1Type.getElementType());
|
|
|
|
|
parser.addTypeToList(resType, result.types);
|
|
|
|
|
return success();
|
|
|
|
|
}
|
|
|
|
|
|
2019-12-16 09:52:13 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// InsertElementOp
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
static void print(OpAsmPrinter &p, InsertElementOp op) {
|
2020-01-11 08:54:04 -08:00
|
|
|
p << op.getOperationName() << " " << op.source() << ", " << op.dest() << "["
|
|
|
|
|
<< op.position() << " : " << op.position().getType() << "]";
|
2019-12-16 09:52:13 -08:00
|
|
|
p.printOptionalAttrDict(op.getAttrs());
|
2020-01-11 08:54:04 -08:00
|
|
|
p << " : " << op.dest().getType();
|
2019-12-16 09:52:13 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static ParseResult parseInsertElementOp(OpAsmParser &parser,
|
|
|
|
|
OperationState &result) {
|
|
|
|
|
OpAsmParser::OperandType source, dest, position;
|
|
|
|
|
Type positionType;
|
|
|
|
|
VectorType destType;
|
|
|
|
|
if (parser.parseOperand(source) || parser.parseComma() ||
|
|
|
|
|
parser.parseOperand(dest) || parser.parseLSquare() ||
|
|
|
|
|
parser.parseOperand(position) || parser.parseColonType(positionType) ||
|
|
|
|
|
parser.parseRSquare() ||
|
|
|
|
|
parser.parseOptionalAttrDict(result.attributes) ||
|
|
|
|
|
parser.parseColonType(destType))
|
|
|
|
|
return failure();
|
|
|
|
|
Type sourceType = destType.getElementType();
|
|
|
|
|
return failure(
|
|
|
|
|
parser.resolveOperand(source, sourceType, result.operands) ||
|
|
|
|
|
parser.resolveOperand(dest, destType, result.operands) ||
|
|
|
|
|
parser.resolveOperand(position, positionType, result.operands) ||
|
|
|
|
|
parser.addTypeToList(destType, result.types));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static LogicalResult verify(InsertElementOp op) {
|
|
|
|
|
auto dstVectorType = op.getDestVectorType();
|
|
|
|
|
if (dstVectorType.getRank() != 1)
|
|
|
|
|
return op.emitOpError("expected 1-D vector");
|
|
|
|
|
return success();
|
|
|
|
|
}
|
|
|
|
|
|
2019-11-25 08:46:37 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2019-12-06 12:38:52 -08:00
|
|
|
// InsertOp
|
2019-11-25 08:46:37 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2019-12-23 14:45:01 -08:00
|
|
|
void InsertOp::build(Builder *builder, OperationState &result, Value source,
|
|
|
|
|
Value dest, ArrayRef<int64_t> position) {
|
2019-11-25 08:46:37 -08:00
|
|
|
result.addOperands({source, dest});
|
2019-12-19 11:47:45 -08:00
|
|
|
auto positionAttr = getVectorSubscriptAttr(*builder, position);
|
2020-01-11 08:54:04 -08:00
|
|
|
result.addTypes(dest.getType());
|
2019-11-25 08:46:37 -08:00
|
|
|
result.addAttribute(getPositionAttrName(), positionAttr);
|
|
|
|
|
}
|
|
|
|
|
|
2019-12-06 12:38:52 -08:00
|
|
|
static LogicalResult verify(InsertOp op) {
|
2019-11-25 08:46:37 -08:00
|
|
|
auto positionAttr = op.position().getValue();
|
|
|
|
|
if (positionAttr.empty())
|
|
|
|
|
return op.emitOpError("expected non-empty position attribute");
|
|
|
|
|
auto destVectorType = op.getDestVectorType();
|
|
|
|
|
if (positionAttr.size() > static_cast<unsigned>(destVectorType.getRank()))
|
|
|
|
|
return op.emitOpError(
|
|
|
|
|
"expected position attribute of rank smaller than dest vector rank");
|
|
|
|
|
auto srcVectorType = op.getSourceType().dyn_cast<VectorType>();
|
|
|
|
|
if (srcVectorType &&
|
|
|
|
|
(static_cast<unsigned>(srcVectorType.getRank()) + positionAttr.size() !=
|
|
|
|
|
static_cast<unsigned>(destVectorType.getRank())))
|
|
|
|
|
return op.emitOpError("expected position attribute rank + source rank to "
|
|
|
|
|
"match dest vector rank");
|
|
|
|
|
else if (!srcVectorType && (positionAttr.size() !=
|
|
|
|
|
static_cast<unsigned>(destVectorType.getRank())))
|
|
|
|
|
return op.emitOpError(
|
|
|
|
|
"expected position attribute rank to match the dest vector rank");
|
|
|
|
|
for (auto en : llvm::enumerate(positionAttr)) {
|
|
|
|
|
auto attr = en.value().dyn_cast<IntegerAttr>();
|
|
|
|
|
if (!attr || attr.getInt() < 0 ||
|
2019-12-09 15:53:50 -08:00
|
|
|
attr.getInt() >= destVectorType.getDimSize(en.index()))
|
2019-11-25 08:46:37 -08:00
|
|
|
return op.emitOpError("expected position attribute #")
|
|
|
|
|
<< (en.index() + 1)
|
|
|
|
|
<< " to be a non-negative integer smaller than the corresponding "
|
|
|
|
|
"dest vector dimension";
|
|
|
|
|
}
|
|
|
|
|
return success();
|
|
|
|
|
}
|
|
|
|
|
|
2019-12-16 12:56:06 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// InsertSlicesOp
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
static LogicalResult verify(InsertSlicesOp op) {
|
|
|
|
|
SmallVector<int64_t, 4> sizes;
|
|
|
|
|
op.getSizes(sizes);
|
|
|
|
|
SmallVector<int64_t, 4> strides;
|
|
|
|
|
op.getStrides(strides);
|
|
|
|
|
return isValidExtractOrInsertSlicesType(
|
|
|
|
|
op.getOperation(), op.getResultVectorType(), op.getSourceTupleType(),
|
|
|
|
|
sizes, strides);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void InsertSlicesOp::getSizes(SmallVectorImpl<int64_t> &results) {
|
|
|
|
|
populateFromInt64AttrArray(sizes(), results);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void InsertSlicesOp::getStrides(SmallVectorImpl<int64_t> &results) {
|
|
|
|
|
populateFromInt64AttrArray(strides(), results);
|
|
|
|
|
}
|
|
|
|
|
|
2019-11-19 12:22:00 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2019-11-25 15:36:45 -08:00
|
|
|
// InsertStridedSliceOp
|
2019-11-19 12:22:00 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2019-11-25 15:36:45 -08:00
|
|
|
void InsertStridedSliceOp::build(Builder *builder, OperationState &result,
|
2019-12-23 14:45:01 -08:00
|
|
|
Value source, Value dest,
|
2019-11-25 15:36:45 -08:00
|
|
|
ArrayRef<int64_t> offsets,
|
|
|
|
|
ArrayRef<int64_t> strides) {
|
|
|
|
|
result.addOperands({source, dest});
|
2019-12-20 15:32:31 -08:00
|
|
|
auto offsetsAttr = getVectorSubscriptAttr(*builder, offsets);
|
|
|
|
|
auto stridesAttr = getVectorSubscriptAttr(*builder, strides);
|
2020-01-11 08:54:04 -08:00
|
|
|
result.addTypes(dest.getType());
|
2019-11-19 12:22:00 -08:00
|
|
|
result.addAttribute(getOffsetsAttrName(), offsetsAttr);
|
|
|
|
|
result.addAttribute(getStridesAttrName(), stridesAttr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// TODO(ntv) Should be moved to Tablegen Confined attributes.
|
2019-11-25 15:36:45 -08:00
|
|
|
template <typename OpType>
|
2020-01-14 14:06:12 +01:00
|
|
|
static LogicalResult isIntegerArrayAttrSmallerThanShape(OpType op,
|
|
|
|
|
ArrayAttr arrayAttr,
|
|
|
|
|
ArrayRef<int64_t> shape,
|
|
|
|
|
StringRef attrName) {
|
2019-11-25 15:36:45 -08:00
|
|
|
if (arrayAttr.size() > shape.size())
|
|
|
|
|
return op.emitOpError("expected ")
|
|
|
|
|
<< attrName << " attribute of rank smaller than vector rank";
|
|
|
|
|
return success();
|
2019-11-19 12:22:00 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Returns true if all integers in `arrayAttr` are in the half-open [min, max}
|
|
|
|
|
// interval. If `halfOpen` is true then the admissible interval is [min, max).
|
|
|
|
|
// Otherwise, the admissible interval is [min, max].
|
2019-11-25 15:36:45 -08:00
|
|
|
template <typename OpType>
|
2020-01-14 14:06:12 +01:00
|
|
|
static LogicalResult
|
|
|
|
|
isIntegerArrayAttrConfinedToRange(OpType op, ArrayAttr arrayAttr, int64_t min,
|
|
|
|
|
int64_t max, StringRef attrName,
|
|
|
|
|
bool halfOpen = true) {
|
2019-11-19 12:22:00 -08:00
|
|
|
for (auto attr : arrayAttr) {
|
|
|
|
|
auto val = attr.cast<IntegerAttr>().getInt();
|
|
|
|
|
auto upper = max;
|
|
|
|
|
if (!halfOpen)
|
|
|
|
|
upper += 1;
|
2019-11-25 15:36:45 -08:00
|
|
|
if (val < min || val >= upper)
|
|
|
|
|
return op.emitOpError("expected ") << attrName << " to be confined to ["
|
|
|
|
|
<< min << ", " << upper << ")";
|
2019-11-19 12:22:00 -08:00
|
|
|
}
|
2019-11-25 15:36:45 -08:00
|
|
|
return success();
|
2019-11-19 12:22:00 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Returns true if all integers in `arrayAttr` are in the half-open [min, max}
|
|
|
|
|
// interval. If `halfOpen` is true then the admissible interval is [min, max).
|
|
|
|
|
// Otherwise, the admissible interval is [min, max].
|
2019-11-25 15:36:45 -08:00
|
|
|
template <typename OpType>
|
2020-01-14 14:06:12 +01:00
|
|
|
static LogicalResult
|
2019-11-25 15:36:45 -08:00
|
|
|
isIntegerArrayAttrConfinedToShape(OpType op, ArrayAttr arrayAttr,
|
|
|
|
|
ArrayRef<int64_t> shape, StringRef attrName,
|
2019-11-19 12:22:00 -08:00
|
|
|
bool halfOpen = true, int64_t min = 0) {
|
2019-11-25 15:36:45 -08:00
|
|
|
assert(arrayAttr.size() <= shape.size());
|
|
|
|
|
unsigned index = 0;
|
|
|
|
|
for (auto it : llvm::zip(arrayAttr, shape)) {
|
2019-11-19 12:22:00 -08:00
|
|
|
auto val = std::get<0>(it).cast<IntegerAttr>().getInt();
|
|
|
|
|
auto max = std::get<1>(it);
|
|
|
|
|
if (!halfOpen)
|
|
|
|
|
max += 1;
|
2019-11-25 15:36:45 -08:00
|
|
|
if (val < min || val >= max)
|
|
|
|
|
return op.emitOpError("expected ")
|
|
|
|
|
<< attrName << " dimension " << index << " to be confined to ["
|
|
|
|
|
<< min << ", " << max << ")";
|
|
|
|
|
++index;
|
2019-11-19 12:22:00 -08:00
|
|
|
}
|
2019-11-25 15:36:45 -08:00
|
|
|
return success();
|
2019-11-19 12:22:00 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Returns true if all integers in `arrayAttr` are in the interval [min, max}.
|
|
|
|
|
// interval. If `halfOpen` is true then the admissible interval is [min, max).
|
|
|
|
|
// Otherwise, the admissible interval is [min, max].
|
2019-11-25 15:36:45 -08:00
|
|
|
template <typename OpType>
|
2020-01-14 14:06:12 +01:00
|
|
|
static LogicalResult isSumOfIntegerArrayAttrConfinedToShape(
|
2019-11-25 15:36:45 -08:00
|
|
|
OpType op, ArrayAttr arrayAttr1, ArrayAttr arrayAttr2,
|
|
|
|
|
ArrayRef<int64_t> shape, StringRef attrName1, StringRef attrName2,
|
|
|
|
|
bool halfOpen = true, int64_t min = 1) {
|
|
|
|
|
assert(arrayAttr1.size() <= shape.size());
|
|
|
|
|
assert(arrayAttr2.size() <= shape.size());
|
|
|
|
|
unsigned index = 0;
|
|
|
|
|
for (auto it : llvm::zip(arrayAttr1, arrayAttr2, shape)) {
|
2019-11-19 12:22:00 -08:00
|
|
|
auto val1 = std::get<0>(it).cast<IntegerAttr>().getInt();
|
|
|
|
|
auto val2 = std::get<1>(it).cast<IntegerAttr>().getInt();
|
|
|
|
|
auto max = std::get<2>(it);
|
|
|
|
|
if (!halfOpen)
|
|
|
|
|
max += 1;
|
2019-11-25 15:36:45 -08:00
|
|
|
if (val1 + val2 < 0 || val1 + val2 >= max)
|
|
|
|
|
return op.emitOpError("expected sum(")
|
|
|
|
|
<< attrName1 << ", " << attrName2 << ") dimension " << index
|
|
|
|
|
<< " to be confined to [" << min << ", " << max << ")";
|
|
|
|
|
++index;
|
2019-11-19 12:22:00 -08:00
|
|
|
}
|
2019-11-25 15:36:45 -08:00
|
|
|
return success();
|
2019-11-19 12:22:00 -08:00
|
|
|
}
|
|
|
|
|
|
2019-11-25 15:36:45 -08:00
|
|
|
static ArrayAttr makeI64ArrayAttr(ArrayRef<int64_t> values,
|
|
|
|
|
MLIRContext *context) {
|
|
|
|
|
auto attrs = functional::map(
|
|
|
|
|
[context](int64_t v) -> Attribute {
|
|
|
|
|
return IntegerAttr::get(IntegerType::get(64, context), APInt(64, v));
|
|
|
|
|
},
|
|
|
|
|
values);
|
|
|
|
|
return ArrayAttr::get(attrs, context);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static LogicalResult verify(InsertStridedSliceOp op) {
|
|
|
|
|
auto sourceVectorType = op.getSourceVectorType();
|
|
|
|
|
auto destVectorType = op.getDestVectorType();
|
2019-11-19 12:22:00 -08:00
|
|
|
auto offsets = op.offsets();
|
|
|
|
|
auto strides = op.strides();
|
2019-11-25 15:56:06 -08:00
|
|
|
if (offsets.size() != static_cast<unsigned>(destVectorType.getRank()))
|
|
|
|
|
return op.emitOpError(
|
|
|
|
|
"expected offsets of same size as destination vector rank");
|
|
|
|
|
if (strides.size() != static_cast<unsigned>(sourceVectorType.getRank()))
|
|
|
|
|
return op.emitOpError(
|
|
|
|
|
"expected strides of same size as source vector rank");
|
|
|
|
|
if (sourceVectorType.getRank() > destVectorType.getRank())
|
|
|
|
|
return op.emitOpError(
|
|
|
|
|
"expected source rank to be smaller than destination rank");
|
2019-11-19 12:22:00 -08:00
|
|
|
|
2019-11-25 15:36:45 -08:00
|
|
|
auto sourceShape = sourceVectorType.getShape();
|
|
|
|
|
auto destShape = destVectorType.getShape();
|
|
|
|
|
SmallVector<int64_t, 4> sourceShapeAsDestShape(
|
|
|
|
|
destShape.size() - sourceShape.size(), 0);
|
|
|
|
|
sourceShapeAsDestShape.append(sourceShape.begin(), sourceShape.end());
|
|
|
|
|
auto offName = InsertStridedSliceOp::getOffsetsAttrName();
|
|
|
|
|
auto stridesName = InsertStridedSliceOp::getStridesAttrName();
|
|
|
|
|
if (failed(
|
|
|
|
|
isIntegerArrayAttrConfinedToShape(op, offsets, destShape, offName)) ||
|
|
|
|
|
failed(isIntegerArrayAttrConfinedToRange(op, strides, 1, 1, stridesName,
|
|
|
|
|
/*halfOpen=*/false)) ||
|
|
|
|
|
failed(isSumOfIntegerArrayAttrConfinedToShape(
|
|
|
|
|
op, offsets,
|
|
|
|
|
makeI64ArrayAttr(sourceShapeAsDestShape, op.getContext()), destShape,
|
|
|
|
|
offName, "source vector shape",
|
|
|
|
|
/*halfOpen=*/false, /*min=*/1)))
|
|
|
|
|
return failure();
|
|
|
|
|
|
2019-11-19 12:22:00 -08:00
|
|
|
return success();
|
|
|
|
|
}
|
|
|
|
|
|
2019-08-09 06:55:10 -07:00
|
|
|
//===----------------------------------------------------------------------===//
|
2019-11-22 07:52:02 -08:00
|
|
|
// OuterProductOp
|
2019-08-09 06:55:10 -07:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2019-11-22 07:52:02 -08:00
|
|
|
static void print(OpAsmPrinter &p, OuterProductOp op) {
|
2020-01-11 08:54:04 -08:00
|
|
|
p << op.getOperationName() << " " << op.lhs() << ", " << op.rhs();
|
2019-12-12 15:31:39 -08:00
|
|
|
if (!op.acc().empty())
|
|
|
|
|
p << ", " << op.acc();
|
2020-01-11 08:54:04 -08:00
|
|
|
p << " : " << op.lhs().getType() << ", " << op.rhs().getType();
|
2019-08-09 06:55:10 -07:00
|
|
|
}
|
|
|
|
|
|
2019-11-22 07:52:02 -08:00
|
|
|
static ParseResult parseOuterProductOp(OpAsmParser &parser,
|
|
|
|
|
OperationState &result) {
|
Extend vector.outerproduct with an optional 3rd argument
This CL adds an optional third argument to the vector.outerproduct instruction.
When such a third argument is specified, it is added to the result of the outerproduct and is lowered to FMA intrinsic when the lowering supports it.
In the future, we can add an attribute on the `vector.outerproduct` instruction to modify the operations for which to emit code (e.g. "+/*", "max/+", "min/+", "log/exp" ...).
This CL additionally performs minor cleanups in the vector lowering and adds tests to improve coverage.
This has been independently verified to result in proper fma instructions for haswell as follows.
Input:
```
func @outerproduct_add(%arg0: vector<17xf32>, %arg1: vector<8xf32>, %arg2: vector<17x8xf32>) -> vector<17x8xf32> {
%2 = vector.outerproduct %arg0, %arg1, %arg2 : vector<17xf32>, vector<8xf32>
return %2 : vector<17x8xf32>
}
}
```
Command:
```
mlir-opt vector-to-llvm.mlir -vector-lower-to-llvm-dialect --disable-pass-threading | mlir-opt -lower-to-cfg -lower-to-llvm | mlir-translate --mlir-to-llvmir | opt -O3 | llc -O3 -march=x86-64 -mcpu=haswell -mattr=fma,avx2
```
Output:
```
outerproduct_add: # @outerproduct_add
# %bb.0:
...
vmovaps 112(%rbp), %ymm8
vbroadcastss %xmm0, %ymm0
...
vbroadcastss 64(%rbp), %ymm15
vfmadd213ps 144(%rbp), %ymm8, %ymm0 # ymm0 = (ymm8 * ymm0) + mem
...
vfmadd213ps 400(%rbp), %ymm8, %ymm9 # ymm9 = (ymm8 * ymm9) + mem
...
```
PiperOrigin-RevId: 263743359
2019-08-16 03:52:56 -07:00
|
|
|
SmallVector<OpAsmParser::OperandType, 3> operandsInfo;
|
|
|
|
|
Type tLHS, tRHS;
|
2019-09-20 11:36:49 -07:00
|
|
|
if (parser.parseOperandList(operandsInfo) || parser.parseColonType(tLHS) ||
|
|
|
|
|
parser.parseComma() || parser.parseType(tRHS))
|
2019-08-09 06:55:10 -07:00
|
|
|
return failure();
|
Extend vector.outerproduct with an optional 3rd argument
This CL adds an optional third argument to the vector.outerproduct instruction.
When such a third argument is specified, it is added to the result of the outerproduct and is lowered to FMA intrinsic when the lowering supports it.
In the future, we can add an attribute on the `vector.outerproduct` instruction to modify the operations for which to emit code (e.g. "+/*", "max/+", "min/+", "log/exp" ...).
This CL additionally performs minor cleanups in the vector lowering and adds tests to improve coverage.
This has been independently verified to result in proper fma instructions for haswell as follows.
Input:
```
func @outerproduct_add(%arg0: vector<17xf32>, %arg1: vector<8xf32>, %arg2: vector<17x8xf32>) -> vector<17x8xf32> {
%2 = vector.outerproduct %arg0, %arg1, %arg2 : vector<17xf32>, vector<8xf32>
return %2 : vector<17x8xf32>
}
}
```
Command:
```
mlir-opt vector-to-llvm.mlir -vector-lower-to-llvm-dialect --disable-pass-threading | mlir-opt -lower-to-cfg -lower-to-llvm | mlir-translate --mlir-to-llvmir | opt -O3 | llc -O3 -march=x86-64 -mcpu=haswell -mattr=fma,avx2
```
Output:
```
outerproduct_add: # @outerproduct_add
# %bb.0:
...
vmovaps 112(%rbp), %ymm8
vbroadcastss %xmm0, %ymm0
...
vbroadcastss 64(%rbp), %ymm15
vfmadd213ps 144(%rbp), %ymm8, %ymm0 # ymm0 = (ymm8 * ymm0) + mem
...
vfmadd213ps 400(%rbp), %ymm8, %ymm9 # ymm9 = (ymm8 * ymm9) + mem
...
```
PiperOrigin-RevId: 263743359
2019-08-16 03:52:56 -07:00
|
|
|
if (operandsInfo.size() < 2)
|
2019-09-20 11:36:49 -07:00
|
|
|
return parser.emitError(parser.getNameLoc(),
|
|
|
|
|
"expected at least 2 operands");
|
Extend vector.outerproduct with an optional 3rd argument
This CL adds an optional third argument to the vector.outerproduct instruction.
When such a third argument is specified, it is added to the result of the outerproduct and is lowered to FMA intrinsic when the lowering supports it.
In the future, we can add an attribute on the `vector.outerproduct` instruction to modify the operations for which to emit code (e.g. "+/*", "max/+", "min/+", "log/exp" ...).
This CL additionally performs minor cleanups in the vector lowering and adds tests to improve coverage.
This has been independently verified to result in proper fma instructions for haswell as follows.
Input:
```
func @outerproduct_add(%arg0: vector<17xf32>, %arg1: vector<8xf32>, %arg2: vector<17x8xf32>) -> vector<17x8xf32> {
%2 = vector.outerproduct %arg0, %arg1, %arg2 : vector<17xf32>, vector<8xf32>
return %2 : vector<17x8xf32>
}
}
```
Command:
```
mlir-opt vector-to-llvm.mlir -vector-lower-to-llvm-dialect --disable-pass-threading | mlir-opt -lower-to-cfg -lower-to-llvm | mlir-translate --mlir-to-llvmir | opt -O3 | llc -O3 -march=x86-64 -mcpu=haswell -mattr=fma,avx2
```
Output:
```
outerproduct_add: # @outerproduct_add
# %bb.0:
...
vmovaps 112(%rbp), %ymm8
vbroadcastss %xmm0, %ymm0
...
vbroadcastss 64(%rbp), %ymm15
vfmadd213ps 144(%rbp), %ymm8, %ymm0 # ymm0 = (ymm8 * ymm0) + mem
...
vfmadd213ps 400(%rbp), %ymm8, %ymm9 # ymm9 = (ymm8 * ymm9) + mem
...
```
PiperOrigin-RevId: 263743359
2019-08-16 03:52:56 -07:00
|
|
|
VectorType vLHS = tLHS.dyn_cast<VectorType>();
|
|
|
|
|
VectorType vRHS = tRHS.dyn_cast<VectorType>();
|
|
|
|
|
if (!vLHS || !vRHS)
|
2019-09-20 11:36:49 -07:00
|
|
|
return parser.emitError(parser.getNameLoc(), "expected 2 vector types");
|
Extend vector.outerproduct with an optional 3rd argument
This CL adds an optional third argument to the vector.outerproduct instruction.
When such a third argument is specified, it is added to the result of the outerproduct and is lowered to FMA intrinsic when the lowering supports it.
In the future, we can add an attribute on the `vector.outerproduct` instruction to modify the operations for which to emit code (e.g. "+/*", "max/+", "min/+", "log/exp" ...).
This CL additionally performs minor cleanups in the vector lowering and adds tests to improve coverage.
This has been independently verified to result in proper fma instructions for haswell as follows.
Input:
```
func @outerproduct_add(%arg0: vector<17xf32>, %arg1: vector<8xf32>, %arg2: vector<17x8xf32>) -> vector<17x8xf32> {
%2 = vector.outerproduct %arg0, %arg1, %arg2 : vector<17xf32>, vector<8xf32>
return %2 : vector<17x8xf32>
}
}
```
Command:
```
mlir-opt vector-to-llvm.mlir -vector-lower-to-llvm-dialect --disable-pass-threading | mlir-opt -lower-to-cfg -lower-to-llvm | mlir-translate --mlir-to-llvmir | opt -O3 | llc -O3 -march=x86-64 -mcpu=haswell -mattr=fma,avx2
```
Output:
```
outerproduct_add: # @outerproduct_add
# %bb.0:
...
vmovaps 112(%rbp), %ymm8
vbroadcastss %xmm0, %ymm0
...
vbroadcastss 64(%rbp), %ymm15
vfmadd213ps 144(%rbp), %ymm8, %ymm0 # ymm0 = (ymm8 * ymm0) + mem
...
vfmadd213ps 400(%rbp), %ymm8, %ymm9 # ymm9 = (ymm8 * ymm9) + mem
...
```
PiperOrigin-RevId: 263743359
2019-08-16 03:52:56 -07:00
|
|
|
VectorType resType = VectorType::get({vLHS.getDimSize(0), vRHS.getDimSize(0)},
|
|
|
|
|
vLHS.getElementType());
|
|
|
|
|
return failure(
|
2019-09-20 19:47:05 -07:00
|
|
|
parser.resolveOperand(operandsInfo[0], tLHS, result.operands) ||
|
|
|
|
|
parser.resolveOperand(operandsInfo[1], tRHS, result.operands) ||
|
Extend vector.outerproduct with an optional 3rd argument
This CL adds an optional third argument to the vector.outerproduct instruction.
When such a third argument is specified, it is added to the result of the outerproduct and is lowered to FMA intrinsic when the lowering supports it.
In the future, we can add an attribute on the `vector.outerproduct` instruction to modify the operations for which to emit code (e.g. "+/*", "max/+", "min/+", "log/exp" ...).
This CL additionally performs minor cleanups in the vector lowering and adds tests to improve coverage.
This has been independently verified to result in proper fma instructions for haswell as follows.
Input:
```
func @outerproduct_add(%arg0: vector<17xf32>, %arg1: vector<8xf32>, %arg2: vector<17x8xf32>) -> vector<17x8xf32> {
%2 = vector.outerproduct %arg0, %arg1, %arg2 : vector<17xf32>, vector<8xf32>
return %2 : vector<17x8xf32>
}
}
```
Command:
```
mlir-opt vector-to-llvm.mlir -vector-lower-to-llvm-dialect --disable-pass-threading | mlir-opt -lower-to-cfg -lower-to-llvm | mlir-translate --mlir-to-llvmir | opt -O3 | llc -O3 -march=x86-64 -mcpu=haswell -mattr=fma,avx2
```
Output:
```
outerproduct_add: # @outerproduct_add
# %bb.0:
...
vmovaps 112(%rbp), %ymm8
vbroadcastss %xmm0, %ymm0
...
vbroadcastss 64(%rbp), %ymm15
vfmadd213ps 144(%rbp), %ymm8, %ymm0 # ymm0 = (ymm8 * ymm0) + mem
...
vfmadd213ps 400(%rbp), %ymm8, %ymm9 # ymm9 = (ymm8 * ymm9) + mem
...
```
PiperOrigin-RevId: 263743359
2019-08-16 03:52:56 -07:00
|
|
|
(operandsInfo.size() > 2 &&
|
2019-09-20 19:47:05 -07:00
|
|
|
parser.resolveOperand(operandsInfo[2], resType, result.operands)) ||
|
|
|
|
|
parser.addTypeToList(resType, result.types));
|
2019-08-09 06:55:10 -07:00
|
|
|
}
|
2018-12-14 09:31:17 -08:00
|
|
|
|
2019-11-22 07:52:02 -08:00
|
|
|
static LogicalResult verify(OuterProductOp op) {
|
Extend vector.outerproduct with an optional 3rd argument
This CL adds an optional third argument to the vector.outerproduct instruction.
When such a third argument is specified, it is added to the result of the outerproduct and is lowered to FMA intrinsic when the lowering supports it.
In the future, we can add an attribute on the `vector.outerproduct` instruction to modify the operations for which to emit code (e.g. "+/*", "max/+", "min/+", "log/exp" ...).
This CL additionally performs minor cleanups in the vector lowering and adds tests to improve coverage.
This has been independently verified to result in proper fma instructions for haswell as follows.
Input:
```
func @outerproduct_add(%arg0: vector<17xf32>, %arg1: vector<8xf32>, %arg2: vector<17x8xf32>) -> vector<17x8xf32> {
%2 = vector.outerproduct %arg0, %arg1, %arg2 : vector<17xf32>, vector<8xf32>
return %2 : vector<17x8xf32>
}
}
```
Command:
```
mlir-opt vector-to-llvm.mlir -vector-lower-to-llvm-dialect --disable-pass-threading | mlir-opt -lower-to-cfg -lower-to-llvm | mlir-translate --mlir-to-llvmir | opt -O3 | llc -O3 -march=x86-64 -mcpu=haswell -mattr=fma,avx2
```
Output:
```
outerproduct_add: # @outerproduct_add
# %bb.0:
...
vmovaps 112(%rbp), %ymm8
vbroadcastss %xmm0, %ymm0
...
vbroadcastss 64(%rbp), %ymm15
vfmadd213ps 144(%rbp), %ymm8, %ymm0 # ymm0 = (ymm8 * ymm0) + mem
...
vfmadd213ps 400(%rbp), %ymm8, %ymm9 # ymm9 = (ymm8 * ymm9) + mem
...
```
PiperOrigin-RevId: 263743359
2019-08-16 03:52:56 -07:00
|
|
|
VectorType vLHS = op.getOperandVectorTypeLHS(),
|
|
|
|
|
vRHS = op.getOperandVectorTypeRHS(),
|
|
|
|
|
vACC = op.getOperandVectorTypeACC(), vRES = op.getVectorType();
|
|
|
|
|
if (vLHS.getRank() != 1)
|
2019-08-09 06:55:10 -07:00
|
|
|
return op.emitOpError("expected 1-d vector for operand #1");
|
Extend vector.outerproduct with an optional 3rd argument
This CL adds an optional third argument to the vector.outerproduct instruction.
When such a third argument is specified, it is added to the result of the outerproduct and is lowered to FMA intrinsic when the lowering supports it.
In the future, we can add an attribute on the `vector.outerproduct` instruction to modify the operations for which to emit code (e.g. "+/*", "max/+", "min/+", "log/exp" ...).
This CL additionally performs minor cleanups in the vector lowering and adds tests to improve coverage.
This has been independently verified to result in proper fma instructions for haswell as follows.
Input:
```
func @outerproduct_add(%arg0: vector<17xf32>, %arg1: vector<8xf32>, %arg2: vector<17x8xf32>) -> vector<17x8xf32> {
%2 = vector.outerproduct %arg0, %arg1, %arg2 : vector<17xf32>, vector<8xf32>
return %2 : vector<17x8xf32>
}
}
```
Command:
```
mlir-opt vector-to-llvm.mlir -vector-lower-to-llvm-dialect --disable-pass-threading | mlir-opt -lower-to-cfg -lower-to-llvm | mlir-translate --mlir-to-llvmir | opt -O3 | llc -O3 -march=x86-64 -mcpu=haswell -mattr=fma,avx2
```
Output:
```
outerproduct_add: # @outerproduct_add
# %bb.0:
...
vmovaps 112(%rbp), %ymm8
vbroadcastss %xmm0, %ymm0
...
vbroadcastss 64(%rbp), %ymm15
vfmadd213ps 144(%rbp), %ymm8, %ymm0 # ymm0 = (ymm8 * ymm0) + mem
...
vfmadd213ps 400(%rbp), %ymm8, %ymm9 # ymm9 = (ymm8 * ymm9) + mem
...
```
PiperOrigin-RevId: 263743359
2019-08-16 03:52:56 -07:00
|
|
|
if (vRHS.getRank() != 1)
|
2019-08-09 06:55:10 -07:00
|
|
|
return op.emitOpError("expected 1-d vector for operand #2");
|
Extend vector.outerproduct with an optional 3rd argument
This CL adds an optional third argument to the vector.outerproduct instruction.
When such a third argument is specified, it is added to the result of the outerproduct and is lowered to FMA intrinsic when the lowering supports it.
In the future, we can add an attribute on the `vector.outerproduct` instruction to modify the operations for which to emit code (e.g. "+/*", "max/+", "min/+", "log/exp" ...).
This CL additionally performs minor cleanups in the vector lowering and adds tests to improve coverage.
This has been independently verified to result in proper fma instructions for haswell as follows.
Input:
```
func @outerproduct_add(%arg0: vector<17xf32>, %arg1: vector<8xf32>, %arg2: vector<17x8xf32>) -> vector<17x8xf32> {
%2 = vector.outerproduct %arg0, %arg1, %arg2 : vector<17xf32>, vector<8xf32>
return %2 : vector<17x8xf32>
}
}
```
Command:
```
mlir-opt vector-to-llvm.mlir -vector-lower-to-llvm-dialect --disable-pass-threading | mlir-opt -lower-to-cfg -lower-to-llvm | mlir-translate --mlir-to-llvmir | opt -O3 | llc -O3 -march=x86-64 -mcpu=haswell -mattr=fma,avx2
```
Output:
```
outerproduct_add: # @outerproduct_add
# %bb.0:
...
vmovaps 112(%rbp), %ymm8
vbroadcastss %xmm0, %ymm0
...
vbroadcastss 64(%rbp), %ymm15
vfmadd213ps 144(%rbp), %ymm8, %ymm0 # ymm0 = (ymm8 * ymm0) + mem
...
vfmadd213ps 400(%rbp), %ymm8, %ymm9 # ymm9 = (ymm8 * ymm9) + mem
...
```
PiperOrigin-RevId: 263743359
2019-08-16 03:52:56 -07:00
|
|
|
if (vRES.getRank() != 2)
|
2019-08-09 06:55:10 -07:00
|
|
|
return op.emitOpError("expected 2-d vector result");
|
Extend vector.outerproduct with an optional 3rd argument
This CL adds an optional third argument to the vector.outerproduct instruction.
When such a third argument is specified, it is added to the result of the outerproduct and is lowered to FMA intrinsic when the lowering supports it.
In the future, we can add an attribute on the `vector.outerproduct` instruction to modify the operations for which to emit code (e.g. "+/*", "max/+", "min/+", "log/exp" ...).
This CL additionally performs minor cleanups in the vector lowering and adds tests to improve coverage.
This has been independently verified to result in proper fma instructions for haswell as follows.
Input:
```
func @outerproduct_add(%arg0: vector<17xf32>, %arg1: vector<8xf32>, %arg2: vector<17x8xf32>) -> vector<17x8xf32> {
%2 = vector.outerproduct %arg0, %arg1, %arg2 : vector<17xf32>, vector<8xf32>
return %2 : vector<17x8xf32>
}
}
```
Command:
```
mlir-opt vector-to-llvm.mlir -vector-lower-to-llvm-dialect --disable-pass-threading | mlir-opt -lower-to-cfg -lower-to-llvm | mlir-translate --mlir-to-llvmir | opt -O3 | llc -O3 -march=x86-64 -mcpu=haswell -mattr=fma,avx2
```
Output:
```
outerproduct_add: # @outerproduct_add
# %bb.0:
...
vmovaps 112(%rbp), %ymm8
vbroadcastss %xmm0, %ymm0
...
vbroadcastss 64(%rbp), %ymm15
vfmadd213ps 144(%rbp), %ymm8, %ymm0 # ymm0 = (ymm8 * ymm0) + mem
...
vfmadd213ps 400(%rbp), %ymm8, %ymm9 # ymm9 = (ymm8 * ymm9) + mem
...
```
PiperOrigin-RevId: 263743359
2019-08-16 03:52:56 -07:00
|
|
|
if (vLHS.getDimSize(0) != vRES.getDimSize(0))
|
|
|
|
|
return op.emitOpError("expected #1 operand dim to match result dim #1");
|
|
|
|
|
if (vRHS.getDimSize(0) != vRES.getDimSize(1))
|
|
|
|
|
return op.emitOpError("expected #2 operand dim to match result dim #2");
|
|
|
|
|
if (vACC && vACC != vRES)
|
|
|
|
|
return op.emitOpError("expected operand #3 of same type as result type");
|
2019-08-09 06:55:10 -07:00
|
|
|
return success();
|
|
|
|
|
}
|
Extend vector.outerproduct with an optional 3rd argument
This CL adds an optional third argument to the vector.outerproduct instruction.
When such a third argument is specified, it is added to the result of the outerproduct and is lowered to FMA intrinsic when the lowering supports it.
In the future, we can add an attribute on the `vector.outerproduct` instruction to modify the operations for which to emit code (e.g. "+/*", "max/+", "min/+", "log/exp" ...).
This CL additionally performs minor cleanups in the vector lowering and adds tests to improve coverage.
This has been independently verified to result in proper fma instructions for haswell as follows.
Input:
```
func @outerproduct_add(%arg0: vector<17xf32>, %arg1: vector<8xf32>, %arg2: vector<17x8xf32>) -> vector<17x8xf32> {
%2 = vector.outerproduct %arg0, %arg1, %arg2 : vector<17xf32>, vector<8xf32>
return %2 : vector<17x8xf32>
}
}
```
Command:
```
mlir-opt vector-to-llvm.mlir -vector-lower-to-llvm-dialect --disable-pass-threading | mlir-opt -lower-to-cfg -lower-to-llvm | mlir-translate --mlir-to-llvmir | opt -O3 | llc -O3 -march=x86-64 -mcpu=haswell -mattr=fma,avx2
```
Output:
```
outerproduct_add: # @outerproduct_add
# %bb.0:
...
vmovaps 112(%rbp), %ymm8
vbroadcastss %xmm0, %ymm0
...
vbroadcastss 64(%rbp), %ymm15
vfmadd213ps 144(%rbp), %ymm8, %ymm0 # ymm0 = (ymm8 * ymm0) + mem
...
vfmadd213ps 400(%rbp), %ymm8, %ymm9 # ymm9 = (ymm8 * ymm9) + mem
...
```
PiperOrigin-RevId: 263743359
2019-08-16 03:52:56 -07:00
|
|
|
|
2019-12-19 12:22:35 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// ReshapeOp
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
static void print(OpAsmPrinter &p, ReshapeOp op) {
|
2020-01-11 08:54:04 -08:00
|
|
|
p << op.getOperationName() << " " << op.vector() << ", [" << op.input_shape()
|
2019-12-19 12:22:35 -08:00
|
|
|
<< "], [" << op.output_shape() << "], " << op.fixed_vector_sizes();
|
|
|
|
|
SmallVector<StringRef, 2> elidedAttrs = {
|
|
|
|
|
ReshapeOp::getOperandSegmentSizeAttr(),
|
|
|
|
|
ReshapeOp::getFixedVectorSizesAttrName()};
|
|
|
|
|
p.printOptionalAttrDict(op.getAttrs(), elidedAttrs);
|
|
|
|
|
p << " : " << op.getInputVectorType() << " to " << op.getOutputVectorType();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// TODO(b/146516564) Consider passing number of inner vector dimensions that
|
|
|
|
|
// are fixed, instead of their values in 'fixesVectorSizes' array attr.
|
|
|
|
|
//
|
|
|
|
|
// operation ::= ssa-id `=` `vector.reshape` ssa-use, `[` ssa-use-list `]`,
|
|
|
|
|
// `[` ssa-use-list `]`, `[` array-attribute `]`
|
|
|
|
|
// `:` vector-type 'to' vector-type
|
|
|
|
|
//
|
|
|
|
|
static ParseResult parseReshapeOp(OpAsmParser &parser, OperationState &result) {
|
|
|
|
|
OpAsmParser::OperandType inputInfo;
|
|
|
|
|
SmallVector<OpAsmParser::OperandType, 4> inputShapeInfo;
|
|
|
|
|
SmallVector<OpAsmParser::OperandType, 4> outputShapeInfo;
|
|
|
|
|
ArrayAttr fixedVectorSizesAttr;
|
|
|
|
|
StringRef attrName = ReshapeOp::getFixedVectorSizesAttrName();
|
|
|
|
|
auto indexType = parser.getBuilder().getIndexType();
|
|
|
|
|
if (parser.parseOperand(inputInfo) || parser.parseComma() ||
|
|
|
|
|
parser.parseOperandList(inputShapeInfo, OpAsmParser::Delimiter::Square) ||
|
|
|
|
|
parser.parseComma() ||
|
|
|
|
|
parser.parseOperandList(outputShapeInfo,
|
|
|
|
|
OpAsmParser::Delimiter::Square) ||
|
|
|
|
|
parser.parseComma()) {
|
|
|
|
|
return failure();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
auto builder = parser.getBuilder();
|
|
|
|
|
result.addAttribute(
|
|
|
|
|
ReshapeOp::getOperandSegmentSizeAttr(),
|
|
|
|
|
builder.getI32VectorAttr({1, static_cast<int32_t>(inputShapeInfo.size()),
|
|
|
|
|
static_cast<int32_t>(outputShapeInfo.size())}));
|
|
|
|
|
Type inputType;
|
|
|
|
|
Type outputType;
|
|
|
|
|
return failure(
|
|
|
|
|
parser.parseAttribute(fixedVectorSizesAttr, attrName,
|
|
|
|
|
result.attributes) ||
|
|
|
|
|
parser.parseOptionalAttrDict(result.attributes) ||
|
|
|
|
|
parser.parseColonType(inputType) ||
|
|
|
|
|
parser.resolveOperand(inputInfo, inputType, result.operands) ||
|
|
|
|
|
parser.resolveOperands(inputShapeInfo, indexType, result.operands) ||
|
|
|
|
|
parser.resolveOperands(outputShapeInfo, indexType, result.operands) ||
|
|
|
|
|
parser.parseKeywordType("to", outputType) ||
|
|
|
|
|
parser.addTypeToList(outputType, result.types));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static LogicalResult verify(ReshapeOp op) {
|
|
|
|
|
// Verify that rank(numInputs/outputs) + numFixedVec dim matches vec rank.
|
|
|
|
|
auto inputVectorType = op.getInputVectorType();
|
|
|
|
|
auto outputVectorType = op.getOutputVectorType();
|
|
|
|
|
int64_t inputShapeRank = op.getNumInputShapeSizes();
|
|
|
|
|
int64_t outputShapeRank = op.getNumOutputShapeSizes();
|
|
|
|
|
SmallVector<int64_t, 4> fixedVectorSizes;
|
|
|
|
|
op.getFixedVectorSizes(fixedVectorSizes);
|
|
|
|
|
int64_t numFixedVectorSizes = fixedVectorSizes.size();
|
|
|
|
|
|
|
|
|
|
if (inputVectorType.getRank() != inputShapeRank + numFixedVectorSizes)
|
|
|
|
|
return op.emitError("invalid input shape for vector type ")
|
|
|
|
|
<< inputVectorType;
|
|
|
|
|
|
|
|
|
|
if (outputVectorType.getRank() != outputShapeRank + numFixedVectorSizes)
|
|
|
|
|
return op.emitError("invalid output shape for vector type ")
|
|
|
|
|
<< outputVectorType;
|
|
|
|
|
|
|
|
|
|
// Verify that the 'fixedVectorSizes' match a input/output vector shape
|
|
|
|
|
// suffix.
|
|
|
|
|
unsigned inputVectorRank = inputVectorType.getRank();
|
|
|
|
|
for (unsigned i = 0; i < numFixedVectorSizes; ++i) {
|
|
|
|
|
unsigned index = inputVectorRank - numFixedVectorSizes - i;
|
|
|
|
|
if (fixedVectorSizes[i] != inputVectorType.getShape()[index])
|
|
|
|
|
return op.emitError("fixed vector size must match input vector for dim ")
|
|
|
|
|
<< i;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
unsigned outputVectorRank = outputVectorType.getRank();
|
|
|
|
|
for (unsigned i = 0; i < numFixedVectorSizes; ++i) {
|
|
|
|
|
unsigned index = outputVectorRank - numFixedVectorSizes - i;
|
|
|
|
|
if (fixedVectorSizes[i] != outputVectorType.getShape()[index])
|
|
|
|
|
return op.emitError("fixed vector size must match output vector for dim ")
|
|
|
|
|
<< i;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// If all shape operands are produced by constant ops, verify that product
|
|
|
|
|
// of dimensions for input/output shape match.
|
2019-12-23 14:45:01 -08:00
|
|
|
auto isDefByConstant = [](Value operand) {
|
2020-01-11 08:54:04 -08:00
|
|
|
return isa_and_nonnull<ConstantIndexOp>(operand.getDefiningOp());
|
2019-12-19 12:22:35 -08:00
|
|
|
};
|
|
|
|
|
if (llvm::all_of(op.input_shape(), isDefByConstant) &&
|
|
|
|
|
llvm::all_of(op.output_shape(), isDefByConstant)) {
|
|
|
|
|
int64_t numInputElements = 1;
|
2019-12-22 21:59:55 -08:00
|
|
|
for (auto operand : op.input_shape())
|
2019-12-19 12:22:35 -08:00
|
|
|
numInputElements *=
|
2020-01-11 08:54:04 -08:00
|
|
|
cast<ConstantIndexOp>(operand.getDefiningOp()).getValue();
|
2019-12-19 12:22:35 -08:00
|
|
|
int64_t numOutputElements = 1;
|
2019-12-22 21:59:55 -08:00
|
|
|
for (auto operand : op.output_shape())
|
2019-12-19 12:22:35 -08:00
|
|
|
numOutputElements *=
|
2020-01-11 08:54:04 -08:00
|
|
|
cast<ConstantIndexOp>(operand.getDefiningOp()).getValue();
|
2019-12-19 12:22:35 -08:00
|
|
|
if (numInputElements != numOutputElements)
|
|
|
|
|
return op.emitError("product of input and output shape sizes must match");
|
|
|
|
|
}
|
|
|
|
|
return success();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ReshapeOp::getFixedVectorSizes(SmallVectorImpl<int64_t> &results) {
|
|
|
|
|
populateFromInt64AttrArray(fixed_vector_sizes(), results);
|
|
|
|
|
}
|
|
|
|
|
|
2019-11-25 15:36:45 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// StridedSliceOp
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
// Inference works as follows:
|
|
|
|
|
// 1. Add 'sizes' from prefix of dims in 'offsets'.
|
|
|
|
|
// 2. Add sizes from 'vectorType' for remaining dims.
|
|
|
|
|
static Type inferStridedSliceOpResultType(VectorType vectorType,
|
|
|
|
|
ArrayAttr offsets, ArrayAttr sizes,
|
|
|
|
|
ArrayAttr strides) {
|
|
|
|
|
assert(offsets.size() == sizes.size() && offsets.size() == strides.size());
|
|
|
|
|
SmallVector<int64_t, 4> shape;
|
|
|
|
|
shape.reserve(vectorType.getRank());
|
|
|
|
|
unsigned idx = 0;
|
|
|
|
|
for (unsigned e = offsets.size(); idx < e; ++idx)
|
|
|
|
|
shape.push_back(sizes.getValue()[idx].cast<IntegerAttr>().getInt());
|
|
|
|
|
for (unsigned e = vectorType.getShape().size(); idx < e; ++idx)
|
|
|
|
|
shape.push_back(vectorType.getShape()[idx]);
|
|
|
|
|
|
|
|
|
|
return VectorType::get(shape, vectorType.getElementType());
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void StridedSliceOp::build(Builder *builder, OperationState &result,
|
2019-12-23 14:45:01 -08:00
|
|
|
Value source, ArrayRef<int64_t> offsets,
|
2019-11-25 15:36:45 -08:00
|
|
|
ArrayRef<int64_t> sizes, ArrayRef<int64_t> strides) {
|
|
|
|
|
result.addOperands(source);
|
2019-12-20 15:32:31 -08:00
|
|
|
auto offsetsAttr = getVectorSubscriptAttr(*builder, offsets);
|
|
|
|
|
auto sizesAttr = getVectorSubscriptAttr(*builder, sizes);
|
|
|
|
|
auto stridesAttr = getVectorSubscriptAttr(*builder, strides);
|
2019-11-25 15:36:45 -08:00
|
|
|
result.addTypes(
|
2020-01-11 08:54:04 -08:00
|
|
|
inferStridedSliceOpResultType(source.getType().cast<VectorType>(),
|
2019-11-25 15:36:45 -08:00
|
|
|
offsetsAttr, sizesAttr, stridesAttr));
|
|
|
|
|
result.addAttribute(getOffsetsAttrName(), offsetsAttr);
|
|
|
|
|
result.addAttribute(getSizesAttrName(), sizesAttr);
|
|
|
|
|
result.addAttribute(getStridesAttrName(), stridesAttr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static LogicalResult verify(StridedSliceOp op) {
|
|
|
|
|
auto type = op.getVectorType();
|
|
|
|
|
auto offsets = op.offsets();
|
|
|
|
|
auto sizes = op.sizes();
|
|
|
|
|
auto strides = op.strides();
|
|
|
|
|
if (offsets.size() != sizes.size() || offsets.size() != strides.size()) {
|
|
|
|
|
op.emitOpError(
|
|
|
|
|
"expected offsets, sizes and strides attributes of same size");
|
|
|
|
|
return failure();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
auto shape = type.getShape();
|
|
|
|
|
auto offName = StridedSliceOp::getOffsetsAttrName();
|
|
|
|
|
auto sizesName = StridedSliceOp::getSizesAttrName();
|
|
|
|
|
auto stridesName = StridedSliceOp::getStridesAttrName();
|
|
|
|
|
if (failed(isIntegerArrayAttrSmallerThanShape(op, offsets, shape, offName)) ||
|
|
|
|
|
failed(isIntegerArrayAttrSmallerThanShape(op, sizes, shape, sizesName)) ||
|
|
|
|
|
failed(isIntegerArrayAttrSmallerThanShape(op, strides, shape,
|
|
|
|
|
stridesName)) ||
|
|
|
|
|
failed(isIntegerArrayAttrConfinedToShape(op, offsets, shape, offName)) ||
|
|
|
|
|
failed(isIntegerArrayAttrConfinedToShape(op, sizes, shape, sizesName,
|
|
|
|
|
/*halfOpen=*/false,
|
|
|
|
|
/*min=*/1)) ||
|
|
|
|
|
failed(isIntegerArrayAttrConfinedToRange(op, strides, 1, 1, stridesName,
|
|
|
|
|
/*halfOpen=*/false)) ||
|
|
|
|
|
failed(isSumOfIntegerArrayAttrConfinedToShape(op, offsets, sizes, shape,
|
|
|
|
|
offName, sizesName,
|
|
|
|
|
/*halfOpen=*/false)))
|
|
|
|
|
return failure();
|
|
|
|
|
|
|
|
|
|
auto resultType = inferStridedSliceOpResultType(
|
|
|
|
|
op.getVectorType(), op.offsets(), op.sizes(), op.strides());
|
2020-01-11 08:54:04 -08:00
|
|
|
if (op.getResult().getType() != resultType) {
|
2019-11-25 15:36:45 -08:00
|
|
|
op.emitOpError("expected result type to be ") << resultType;
|
|
|
|
|
return failure();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return success();
|
|
|
|
|
}
|
|
|
|
|
|
2019-12-10 17:02:17 -08:00
|
|
|
void StridedSliceOp::getOffsets(SmallVectorImpl<int64_t> &results) {
|
|
|
|
|
populateFromInt64AttrArray(offsets(), results);
|
2019-12-04 13:00:14 -08:00
|
|
|
}
|
|
|
|
|
|
2019-12-10 17:02:17 -08:00
|
|
|
namespace {
|
|
|
|
|
|
2019-12-04 13:00:14 -08:00
|
|
|
// Pattern to rewrite a StridedSliceOp(ConstantMaskOp) -> ConstantMaskOp.
|
|
|
|
|
class StridedSliceConstantMaskFolder final
|
|
|
|
|
: public OpRewritePattern<StridedSliceOp> {
|
|
|
|
|
public:
|
|
|
|
|
using OpRewritePattern<StridedSliceOp>::OpRewritePattern;
|
|
|
|
|
|
|
|
|
|
PatternMatchResult matchAndRewrite(StridedSliceOp stridedSliceOp,
|
|
|
|
|
PatternRewriter &rewriter) const override {
|
|
|
|
|
// Return if 'stridedSliceOp' operand is not defined by a ConstantMaskOp.
|
2020-01-11 08:54:04 -08:00
|
|
|
auto defOp = stridedSliceOp.vector().getDefiningOp();
|
2019-12-04 13:00:14 -08:00
|
|
|
auto constantMaskOp = dyn_cast_or_null<ConstantMaskOp>(defOp);
|
|
|
|
|
if (!constantMaskOp)
|
|
|
|
|
return matchFailure();
|
|
|
|
|
// Return if 'stridedSliceOp' has non-unit strides.
|
|
|
|
|
if (llvm::any_of(stridedSliceOp.strides(), [](Attribute attr) {
|
|
|
|
|
return attr.cast<IntegerAttr>().getInt() != 1;
|
|
|
|
|
}))
|
|
|
|
|
return matchFailure();
|
|
|
|
|
// Gather constant mask dimension sizes.
|
|
|
|
|
SmallVector<int64_t, 4> maskDimSizes;
|
|
|
|
|
populateFromInt64AttrArray(constantMaskOp.mask_dim_sizes(), maskDimSizes);
|
|
|
|
|
// Gather strided slice offsets and sizes.
|
|
|
|
|
SmallVector<int64_t, 4> sliceOffsets;
|
|
|
|
|
populateFromInt64AttrArray(stridedSliceOp.offsets(), sliceOffsets);
|
|
|
|
|
SmallVector<int64_t, 4> sliceSizes;
|
|
|
|
|
populateFromInt64AttrArray(stridedSliceOp.sizes(), sliceSizes);
|
|
|
|
|
|
|
|
|
|
// Compute slice of vector mask region.
|
|
|
|
|
SmallVector<int64_t, 4> sliceMaskDimSizes;
|
|
|
|
|
assert(sliceOffsets.size() == maskDimSizes.size());
|
2020-01-01 15:55:14 -08:00
|
|
|
for (auto it : llvm::zip(maskDimSizes, sliceOffsets, sliceSizes)) {
|
2019-12-04 13:00:14 -08:00
|
|
|
int64_t maskDimSize = std::get<0>(it);
|
|
|
|
|
int64_t sliceOffset = std::get<1>(it);
|
|
|
|
|
int64_t sliceSize = std::get<2>(it);
|
|
|
|
|
int64_t sliceMaskDimSize = std::max(
|
|
|
|
|
static_cast<int64_t>(0),
|
|
|
|
|
std::min(sliceOffset + sliceSize, maskDimSize) - sliceOffset);
|
|
|
|
|
sliceMaskDimSizes.push_back(sliceMaskDimSize);
|
|
|
|
|
}
|
|
|
|
|
// If any of 'sliceMaskDimSizes' are zero, then set all to zero (masked
|
|
|
|
|
// region is a conjunction of mask dim intervals).
|
|
|
|
|
if (llvm::any_of(sliceMaskDimSizes, [](int64_t sz) { return sz == 0; }))
|
|
|
|
|
sliceMaskDimSizes.assign(maskDimSizes.size(), 0);
|
|
|
|
|
|
|
|
|
|
// Replace 'stridedSliceOp' with ConstantMaskOp with sliced mask region.
|
|
|
|
|
rewriter.replaceOpWithNewOp<ConstantMaskOp>(
|
2020-01-11 08:54:04 -08:00
|
|
|
stridedSliceOp, stridedSliceOp.getResult().getType(),
|
2019-12-20 15:32:31 -08:00
|
|
|
vector::getVectorSubscriptAttr(rewriter, sliceMaskDimSizes));
|
2019-12-04 13:00:14 -08:00
|
|
|
return matchSuccess();
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
} // end anonymous namespace
|
|
|
|
|
|
|
|
|
|
void StridedSliceOp::getCanonicalizationPatterns(
|
|
|
|
|
OwningRewritePatternList &results, MLIRContext *context) {
|
|
|
|
|
// Pattern to rewrite a StridedSliceOp(ConstantMaskOp) -> ConstantMaskOp.
|
|
|
|
|
results.insert<StridedSliceConstantMaskFolder>(context);
|
|
|
|
|
}
|
|
|
|
|
|
2018-12-14 09:31:17 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2019-11-22 07:52:02 -08:00
|
|
|
// TransferReadOp
|
2018-12-14 09:31:17 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
template <typename EmitFun>
|
2019-04-02 13:09:34 -07:00
|
|
|
static LogicalResult verifyPermutationMap(AffineMap permutationMap,
|
|
|
|
|
EmitFun emitOpError) {
|
2018-12-14 09:31:17 -08:00
|
|
|
SmallVector<bool, 8> seen(permutationMap.getNumInputs(), false);
|
|
|
|
|
for (auto expr : permutationMap.getResults()) {
|
|
|
|
|
auto dim = expr.dyn_cast<AffineDimExpr>();
|
|
|
|
|
auto zero = expr.dyn_cast<AffineConstantExpr>();
|
|
|
|
|
if (zero) {
|
|
|
|
|
if (zero.getValue() != 0) {
|
|
|
|
|
return emitOpError(
|
|
|
|
|
"requires a projected permutation_map (at most one dim or the zero "
|
|
|
|
|
"constant can appear in each result)");
|
|
|
|
|
}
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
if (!dim) {
|
|
|
|
|
return emitOpError("requires a projected permutation_map (at most one "
|
|
|
|
|
"dim or the zero constant can appear in each result)");
|
|
|
|
|
}
|
|
|
|
|
if (seen[dim.getPosition()]) {
|
|
|
|
|
return emitOpError(
|
|
|
|
|
"requires a permutation_map that is a permutation (found one dim "
|
|
|
|
|
"used more than once)");
|
|
|
|
|
}
|
|
|
|
|
seen[dim.getPosition()] = true;
|
|
|
|
|
}
|
2019-04-02 13:09:34 -07:00
|
|
|
return success();
|
2018-12-14 09:31:17 -08:00
|
|
|
}
|
|
|
|
|
|
2019-12-19 16:04:59 -08:00
|
|
|
static LogicalResult verifyTransferOp(Operation *op, MemRefType memrefType,
|
|
|
|
|
VectorType vectorType,
|
|
|
|
|
AffineMap permutationMap) {
|
|
|
|
|
auto memrefElementType = memrefType.getElementType();
|
|
|
|
|
if (auto memrefVectorElementType = memrefElementType.dyn_cast<VectorType>()) {
|
|
|
|
|
// Memref has vector element type.
|
|
|
|
|
|
|
|
|
|
// Check that 'memrefVectorElementType' and vector element types match.
|
|
|
|
|
if (memrefVectorElementType.getElementType() != vectorType.getElementType())
|
|
|
|
|
return op->emitOpError(
|
|
|
|
|
"requires memref and vector types of the same elemental type");
|
|
|
|
|
|
|
|
|
|
// Check that memref vector type is a suffix of 'vectorType.
|
|
|
|
|
unsigned memrefVecEltRank = memrefVectorElementType.getRank();
|
|
|
|
|
unsigned resultVecRank = vectorType.getRank();
|
|
|
|
|
if (memrefVecEltRank > resultVecRank)
|
|
|
|
|
return op->emitOpError(
|
|
|
|
|
"requires memref vector element and vector result ranks to match.");
|
|
|
|
|
// TODO(b/146516564) Move this to isSuffix in VectorOps/Utils.h.
|
|
|
|
|
unsigned rankOffset = resultVecRank - memrefVecEltRank;
|
|
|
|
|
auto memrefVecEltShape = memrefVectorElementType.getShape();
|
|
|
|
|
auto resultVecShape = vectorType.getShape();
|
|
|
|
|
for (unsigned i = 0; i < memrefVecEltRank; ++i)
|
|
|
|
|
if (memrefVecEltShape[i] != resultVecShape[rankOffset + i])
|
|
|
|
|
return op->emitOpError(
|
|
|
|
|
"requires memref vector element shape to match suffix of "
|
|
|
|
|
"vector result shape.");
|
|
|
|
|
// Check that permutation map results match 'rankOffset' of vector type.
|
|
|
|
|
if (permutationMap.getNumResults() != rankOffset)
|
|
|
|
|
return op->emitOpError("requires a permutation_map with result dims of "
|
|
|
|
|
"the same rank as the vector type");
|
|
|
|
|
} else {
|
|
|
|
|
// Memref has scalar element type.
|
|
|
|
|
|
|
|
|
|
// Check that memref and vector element types match.
|
|
|
|
|
if (memrefType.getElementType() != vectorType.getElementType())
|
|
|
|
|
return op->emitOpError(
|
|
|
|
|
"requires memref and vector types of the same elemental type");
|
|
|
|
|
|
|
|
|
|
// Check that permutation map results match rank of vector type.
|
|
|
|
|
if (permutationMap.getNumResults() != vectorType.getRank())
|
|
|
|
|
return op->emitOpError("requires a permutation_map with result dims of "
|
|
|
|
|
"the same rank as the vector type");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (permutationMap.getNumSymbols() != 0)
|
|
|
|
|
return op->emitOpError("requires permutation_map without symbols");
|
|
|
|
|
if (permutationMap.getNumInputs() != memrefType.getRank())
|
|
|
|
|
return op->emitOpError("requires a permutation_map with input dims of the "
|
|
|
|
|
"same rank as the memref type");
|
|
|
|
|
return success();
|
|
|
|
|
}
|
|
|
|
|
|
2019-11-22 07:52:02 -08:00
|
|
|
static void print(OpAsmPrinter &p, TransferReadOp op) {
|
2019-12-12 15:31:39 -08:00
|
|
|
p << op.getOperationName() << " " << op.memref() << "[" << op.indices()
|
|
|
|
|
<< "], " << op.padding() << " ";
|
2019-11-14 08:10:36 -08:00
|
|
|
p.printOptionalAttrDict(op.getAttrs());
|
2019-12-12 15:31:39 -08:00
|
|
|
p << " : " << op.getMemRefType() << ", " << op.getVectorType();
|
2018-12-14 09:31:17 -08:00
|
|
|
}
|
|
|
|
|
|
2020-01-14 14:06:12 +01:00
|
|
|
static ParseResult parseTransferReadOp(OpAsmParser &parser,
|
|
|
|
|
OperationState &result) {
|
2019-11-14 08:10:36 -08:00
|
|
|
llvm::SMLoc typesLoc;
|
Cleanup SuperVectorization dialect printing and parsing.
On the read side,
```
%3 = vector_transfer_read %arg0, %i2, %i1, %i0 {permutation_map: (d0, d1, d2)->(d2, d0)} : (memref<?x?x?xf32>, index, index, index) -> vector<32x256xf32>
```
becomes:
```
%3 = vector_transfer_read %arg0[%i2, %i1, %i0] {permutation_map: (d0, d1, d2)->(d2, d0)} : memref<?x?x?xf32>, vector<32x256xf32>
```
On the write side,
```
vector_transfer_write %0, %arg0, %c3, %c3 {permutation_map: (d0, d1)->(d0)} : vector<128xf32>, memref<?x?xf32>, index, index
```
becomes
```
vector_transfer_write %0, %arg0[%c3, %c3] {permutation_map: (d0, d1)->(d0)} : vector<128xf32>, memref<?x?xf32>
```
Documentation will be cleaned up in a followup commit that also extracts a proper .md from the top of the file comments.
PiperOrigin-RevId: 241021879
2019-03-29 11:48:20 -07:00
|
|
|
OpAsmParser::OperandType memrefInfo;
|
|
|
|
|
SmallVector<OpAsmParser::OperandType, 8> indexInfo;
|
2019-11-14 08:10:36 -08:00
|
|
|
OpAsmParser::OperandType paddingInfo;
|
Cleanup SuperVectorization dialect printing and parsing.
On the read side,
```
%3 = vector_transfer_read %arg0, %i2, %i1, %i0 {permutation_map: (d0, d1, d2)->(d2, d0)} : (memref<?x?x?xf32>, index, index, index) -> vector<32x256xf32>
```
becomes:
```
%3 = vector_transfer_read %arg0[%i2, %i1, %i0] {permutation_map: (d0, d1, d2)->(d2, d0)} : memref<?x?x?xf32>, vector<32x256xf32>
```
On the write side,
```
vector_transfer_write %0, %arg0, %c3, %c3 {permutation_map: (d0, d1)->(d0)} : vector<128xf32>, memref<?x?xf32>, index, index
```
becomes
```
vector_transfer_write %0, %arg0[%c3, %c3] {permutation_map: (d0, d1)->(d0)} : vector<128xf32>, memref<?x?xf32>
```
Documentation will be cleaned up in a followup commit that also extracts a proper .md from the top of the file comments.
PiperOrigin-RevId: 241021879
2019-03-29 11:48:20 -07:00
|
|
|
SmallVector<Type, 2> types;
|
2018-12-14 09:31:17 -08:00
|
|
|
// Parsing with support for optional paddingValue.
|
2019-09-20 11:36:49 -07:00
|
|
|
if (parser.parseOperand(memrefInfo) ||
|
|
|
|
|
parser.parseOperandList(indexInfo, OpAsmParser::Delimiter::Square) ||
|
2019-11-14 08:10:36 -08:00
|
|
|
parser.parseComma() || parser.parseOperand(paddingInfo) ||
|
2019-11-05 13:32:07 -08:00
|
|
|
parser.parseOptionalAttrDict(result.attributes) ||
|
2019-11-14 08:10:36 -08:00
|
|
|
parser.getCurrentLocation(&typesLoc) || parser.parseColonTypeList(types))
|
2019-05-06 22:01:31 -07:00
|
|
|
return failure();
|
Cleanup SuperVectorization dialect printing and parsing.
On the read side,
```
%3 = vector_transfer_read %arg0, %i2, %i1, %i0 {permutation_map: (d0, d1, d2)->(d2, d0)} : (memref<?x?x?xf32>, index, index, index) -> vector<32x256xf32>
```
becomes:
```
%3 = vector_transfer_read %arg0[%i2, %i1, %i0] {permutation_map: (d0, d1, d2)->(d2, d0)} : memref<?x?x?xf32>, vector<32x256xf32>
```
On the write side,
```
vector_transfer_write %0, %arg0, %c3, %c3 {permutation_map: (d0, d1)->(d0)} : vector<128xf32>, memref<?x?xf32>, index, index
```
becomes
```
vector_transfer_write %0, %arg0[%c3, %c3] {permutation_map: (d0, d1)->(d0)} : vector<128xf32>, memref<?x?xf32>
```
Documentation will be cleaned up in a followup commit that also extracts a proper .md from the top of the file comments.
PiperOrigin-RevId: 241021879
2019-03-29 11:48:20 -07:00
|
|
|
if (types.size() != 2)
|
2019-11-14 08:10:36 -08:00
|
|
|
return parser.emitError(typesLoc, "two types required");
|
2019-09-20 11:36:49 -07:00
|
|
|
auto indexType = parser.getBuilder().getIndexType();
|
2019-11-14 08:10:36 -08:00
|
|
|
MemRefType memRefType = types[0].dyn_cast<MemRefType>();
|
|
|
|
|
if (!memRefType)
|
|
|
|
|
return parser.emitError(typesLoc, "memref type required"), failure();
|
|
|
|
|
Type vectorType = types[1];
|
2019-05-06 22:01:31 -07:00
|
|
|
return failure(
|
2019-11-14 08:10:36 -08:00
|
|
|
parser.resolveOperand(memrefInfo, memRefType, result.operands) ||
|
2019-09-20 19:47:05 -07:00
|
|
|
parser.resolveOperands(indexInfo, indexType, result.operands) ||
|
2019-11-14 08:10:36 -08:00
|
|
|
parser.resolveOperand(paddingInfo, memRefType.getElementType(),
|
|
|
|
|
result.operands) ||
|
2019-09-20 19:47:05 -07:00
|
|
|
parser.addTypeToList(vectorType, result.types));
|
2018-12-14 09:31:17 -08:00
|
|
|
}
|
|
|
|
|
|
2019-11-22 07:52:02 -08:00
|
|
|
static LogicalResult verify(TransferReadOp op) {
|
2018-12-14 09:31:17 -08:00
|
|
|
// Consistency of elemental types in memref and vector.
|
2019-11-14 08:10:36 -08:00
|
|
|
MemRefType memrefType = op.getMemRefType();
|
|
|
|
|
VectorType vectorType = op.getVectorType();
|
2020-01-11 08:54:04 -08:00
|
|
|
auto paddingType = op.padding().getType();
|
2019-11-14 08:10:36 -08:00
|
|
|
auto permutationMap = op.permutation_map();
|
2019-12-19 16:04:59 -08:00
|
|
|
auto memrefElementType = memrefType.getElementType();
|
|
|
|
|
|
|
|
|
|
if (static_cast<int64_t>(op.indices().size()) != memrefType.getRank())
|
|
|
|
|
return op.emitOpError("requires ") << memrefType.getRank() << " indices";
|
|
|
|
|
|
|
|
|
|
if (failed(verifyTransferOp(op.getOperation(), memrefType, vectorType,
|
|
|
|
|
permutationMap)))
|
|
|
|
|
return failure();
|
|
|
|
|
|
|
|
|
|
if (auto memrefVectorElementType = memrefElementType.dyn_cast<VectorType>()) {
|
|
|
|
|
// Memref has vector element type.
|
|
|
|
|
// Check that 'memrefVectorElementType' and 'paddingType' types match.
|
|
|
|
|
if (memrefVectorElementType != paddingType)
|
|
|
|
|
return op.emitOpError(
|
|
|
|
|
"requires memref element type and padding type to match.");
|
|
|
|
|
|
|
|
|
|
} else {
|
|
|
|
|
// Check that 'paddingType' is valid to store in a vector type.
|
|
|
|
|
if (!VectorType::isValidElementType(paddingType))
|
|
|
|
|
return op.emitOpError("requires valid padding vector elemental type");
|
|
|
|
|
|
|
|
|
|
// Check that padding type and vector element types match.
|
|
|
|
|
if (paddingType != vectorType.getElementType())
|
|
|
|
|
return op.emitOpError(
|
|
|
|
|
"requires formal padding and vector of the same elemental type");
|
|
|
|
|
}
|
|
|
|
|
|
2018-12-14 09:31:17 -08:00
|
|
|
return verifyPermutationMap(permutationMap,
|
2019-11-14 08:10:36 -08:00
|
|
|
[&op](Twine t) { return op.emitOpError(t); });
|
2018-12-14 09:31:17 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
2019-11-22 07:52:02 -08:00
|
|
|
// TransferWriteOp
|
2018-12-14 09:31:17 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2019-11-22 07:52:02 -08:00
|
|
|
static LogicalResult verify(TransferWriteOp op) {
|
2018-12-14 09:31:17 -08:00
|
|
|
// Consistency of elemental types in memref and vector.
|
2019-11-14 08:10:36 -08:00
|
|
|
MemRefType memrefType = op.getMemRefType();
|
|
|
|
|
VectorType vectorType = op.getVectorType();
|
2019-12-19 16:04:59 -08:00
|
|
|
auto permutationMap = op.permutation_map();
|
|
|
|
|
|
2019-11-14 08:10:36 -08:00
|
|
|
if (llvm::size(op.indices()) != memrefType.getRank())
|
|
|
|
|
return op.emitOpError("requires ") << memrefType.getRank() << " indices";
|
2018-12-14 09:31:17 -08:00
|
|
|
|
2019-12-19 16:04:59 -08:00
|
|
|
if (failed(verifyTransferOp(op.getOperation(), memrefType, vectorType,
|
|
|
|
|
permutationMap)))
|
|
|
|
|
return failure();
|
|
|
|
|
|
2018-12-14 09:31:17 -08:00
|
|
|
return verifyPermutationMap(permutationMap,
|
2019-11-14 08:10:36 -08:00
|
|
|
[&op](Twine t) { return op.emitOpError(t); });
|
2018-12-14 09:31:17 -08:00
|
|
|
}
|
2018-12-17 14:10:52 -08:00
|
|
|
|
[mlir][VectorOps] Add ShapeCastOp to the vector ops dialect.
Summary:
Add ShapeCastOp to the vector ops dialect.
The shape_cast operation casts between an n-D source vector shape and a k-D result vector shape (the element type remains the same).
Reviewers: nicolasvasilache, aartbik
Reviewed By: nicolasvasilache
Subscribers: Joonsoo, merge_guards_bot, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, liufengdb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73635
2020-02-05 15:35:50 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// ShapeCastOp
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
/// Returns true if each element of 'a' is equal to the product of a contiguous
|
|
|
|
|
/// sequence of the elements of 'b'. Returns false otherwise.
|
|
|
|
|
static bool isValidShapeCast(ArrayRef<int64_t> a, ArrayRef<int64_t> b) {
|
|
|
|
|
unsigned rankA = a.size();
|
|
|
|
|
unsigned rankB = b.size();
|
|
|
|
|
assert(rankA < rankB);
|
|
|
|
|
|
|
|
|
|
unsigned i = 0;
|
|
|
|
|
unsigned j = 0;
|
|
|
|
|
while (i < rankA && j < rankB) {
|
|
|
|
|
int64_t dimA = a[i];
|
|
|
|
|
int64_t dimB = 1;
|
|
|
|
|
while (dimB < dimA && j < rankB)
|
|
|
|
|
dimB *= b[j++];
|
|
|
|
|
if (dimA != dimB)
|
|
|
|
|
break;
|
|
|
|
|
++i;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return i == rankA && j == rankB;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static LogicalResult verifyVectorShapeCast(Operation *op,
|
|
|
|
|
VectorType sourceVectorType,
|
|
|
|
|
VectorType resultVectorType) {
|
|
|
|
|
// Check that element type is the same.
|
|
|
|
|
if (sourceVectorType.getElementType() != resultVectorType.getElementType())
|
|
|
|
|
return op->emitOpError("source/result vectors must have same element type");
|
|
|
|
|
auto sourceShape = sourceVectorType.getShape();
|
|
|
|
|
auto resultShape = resultVectorType.getShape();
|
|
|
|
|
|
|
|
|
|
// Check that product of source dim sizes matches product of result dim sizes.
|
|
|
|
|
int64_t sourceDimProduct = std::accumulate(
|
|
|
|
|
sourceShape.begin(), sourceShape.end(), 1LL, std::multiplies<int64_t>{});
|
|
|
|
|
int64_t resultDimProduct = std::accumulate(
|
|
|
|
|
resultShape.begin(), resultShape.end(), 1LL, std::multiplies<int64_t>{});
|
|
|
|
|
if (sourceDimProduct != resultDimProduct)
|
|
|
|
|
return op->emitOpError("source/result number of elements must match");
|
|
|
|
|
|
|
|
|
|
// Check that expanding/contracting rank cases.
|
|
|
|
|
unsigned sourceRank = sourceVectorType.getRank();
|
|
|
|
|
unsigned resultRank = resultVectorType.getRank();
|
|
|
|
|
if (sourceRank < resultRank) {
|
|
|
|
|
if (!isValidShapeCast(sourceShape, resultShape))
|
|
|
|
|
return op->emitOpError("invalid shape cast");
|
|
|
|
|
} else if (sourceRank > resultRank) {
|
|
|
|
|
if (!isValidShapeCast(resultShape, sourceShape))
|
|
|
|
|
return op->emitOpError("invalid shape cast");
|
|
|
|
|
}
|
|
|
|
|
return success();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static LogicalResult verify(ShapeCastOp op) {
|
|
|
|
|
auto sourceVectorType = op.source().getType().dyn_cast_or_null<VectorType>();
|
|
|
|
|
auto resultVectorType = op.result().getType().dyn_cast_or_null<VectorType>();
|
|
|
|
|
|
|
|
|
|
// Check if source/result are of vector type.
|
|
|
|
|
if (sourceVectorType && resultVectorType)
|
|
|
|
|
return verifyVectorShapeCast(op, sourceVectorType, resultVectorType);
|
|
|
|
|
|
|
|
|
|
// Check if source/result are "tuple of vectors" type.
|
|
|
|
|
auto sourceTupleType = op.source().getType().dyn_cast_or_null<TupleType>();
|
|
|
|
|
auto resultTupleType = op.result().getType().dyn_cast_or_null<TupleType>();
|
|
|
|
|
if (!sourceTupleType || !resultTupleType)
|
|
|
|
|
return op.emitOpError("source/result must be of same type");
|
|
|
|
|
|
|
|
|
|
// Check that source/result tuple sizes are the same.
|
|
|
|
|
if (sourceTupleType.size() != resultTupleType.size())
|
|
|
|
|
return op.emitOpError("source/result tuples must be the same size");
|
|
|
|
|
|
|
|
|
|
// Check each source/result tuple element pair.
|
|
|
|
|
for (unsigned i = 0, e = sourceTupleType.size(); i < e; ++i)
|
|
|
|
|
if (failed(verifyVectorShapeCast(
|
|
|
|
|
op, sourceTupleType.getType(i).cast<VectorType>(),
|
|
|
|
|
resultTupleType.getType(i).cast<VectorType>())))
|
|
|
|
|
return failure();
|
|
|
|
|
|
|
|
|
|
return success();
|
|
|
|
|
}
|
|
|
|
|
|
2018-12-17 14:10:52 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2019-11-22 07:52:02 -08:00
|
|
|
// TypeCastOp
|
2018-12-17 14:10:52 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2019-11-14 08:10:36 -08:00
|
|
|
static MemRefType inferVectorTypeCastResultType(MemRefType t) {
|
|
|
|
|
return MemRefType::get({}, VectorType::get(t.getShape(), t.getElementType()));
|
2018-12-17 14:10:52 -08:00
|
|
|
}
|
|
|
|
|
|
2019-12-23 14:45:01 -08:00
|
|
|
void TypeCastOp::build(Builder *builder, OperationState &result, Value source) {
|
2019-11-14 08:10:36 -08:00
|
|
|
result.addOperands(source);
|
|
|
|
|
result.addTypes(
|
2020-01-11 08:54:04 -08:00
|
|
|
inferVectorTypeCastResultType(source.getType().cast<MemRefType>()));
|
2018-12-17 14:10:52 -08:00
|
|
|
}
|
|
|
|
|
|
2019-12-12 15:31:39 -08:00
|
|
|
static void print(OpAsmPrinter &p, TypeCastOp op) {
|
2020-01-11 08:54:04 -08:00
|
|
|
auto type = op.getOperand().getType().cast<MemRefType>();
|
|
|
|
|
p << op.getOperationName() << ' ' << op.memref() << " : " << type << " to "
|
2019-11-14 08:10:36 -08:00
|
|
|
<< inferVectorTypeCastResultType(type);
|
|
|
|
|
}
|
2018-12-17 14:10:52 -08:00
|
|
|
|
2019-12-12 15:31:39 -08:00
|
|
|
static LogicalResult verify(TypeCastOp op) {
|
2019-11-14 08:10:36 -08:00
|
|
|
auto resultType = inferVectorTypeCastResultType(op.getMemRefType());
|
|
|
|
|
if (op.getResultMemRefType() != resultType)
|
|
|
|
|
return op.emitOpError("expects result type to be: ") << resultType;
|
2019-04-02 13:09:34 -07:00
|
|
|
return success();
|
2018-12-17 14:10:52 -08:00
|
|
|
}
|
2019-08-09 05:58:19 -07:00
|
|
|
|
2019-12-16 06:38:33 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// TupleOp
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
static ParseResult parseTupleOp(OpAsmParser &parser, OperationState &result) {
|
|
|
|
|
SmallVector<OpAsmParser::OperandType, 4> operandInfos;
|
|
|
|
|
SmallVector<Type, 4> types;
|
|
|
|
|
auto loc = parser.getCurrentLocation();
|
|
|
|
|
auto *ctx = parser.getBuilder().getContext();
|
|
|
|
|
return failure(
|
|
|
|
|
parser.parseOperandList(operandInfos) ||
|
|
|
|
|
parser.parseOptionalAttrDict(result.attributes) ||
|
|
|
|
|
parser.parseColonTypeList(types) ||
|
|
|
|
|
parser.resolveOperands(operandInfos, types, loc, result.operands) ||
|
|
|
|
|
parser.addTypeToList(TupleType::get(types, ctx), result.types));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void print(OpAsmPrinter &p, TupleOp op) {
|
|
|
|
|
p << op.getOperationName() << ' ';
|
|
|
|
|
p.printOperands(op.getOperands());
|
|
|
|
|
p.printOptionalAttrDict(op.getAttrs());
|
|
|
|
|
p << " : ";
|
|
|
|
|
interleaveComma(op.getOperation()->getOperandTypes(), p);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static LogicalResult verify(TupleOp op) { return success(); }
|
|
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// TupleGetOp
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
static ParseResult parseTupleGetOp(OpAsmParser &parser,
|
|
|
|
|
OperationState &result) {
|
|
|
|
|
OpAsmParser::OperandType operandInfo;
|
|
|
|
|
IntegerAttr indexAttr;
|
|
|
|
|
StringRef indexAttrName = TupleGetOp::getIndexAttrName();
|
|
|
|
|
Type indexType = parser.getBuilder().getIndexType();
|
|
|
|
|
TupleType tupleType;
|
|
|
|
|
if (parser.parseOperand(operandInfo) || parser.parseComma() ||
|
|
|
|
|
parser.parseAttribute(indexAttr, indexType, indexAttrName,
|
|
|
|
|
result.attributes) ||
|
|
|
|
|
parser.parseOptionalAttrDict(result.attributes) ||
|
|
|
|
|
parser.parseColonType(tupleType) ||
|
|
|
|
|
parser.resolveOperand(operandInfo, tupleType, result.operands))
|
|
|
|
|
return failure();
|
|
|
|
|
if (indexAttr.getInt() < 0 ||
|
|
|
|
|
indexAttr.getInt() >= static_cast<int64_t>(tupleType.size()))
|
|
|
|
|
return failure();
|
|
|
|
|
parser.addTypeToList(tupleType.getType(indexAttr.getInt()), result.types);
|
|
|
|
|
return success();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void print(OpAsmPrinter &p, TupleGetOp op) {
|
2020-01-11 08:54:04 -08:00
|
|
|
p << op.getOperationName() << ' ' << op.getOperand() << ", " << op.index();
|
2019-12-16 06:38:33 -08:00
|
|
|
p.printOptionalAttrDict(op.getAttrs(),
|
|
|
|
|
/*elidedAttrs=*/{TupleGetOp::getIndexAttrName()});
|
2020-01-11 08:54:04 -08:00
|
|
|
p << " : " << op.getOperand().getType();
|
2019-12-16 06:38:33 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static LogicalResult verify(TupleGetOp op) {
|
2020-01-11 08:54:04 -08:00
|
|
|
auto tupleType = op.getOperand().getType().cast<TupleType>();
|
2019-12-17 13:10:07 -08:00
|
|
|
if (op.getIndex() < 0 ||
|
|
|
|
|
op.getIndex() >= static_cast<int64_t>(tupleType.size()))
|
2019-12-16 06:38:33 -08:00
|
|
|
return op.emitOpError("tuple get index out of range");
|
|
|
|
|
return success();
|
|
|
|
|
}
|
|
|
|
|
|
[mlir] [VectorOps] Implement vector tuple get folding
Summary: Rewrites get-i tup<a1,...,an> into ai
Reviewers: nicolasvasilache, rriddle, andydavis1
Reviewed By: nicolasvasilache, rriddle, andydavis1
Subscribers: merge_guards_bot, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, liufengdb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73213
2020-01-23 14:11:36 -08:00
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OpFoldResult TupleGetOp::fold(ArrayRef<Attribute> operands) {
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// Rewrite:
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// %t = vector.tuple .., %e_i, ..
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// %x = vector.tuple_get %t, i
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// into:
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// %t = vector.tuple .., %e_i, .. // one less use
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// %x = %e_i
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if (auto tupleOp = dyn_cast_or_null<TupleOp>(getOperand().getDefiningOp()))
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return tupleOp.getOperand(getIndex());
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return {};
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}
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2019-12-04 13:00:14 -08:00
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//===----------------------------------------------------------------------===//
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// ConstantMaskOp
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//===----------------------------------------------------------------------===//
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static LogicalResult verify(ConstantMaskOp &op) {
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// Verify that array attr size matches the rank of the vector result.
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2020-01-11 08:54:04 -08:00
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auto resultType = op.getResult().getType().cast<VectorType>();
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2019-12-04 13:00:14 -08:00
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if (static_cast<int64_t>(op.mask_dim_sizes().size()) != resultType.getRank())
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return op.emitOpError(
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"must specify array attr of size equal vector result rank");
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// Verify that each array attr element is in bounds of corresponding vector
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// result dimension size.
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auto resultShape = resultType.getShape();
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SmallVector<int64_t, 4> maskDimSizes;
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for (auto it : llvm::enumerate(op.mask_dim_sizes())) {
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int64_t attrValue = it.value().cast<IntegerAttr>().getInt();
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if (attrValue < 0 || attrValue > resultShape[it.index()])
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return op.emitOpError(
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"array attr of size out of bounds of vector result dimension size");
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maskDimSizes.push_back(attrValue);
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}
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// Verify that if one mask dim size is zero, they all should be zero (because
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// the mask region is a conjunction of each mask dimension interval).
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bool any_zeros = llvm::is_contained(maskDimSizes, 0);
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bool all_zeros = llvm::all_of(maskDimSizes, [](int64_t s) { return s == 0; });
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if (any_zeros && !all_zeros)
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return op.emitOpError("expected all mask dim sizes to be zeros, "
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"as a result of conjunction with zero mask dim");
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return success();
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}
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2019-12-03 11:55:09 -08:00
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//===----------------------------------------------------------------------===//
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// CreateMaskOp
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//===----------------------------------------------------------------------===//
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2019-12-12 15:31:39 -08:00
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static LogicalResult verify(CreateMaskOp op) {
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2019-12-03 11:55:09 -08:00
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// Verify that an operand was specified for each result vector each dimension.
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if (op.getNumOperands() !=
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2020-01-11 08:54:04 -08:00
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op.getResult().getType().cast<VectorType>().getRank())
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2019-12-03 11:55:09 -08:00
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return op.emitOpError(
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"must specify an operand for each result vector dimension");
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return success();
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}
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2019-12-04 13:00:14 -08:00
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namespace {
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// Pattern to rewrite a CreateMaskOp with a ConstantMaskOp.
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class CreateMaskFolder final : public OpRewritePattern<CreateMaskOp> {
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public:
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using OpRewritePattern<CreateMaskOp>::OpRewritePattern;
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PatternMatchResult matchAndRewrite(CreateMaskOp createMaskOp,
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PatternRewriter &rewriter) const override {
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// Return if any of 'createMaskOp' operands are not defined by a constant.
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2019-12-23 14:45:01 -08:00
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auto is_not_def_by_constant = [](Value operand) {
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2020-01-11 08:54:04 -08:00
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return !isa_and_nonnull<ConstantIndexOp>(operand.getDefiningOp());
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2019-12-04 13:00:14 -08:00
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};
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if (llvm::any_of(createMaskOp.operands(), is_not_def_by_constant))
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return matchFailure();
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// Gather constant mask dimension sizes.
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SmallVector<int64_t, 4> maskDimSizes;
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2019-12-22 21:59:55 -08:00
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for (auto operand : createMaskOp.operands()) {
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2020-01-11 08:54:04 -08:00
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auto defOp = operand.getDefiningOp();
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2019-12-04 13:00:14 -08:00
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maskDimSizes.push_back(cast<ConstantIndexOp>(defOp).getValue());
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}
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// Replace 'createMaskOp' with ConstantMaskOp.
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rewriter.replaceOpWithNewOp<ConstantMaskOp>(
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2020-01-11 08:54:04 -08:00
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createMaskOp, createMaskOp.getResult().getType(),
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2019-12-20 15:32:31 -08:00
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vector::getVectorSubscriptAttr(rewriter, maskDimSizes));
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2019-12-04 13:00:14 -08:00
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return matchSuccess();
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}
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};
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} // end anonymous namespace
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void CreateMaskOp::getCanonicalizationPatterns(
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OwningRewritePatternList &results, MLIRContext *context) {
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results.insert<CreateMaskFolder>(context);
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}
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2019-12-06 07:36:55 -08:00
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void mlir::vector::populateVectorToVectorCanonicalizationPatterns(
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OwningRewritePatternList &patterns, MLIRContext *context) {
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patterns.insert<CreateMaskFolder, StridedSliceConstantMaskFolder>(context);
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2019-11-20 14:43:15 -08:00
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}
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2019-08-09 05:58:19 -07:00
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namespace mlir {
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2019-11-22 07:52:02 -08:00
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namespace vector {
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2019-08-09 05:58:19 -07:00
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#define GET_OP_CLASSES
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2019-08-19 17:11:12 -07:00
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#include "mlir/Dialect/VectorOps/VectorOps.cpp.inc"
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2019-08-09 05:58:19 -07:00
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2019-11-22 07:52:02 -08:00
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} // namespace vector
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2019-08-09 05:58:19 -07:00
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} // namespace mlir
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