From 87345d2ad48f6be87c98e748423a3b9de74dbef9 Mon Sep 17 00:00:00 2001
From: Erick Ochoa Lopez <erick.ochoalopez@amd.com>
Date: Thu, 11 Dec 2025 08:44:19 -0500
Subject: [PATCH] [mlir][amdgpu] Add type conversion to populate method (NFC)
 (#171708)

* Renames populateAMDGPUMemorySpaceAttributeConversions to
populateAMDGPUTypeAndAttributeConversions.
* Adds TDMBaseType conversion to
populateAMDGPUTypeAndAttributeConversions.
---
 .../mlir/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.h    |  7 +++----
 mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp  | 12 ++++++------
 2 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/mlir/include/mlir/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.h b/mlir/include/mlir/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.h
index b550980c4ad0..44aae7b65a69 100644
--- a/mlir/include/mlir/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.h
+++ b/mlir/include/mlir/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.h
@@ -23,8 +23,8 @@ class Pass;
 #include "mlir/Conversion/Passes.h.inc"
 
 /// Note: This function will also add conversions for the AMDGPU-specific
-/// address spaces, but those can be added separately using
-/// populateAMDGPUMemorySpaceAttributeConversions().
+/// address spaces and types, but those can be added separately using
+/// populateAMDGPUTypeAndAttributeConversions().
 void populateAMDGPUToROCDLConversionPatterns(LLVMTypeConverter &converter,
                                              RewritePatternSet &patterns,
                                              amdgpu::Chipset chipset);
@@ -33,8 +33,7 @@ void populateAMDGPUToROCDLConversionPatterns(LLVMTypeConverter &converter,
 /// by mapping amdgpu::AddressSpace::fat_raw_buffer to ptr addrspace(7),
 /// amdgpu::AddressSpace::buffer_rsrc to ptr addrspace(8), and
 /// amdgpu::AddressSpace::fat_strided_buffer to ptr addrspace(9).
-void populateAMDGPUMemorySpaceAttributeConversions(
-    TypeConverter &typeConverter);
+void populateAMDGPUTypeAndAttributeConversions(TypeConverter &typeConverter);
 
 } // namespace mlir
 
diff --git a/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp b/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
index e3dacfff16aa..91154b846f56 100644
--- a/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+++ b/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
@@ -2725,10 +2725,6 @@ struct ConvertAMDGPUToROCDLPass
 
     RewritePatternSet patterns(ctx);
     LLVMTypeConverter converter(ctx);
-    converter.addConversion([&](TDMBaseType type) -> Type {
-      Type i32 = IntegerType::get(type.getContext(), 32);
-      return converter.convertType(VectorType::get(4, i32));
-    });
 
     populateAMDGPUToROCDLConversionPatterns(converter, patterns, *maybeChipset);
     populateGpuMemorySpaceAttributeConversions(
@@ -2754,7 +2750,7 @@ struct ConvertAMDGPUToROCDLPass
 };
 } // namespace
 
-void mlir::populateAMDGPUMemorySpaceAttributeConversions(
+void mlir::populateAMDGPUTypeAndAttributeConversions(
     TypeConverter &typeConverter) {
   typeConverter.addTypeAttributeConversion(
       [](BaseMemRefType type, amdgpu::AddressSpaceAttr as)
@@ -2771,12 +2767,16 @@ void mlir::populateAMDGPUMemorySpaceAttributeConversions(
         }
         return TypeConverter::AttributeConversionResult::abort();
       });
+  typeConverter.addConversion([&](TDMBaseType type) -> Type {
+    Type i32 = IntegerType::get(type.getContext(), 32);
+    return typeConverter.convertType(VectorType::get(4, i32));
+  });
 }
 
 void mlir::populateAMDGPUToROCDLConversionPatterns(LLVMTypeConverter &converter,
                                                    RewritePatternSet &patterns,
                                                    Chipset chipset) {
-  populateAMDGPUMemorySpaceAttributeConversions(converter);
+  populateAMDGPUTypeAndAttributeConversions(converter);
   patterns.add<
       FatRawBufferCastLowering,
       RawBufferOpLowering<RawBufferLoadOp, ROCDL::RawPtrBufferLoadOp>,