From 88928259173ba6fe99b20258fcde512d82b72a46 Mon Sep 17 00:00:00 2001
From: carlobertolli <carlo.bertolli@amd.com>
Date: Mon, 13 Oct 2025 15:38:28 -0500
Subject: [PATCH] [AMDGPU] Enable saving SHARED_BASE to VCC (#163244)

---
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp      | 2 +-
 llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir | 9 +++++++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index ec5c5bb349ac..a44a247184ea 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -899,7 +899,7 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     }
 
     if (DestReg == AMDGPU::VCC) {
-      if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
+      if (AMDGPU::SReg_64_EncodableRegClass.contains(SrcReg)) {
         BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
           .addReg(SrcReg, getKillRegState(KillSrc));
       } else {
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir b/llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
index 9553fcc1c51c..f11fe4aa6e00 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
@@ -58,6 +58,15 @@ body:             |
     $sgpr0_sgpr1 = COPY $src_shared_base
 ...
 
+---
+name: src_shared_base_to_vcc
+body:             |
+  bb.0:
+    ; GFX9-LABEL: name: src_shared_base_to_vcc
+    ; GFX9: $vcc = S_MOV_B64 $src_shared_base
+    $vcc = COPY $src_shared_base
+...
+
 ---
 name: sgpr96_aligned_src_dst
 body:             |