From 8ea3e9d9a2640097e10fe0bc80a0d670831bced6 Mon Sep 17 00:00:00 2001 From: Dmitry Preobrazhensky Date: Fri, 27 Aug 2021 17:16:22 +0300 Subject: [PATCH] [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - Added f16 omod modifier (bug 51386). - Corrected names of data types (bug 48638). - Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231). - Corrected description of integer operands (bug 51130). - Corrected description of 8-bit DS offsets (bug 51536). - Improved PERMLANE op_sel description. - Corrected *SAD* opcode types. --- llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst | 4105 +++++++++-------- llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst | 52 +- llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst | 2552 +++++----- llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst | 3402 +++++++------- llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst | 1218 ++--- llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst | 22 +- llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst | 22 +- llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst | 69 +- llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst | 187 +- llvm/docs/AMDGPU/AMDGPUAsmGFX90a.rst | 1534 +++--- .../{gfx10_src32_2.rst => gfx1011_src.rst} | 4 +- .../{gfx10_src32_4.rst => gfx1011_src_1.rst} | 4 +- .../{gfx10_src32_3.rst => gfx1011_src_2.rst} | 6 +- .../{gfx10_src32_1.rst => gfx1011_src_3.rst} | 6 +- llvm/docs/AMDGPU/gfx1011_type_dev.rst | 13 - ...ype_dev.rst => gfx1011_type_deviation.rst} | 8 +- .../{gfx7_vdst32_0.rst => gfx1011_vdst.rst} | 4 +- llvm/docs/AMDGPU/gfx1011_vdst32_0.rst | 17 - .../{gfx8_vsrc32_0.rst => gfx1011_vsrc.rst} | 4 +- llvm/docs/AMDGPU/gfx1011_vsrc32_0.rst | 17 - llvm/docs/AMDGPU/gfx10_attr.rst | 4 +- .../AMDGPU/{gfx7_ret.rst => gfx10_dst.rst} | 4 +- ..._mad_type_dev.rst => gfx10_fx_operand.rst} | 6 +- llvm/docs/AMDGPU/gfx10_hwreg.rst | 4 +- .../{gfx7_simm16.rst => gfx10_imm16.rst} | 4 +- .../{gfx8_uimm16.rst => gfx10_imm16_1.rst} | 4 +- .../{gfx8_bimm16.rst => gfx10_imm16_2.rst} | 4 +- llvm/docs/AMDGPU/gfx10_label.rst | 4 +- .../docs/AMDGPU/{gfx7_mod.rst => gfx10_m.rst} | 4 +- .../{gfx8_mod_sdwa_sext.rst => gfx10_m_1.rst} | 4 +- .../AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst | 13 - llvm/docs/AMDGPU/gfx10_msg.rst | 5 +- llvm/docs/AMDGPU/gfx10_opt.rst | 4 +- llvm/docs/AMDGPU/gfx10_param.rst | 4 +- .../{gfx8_perm_smem.rst => gfx10_probe.rst} | 6 +- ..._saddr_flat_global.rst => gfx10_saddr.rst} | 8 +- ...ddr_flat_scratch.rst => gfx10_saddr_1.rst} | 8 +- ...x10_base_smem_addr.rst => gfx10_sbase.rst} | 4 +- ...x7_base_smem_buf.rst => gfx10_sbase_1.rst} | 4 +- ...ase_smem_scratch.rst => gfx10_sbase_2.rst} | 4 +- ...data_smem_atomic32.rst => gfx10_sdata.rst} | 4 +- ...ta_smem_atomic64.rst => gfx10_sdata_1.rst} | 4 +- ...a_smem_atomic128.rst => gfx10_sdata_2.rst} | 4 +- ...{gfx10_sdata32_0.rst => gfx10_sdata_3.rst} | 4 +- ...{gfx10_sdata64_0.rst => gfx10_sdata_4.rst} | 4 +- ...{gfx8_sdata128_0.rst => gfx10_sdata_5.rst} | 4 +- .../{gfx10_wsdst.rst => gfx10_sdst.rst} | 4 +- .../{gfx10_sdst32_0.rst => gfx10_sdst_1.rst} | 4 +- .../{gfx10_sdst512_0.rst => gfx10_sdst_2.rst} | 4 +- .../{gfx10_sdst64_0.rst => gfx10_sdst_3.rst} | 4 +- .../{gfx8_sdst128_0.rst => gfx10_sdst_4.rst} | 4 +- .../{gfx8_sdst256_0.rst => gfx10_sdst_5.rst} | 4 +- .../{gfx10_sdst32_1.rst => gfx10_sdst_6.rst} | 4 +- .../{gfx10_sdst64_1.rst => gfx10_sdst_7.rst} | 4 +- .../{gfx10_sdst32_2.rst => gfx10_sdst_8.rst} | 4 +- .../{gfx8_bimm32.rst => gfx10_simm32.rst} | 6 +- .../{gfx8_fimm16.rst => gfx10_simm32_1.rst} | 6 +- .../{gfx8_fimm32.rst => gfx10_simm32_2.rst} | 6 +- ...gfx10_offset_buf.rst => gfx10_soffset.rst} | 4 +- ...set_smem_plain.rst => gfx10_soffset_1.rst} | 4 +- ...ffset_smem_buf.rst => gfx10_soffset_2.rst} | 4 +- .../{gfx10_src32_0.rst => gfx10_src.rst} | 4 +- .../{gfx10_src32_5.rst => gfx10_src_1.rst} | 6 +- .../{gfx1011_src32_0.rst => gfx10_src_2.rst} | 4 +- .../{gfx10_src64_0.rst => gfx10_src_3.rst} | 4 +- .../{gfx1011_src32_2.rst => gfx10_src_4.rst} | 6 +- .../{gfx7_vsrc32_1.rst => gfx10_src_5.rst} | 6 +- .../{gfx1011_src32_1.rst => gfx10_src_6.rst} | 4 +- .../{gfx10_src32_6.rst => gfx10_src_7.rst} | 4 +- .../{gfx1011_src32_3.rst => gfx10_src_8.rst} | 6 +- .../{gfx8_rsrc_mimg.rst => gfx10_srsrc.rst} | 4 +- .../{gfx8_rsrc_buf.rst => gfx10_srsrc_1.rst} | 4 +- .../{gfx8_samp_mimg.rst => gfx10_ssamp.rst} | 4 +- .../{gfx10_ssrc32_0.rst => gfx10_ssrc.rst} | 4 +- .../{gfx10_ssrc64_0.rst => gfx10_ssrc_1.rst} | 4 +- .../{gfx10_ssrc32_1.rst => gfx10_ssrc_2.rst} | 4 +- .../{gfx10_ssrc64_1.rst => gfx10_ssrc_3.rst} | 4 +- .../{gfx10_ssrc32_2.rst => gfx10_ssrc_4.rst} | 4 +- .../{gfx10_wssrc.rst => gfx10_ssrc_5.rst} | 4 +- .../{gfx10_ssrc32_3.rst => gfx10_ssrc_6.rst} | 4 +- .../{gfx10_ssrc32_4.rst => gfx10_ssrc_7.rst} | 4 +- .../{gfx10_ssrc32_5.rst => gfx10_ssrc_8.rst} | 4 +- llvm/docs/AMDGPU/gfx10_tgt.rst | 4 +- ..._type_dev.rst => gfx10_type_deviation.rst} | 8 +- .../{gfx7_addr_ds.rst => gfx10_vaddr.rst} | 4 +- .../{gfx7_addr_flat.rst => gfx10_vaddr_1.rst} | 4 +- llvm/docs/AMDGPU/gfx10_vaddr_2.rst | 20 + ...ddr_flat_scratch.rst => gfx10_vaddr_3.rst} | 6 +- ...{gfx10_addr_mimg.rst => gfx10_vaddr_4.rst} | 5 +- .../{gfx8_addr_buf.rst => gfx10_vaddr_5.rst} | 4 +- llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst | 20 - .../{gfx10_vcc_32.rst => gfx10_vcc.rst} | 4 +- .../{gfx8_vdata32_0.rst => gfx10_vdata.rst} | 4 +- llvm/docs/AMDGPU/gfx10_vdata0.rst | 17 + llvm/docs/AMDGPU/gfx10_vdata0_1.rst | 17 + llvm/docs/AMDGPU/gfx10_vdata1.rst | 17 + llvm/docs/AMDGPU/gfx10_vdata1_1.rst | 17 + .../{gfx7_vdata64_0.rst => gfx10_vdata_1.rst} | 4 +- ...a_buf_atomic128.rst => gfx10_vdata_10.rst} | 4 +- ...{gfx8_vdata128_0.rst => gfx10_vdata_2.rst} | 4 +- .../{gfx7_vdata96_0.rst => gfx10_vdata_3.rst} | 4 +- ..._mimg_atomic_reg.rst => gfx10_vdata_4.rst} | 4 +- ..._mimg_atomic_cmp.rst => gfx10_vdata_5.rst} | 5 +- ...a_mimg_store_d16.rst => gfx10_vdata_6.rst} | 5 +- ..._data_mimg_store.rst => gfx10_vdata_7.rst} | 5 +- ...ata_buf_atomic32.rst => gfx10_vdata_8.rst} | 4 +- ...ata_buf_atomic64.rst => gfx10_vdata_9.rst} | 4 +- .../{gfx8_vdst32_0.rst => gfx10_vdst.rst} | 4 +- .../{gfx8_vdst64_0.rst => gfx10_vdst_1.rst} | 4 +- ...{gfx7_dst_buf_64.rst => gfx10_vdst_10.rst} | 4 +- ...{gfx8_dst_buf_96.rst => gfx10_vdst_11.rst} | 4 +- ...gfx7_dst_buf_128.rst => gfx10_vdst_12.rst} | 4 +- ...gfx8_dst_buf_lds.rst => gfx10_vdst_13.rst} | 4 +- .../{gfx8_vdst128_0.rst => gfx10_vdst_2.rst} | 4 +- .../{gfx7_vdst96_0.rst => gfx10_vdst_3.rst} | 4 +- ...dst_flat_atomic32.rst => gfx10_vdst_4.rst} | 4 +- ...dst_flat_atomic64.rst => gfx10_vdst_5.rst} | 4 +- ..._dst_mimg_gather4.rst => gfx10_vdst_6.rst} | 4 +- ..._dst_mimg_regular.rst => gfx10_vdst_7.rst} | 4 +- ..._mimg_regular_d16.rst => gfx10_vdst_8.rst} | 5 +- .../{gfx7_dst_buf_32.rst => gfx10_vdst_9.rst} | 4 +- .../{gfx7_vsrc32_0.rst => gfx10_vsrc.rst} | 4 +- .../{gfx8_src_exp.rst => gfx10_vsrc_1.rst} | 4 +- .../{gfx7_vsrc128_0.rst => gfx10_vsrc_2.rst} | 4 +- .../{gfx8_vsrc64_0.rst => gfx10_vsrc_3.rst} | 4 +- llvm/docs/AMDGPU/gfx10_waitcnt.rst | 4 +- llvm/docs/AMDGPU/gfx7_attr.rst | 4 +- .../AMDGPU/{gfx8_ret.rst => gfx7_dst.rst} | 4 +- llvm/docs/AMDGPU/gfx7_hwreg.rst | 4 +- .../{gfx8_simm16.rst => gfx7_imm16.rst} | 4 +- .../{gfx7_uimm16.rst => gfx7_imm16_1.rst} | 4 +- .../{gfx7_bimm16.rst => gfx7_imm16_2.rst} | 4 +- llvm/docs/AMDGPU/gfx7_label.rst | 4 +- .../{gfx8_mod_vop3_abs_neg.rst => gfx7_m.rst} | 4 +- llvm/docs/AMDGPU/gfx7_msg.rst | 5 +- llvm/docs/AMDGPU/gfx7_opt.rst | 4 +- llvm/docs/AMDGPU/gfx7_param.rst | 4 +- ...{gfx8_base_smem_buf.rst => gfx7_sbase.rst} | 4 +- ...x7_base_smem_addr.rst => gfx7_sbase_1.rst} | 4 +- .../{gfx7_sdst32_0.rst => gfx7_sdst.rst} | 4 +- .../{gfx7_sdst512_0.rst => gfx7_sdst_1.rst} | 4 +- .../{gfx7_sdst64_0.rst => gfx7_sdst_2.rst} | 4 +- .../{gfx7_sdst128_0.rst => gfx7_sdst_3.rst} | 4 +- .../{gfx7_sdst256_0.rst => gfx7_sdst_4.rst} | 4 +- .../{gfx7_sdst32_1.rst => gfx7_sdst_5.rst} | 4 +- .../{gfx7_sdst64_1.rst => gfx7_sdst_6.rst} | 4 +- .../{gfx7_sdst32_2.rst => gfx7_sdst_7.rst} | 4 +- .../{gfx7_bimm32.rst => gfx7_simm32.rst} | 6 +- .../{gfx7_fimm32.rst => gfx7_simm32_1.rst} | 6 +- .../{gfx7_offset_buf.rst => gfx7_soffset.rst} | 4 +- ...fx7_offset_smem.rst => gfx7_soffset_1.rst} | 4 +- .../AMDGPU/{gfx7_src32_0.rst => gfx7_src.rst} | 4 +- llvm/docs/AMDGPU/gfx7_src64_2.rst | 17 - .../{gfx7_src64_0.rst => gfx7_src_1.rst} | 4 +- .../{gfx7_src32_6.rst => gfx7_src_10.rst} | 4 +- llvm/docs/AMDGPU/gfx7_src_2.rst | 17 + .../{gfx8_vsrc32_1.rst => gfx7_src_3.rst} | 6 +- .../{gfx7_src32_2.rst => gfx7_src_4.rst} | 4 +- .../{gfx7_src32_3.rst => gfx7_src_5.rst} | 4 +- .../{gfx7_src32_4.rst => gfx7_src_6.rst} | 4 +- .../{gfx7_src64_1.rst => gfx7_src_7.rst} | 4 +- .../{gfx7_src32_5.rst => gfx7_src_8.rst} | 4 +- .../{gfx7_src32_1.rst => gfx7_src_9.rst} | 4 +- .../{gfx7_rsrc_mimg.rst => gfx7_srsrc.rst} | 4 +- .../{gfx7_rsrc_buf.rst => gfx7_srsrc_1.rst} | 4 +- .../{gfx7_samp_mimg.rst => gfx7_ssamp.rst} | 4 +- .../{gfx7_ssrc32_0.rst => gfx7_ssrc.rst} | 4 +- .../{gfx7_ssrc64_0.rst => gfx7_ssrc_1.rst} | 4 +- .../{gfx7_ssrc32_6.rst => gfx7_ssrc_10.rst} | 4 +- .../{gfx7_ssrc32_1.rst => gfx7_ssrc_2.rst} | 4 +- .../{gfx7_ssrc32_2.rst => gfx7_ssrc_3.rst} | 4 +- .../{gfx7_ssrc64_1.rst => gfx7_ssrc_4.rst} | 4 +- .../{gfx7_ssrc32_3.rst => gfx7_ssrc_5.rst} | 4 +- .../{gfx7_ssrc64_2.rst => gfx7_ssrc_6.rst} | 4 +- .../{gfx7_ssrc64_3.rst => gfx7_ssrc_7.rst} | 4 +- .../{gfx7_ssrc32_4.rst => gfx7_ssrc_8.rst} | 4 +- .../{gfx7_ssrc32_5.rst => gfx7_ssrc_9.rst} | 4 +- llvm/docs/AMDGPU/gfx7_tgt.rst | 4 +- ...8_type_dev.rst => gfx7_type_deviation.rst} | 8 +- .../{gfx8_addr_ds.rst => gfx7_vaddr.rst} | 4 +- .../{gfx8_addr_flat.rst => gfx7_vaddr_1.rst} | 4 +- .../{gfx7_addr_mimg.rst => gfx7_vaddr_2.rst} | 4 +- .../{gfx7_addr_buf.rst => gfx7_vaddr_3.rst} | 4 +- .../AMDGPU/{gfx7_vcc_64.rst => gfx7_vcc.rst} | 4 +- .../{gfx7_vdata32_0.rst => gfx7_vdata.rst} | 4 +- llvm/docs/AMDGPU/gfx7_vdata0.rst | 17 + llvm/docs/AMDGPU/gfx7_vdata0_1.rst | 17 + llvm/docs/AMDGPU/gfx7_vdata1.rst | 17 + llvm/docs/AMDGPU/gfx7_vdata1_1.rst | 17 + .../{gfx8_vdata64_0.rst => gfx7_vdata_1.rst} | 4 +- .../{gfx7_vdata128_0.rst => gfx7_vdata_2.rst} | 4 +- .../{gfx8_vdata96_0.rst => gfx7_vdata_3.rst} | 4 +- ...a_mimg_atomic_reg.rst => gfx7_vdata_4.rst} | 4 +- ...a_mimg_atomic_cmp.rst => gfx7_vdata_5.rst} | 5 +- ...8_data_mimg_store.rst => gfx7_vdata_6.rst} | 5 +- ...data_buf_atomic32.rst => gfx7_vdata_7.rst} | 4 +- ...data_buf_atomic64.rst => gfx7_vdata_8.rst} | 4 +- ...ata_buf_atomic128.rst => gfx7_vdata_9.rst} | 4 +- .../{gfx10_vdst32_0.rst => gfx7_vdst.rst} | 4 +- .../{gfx7_vdst64_0.rst => gfx7_vdst_1.rst} | 4 +- .../{gfx7_dst_buf_96.rst => gfx7_vdst_10.rst} | 4 +- ...{gfx8_dst_buf_128.rst => gfx7_vdst_11.rst} | 4 +- ...{gfx7_dst_buf_lds.rst => gfx7_vdst_12.rst} | 4 +- .../{gfx7_vdst128_0.rst => gfx7_vdst_2.rst} | 4 +- .../{gfx8_vdst96_0.rst => gfx7_vdst_3.rst} | 4 +- ..._dst_flat_atomic32.rst => gfx7_vdst_4.rst} | 4 +- ..._dst_flat_atomic64.rst => gfx7_vdst_5.rst} | 4 +- ...7_dst_mimg_gather4.rst => gfx7_vdst_6.rst} | 4 +- ...8_dst_mimg_regular.rst => gfx7_vdst_7.rst} | 4 +- .../{gfx8_dst_buf_32.rst => gfx7_vdst_8.rst} | 4 +- .../{gfx8_dst_buf_64.rst => gfx7_vdst_9.rst} | 4 +- .../{gfx7_src_exp.rst => gfx7_vsrc.rst} | 4 +- .../{gfx10_vsrc32_0.rst => gfx7_vsrc_1.rst} | 4 +- .../{gfx8_vsrc128_0.rst => gfx7_vsrc_2.rst} | 4 +- .../{gfx7_vsrc64_0.rst => gfx7_vsrc_3.rst} | 4 +- llvm/docs/AMDGPU/gfx7_waitcnt.rst | 4 +- llvm/docs/AMDGPU/gfx8_attr.rst | 4 +- .../AMDGPU/{gfx10_ret.rst => gfx8_dst.rst} | 4 +- llvm/docs/AMDGPU/gfx8_hwreg.rst | 4 +- llvm/docs/AMDGPU/gfx8_imask.rst | 4 +- .../{gfx10_simm16.rst => gfx8_imm16.rst} | 4 +- .../{gfx10_uimm16.rst => gfx8_imm16_1.rst} | 4 +- .../{gfx10_bimm16.rst => gfx8_imm16_2.rst} | 4 +- llvm/docs/AMDGPU/gfx8_label.rst | 4 +- .../{gfx10_mod_sdwa_sext.rst => gfx8_m.rst} | 4 +- ...fx10_mod_vop3_abs_neg.rst => gfx8_m_1.rst} | 4 +- .../docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst | 13 - llvm/docs/AMDGPU/gfx8_msg.rst | 5 +- llvm/docs/AMDGPU/gfx8_opt.rst | 4 +- llvm/docs/AMDGPU/gfx8_param.rst | 4 +- .../{gfx10_perm_smem.rst => gfx8_probe.rst} | 6 +- ...gfx8_base_smem_addr.rst => gfx8_sbase.rst} | 6 +- ...x10_base_smem_buf.rst => gfx8_sbase_1.rst} | 4 +- .../{gfx8_sdata32_0.rst => gfx8_sdata.rst} | 6 +- .../{gfx8_sdata64_0.rst => gfx8_sdata_1.rst} | 6 +- ...{gfx10_sdata128_0.rst => gfx8_sdata_2.rst} | 4 +- .../{gfx8_sdst32_0.rst => gfx8_sdst.rst} | 6 +- llvm/docs/AMDGPU/gfx8_sdst32_1.rst | 17 - .../{gfx8_sdst512_0.rst => gfx8_sdst_1.rst} | 4 +- .../{gfx8_sdst64_0.rst => gfx8_sdst_2.rst} | 6 +- .../{gfx10_sdst128_0.rst => gfx8_sdst_3.rst} | 4 +- .../{gfx10_sdst256_0.rst => gfx8_sdst_4.rst} | 4 +- llvm/docs/AMDGPU/gfx8_sdst_5.rst | 17 + .../{gfx8_sdst64_1.rst => gfx8_sdst_6.rst} | 6 +- .../{gfx8_sdst32_2.rst => gfx8_sdst_7.rst} | 6 +- .../{gfx10_bimm32.rst => gfx8_simm32.rst} | 6 +- .../{gfx10_fimm16.rst => gfx8_simm32_1.rst} | 6 +- .../{gfx10_fimm32.rst => gfx8_simm32_2.rst} | 6 +- .../{gfx8_offset_buf.rst => gfx8_soffset.rst} | 6 +- ...ffset_smem_load.rst => gfx8_soffset_1.rst} | 6 +- ...fset_smem_store.rst => gfx8_soffset_2.rst} | 4 +- llvm/docs/AMDGPU/gfx8_src.rst | 17 + llvm/docs/AMDGPU/gfx8_src32_0.rst | 17 - llvm/docs/AMDGPU/gfx8_src32_1.rst | 17 - llvm/docs/AMDGPU/gfx8_src32_2.rst | 17 - llvm/docs/AMDGPU/gfx8_src32_3.rst | 17 - llvm/docs/AMDGPU/gfx8_src32_4.rst | 17 - llvm/docs/AMDGPU/gfx8_src32_5.rst | 17 - llvm/docs/AMDGPU/gfx8_src32_6.rst | 17 - llvm/docs/AMDGPU/gfx8_src32_7.rst | 17 - llvm/docs/AMDGPU/gfx8_src64_0.rst | 17 - llvm/docs/AMDGPU/gfx8_src64_1.rst | 17 - llvm/docs/AMDGPU/gfx8_src_1.rst | 17 + llvm/docs/AMDGPU/gfx8_src_10.rst | 17 + llvm/docs/AMDGPU/gfx8_src_2.rst | 17 + .../{gfx10_vsrc32_1.rst => gfx8_src_3.rst} | 6 +- llvm/docs/AMDGPU/gfx8_src_4.rst | 17 + .../{gfx8_ssrc64_0.rst => gfx8_src_5.rst} | 10 +- llvm/docs/AMDGPU/gfx8_src_6.rst | 17 + .../{gfx8_ssrc64_2.rst => gfx8_src_7.rst} | 10 +- llvm/docs/AMDGPU/gfx8_src_8.rst | 17 + llvm/docs/AMDGPU/gfx8_src_9.rst | 17 + .../{gfx10_rsrc_mimg.rst => gfx8_srsrc.rst} | 4 +- .../{gfx10_rsrc_buf.rst => gfx8_srsrc_1.rst} | 4 +- .../{gfx10_samp_mimg.rst => gfx8_ssamp.rst} | 4 +- llvm/docs/AMDGPU/gfx8_ssrc.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc32_0.rst | 17 - llvm/docs/AMDGPU/gfx8_ssrc32_2.rst | 17 - llvm/docs/AMDGPU/gfx8_ssrc32_3.rst | 17 - llvm/docs/AMDGPU/gfx8_ssrc32_4.rst | 17 - llvm/docs/AMDGPU/gfx8_ssrc64_3.rst | 17 - llvm/docs/AMDGPU/gfx8_ssrc_1.rst | 17 + .../{gfx8_ssrc32_1.rst => gfx8_ssrc_2.rst} | 6 +- .../{gfx8_ssrc64_1.rst => gfx8_ssrc_3.rst} | 6 +- llvm/docs/AMDGPU/gfx8_ssrc_4.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc_5.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc_6.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc_7.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc_8.rst | 17 + llvm/docs/AMDGPU/gfx8_tgt.rst | 4 +- ...6_type_dev.rst => gfx8_type_deviation.rst} | 8 +- .../{gfx10_addr_ds.rst => gfx8_vaddr.rst} | 4 +- .../{gfx10_addr_flat.rst => gfx8_vaddr_1.rst} | 4 +- .../{gfx8_addr_mimg.rst => gfx8_vaddr_2.rst} | 4 +- .../{gfx10_addr_buf.rst => gfx8_vaddr_3.rst} | 4 +- .../AMDGPU/{gfx8_vcc_64.rst => gfx8_vcc.rst} | 4 +- .../{gfx10_vdata32_0.rst => gfx8_vdata.rst} | 4 +- llvm/docs/AMDGPU/gfx8_vdata0.rst | 17 + llvm/docs/AMDGPU/gfx8_vdata0_1.rst | 17 + llvm/docs/AMDGPU/gfx8_vdata1.rst | 17 + llvm/docs/AMDGPU/gfx8_vdata1_1.rst | 17 + .../{gfx10_vdata64_0.rst => gfx8_vdata_1.rst} | 4 +- ..._data_buf_d16_96.rst => gfx8_vdata_10.rst} | 4 +- ...data_buf_d16_128.rst => gfx8_vdata_11.rst} | 4 +- ...ata_buf_atomic32.rst => gfx8_vdata_12.rst} | 4 +- ...ata_buf_atomic64.rst => gfx8_vdata_13.rst} | 4 +- ...ta_buf_atomic128.rst => gfx8_vdata_14.rst} | 4 +- ...{gfx10_vdata128_0.rst => gfx8_vdata_2.rst} | 4 +- .../{gfx10_vdata96_0.rst => gfx8_vdata_3.rst} | 4 +- ...a_mimg_atomic_reg.rst => gfx8_vdata_4.rst} | 4 +- ...a_mimg_atomic_cmp.rst => gfx8_vdata_5.rst} | 5 +- ...ta_mimg_store_d16.rst => gfx8_vdata_6.rst} | 5 +- ...0_data_mimg_store.rst => gfx8_vdata_7.rst} | 5 +- ...8_data_buf_d16_32.rst => gfx8_vdata_8.rst} | 4 +- ...8_data_buf_d16_64.rst => gfx8_vdata_9.rst} | 4 +- .../{gfx900_vdst32_0.rst => gfx8_vdst.rst} | 4 +- .../{gfx10_vdst64_0.rst => gfx8_vdst_1.rst} | 4 +- ...x8_dst_buf_d16_64.rst => gfx8_vdst_10.rst} | 4 +- ...x8_dst_buf_d16_96.rst => gfx8_vdst_11.rst} | 4 +- ...8_dst_buf_d16_128.rst => gfx8_vdst_12.rst} | 4 +- ...{gfx10_dst_buf_32.rst => gfx8_vdst_13.rst} | 4 +- ...{gfx10_dst_buf_64.rst => gfx8_vdst_14.rst} | 4 +- ...{gfx10_dst_buf_96.rst => gfx8_vdst_15.rst} | 4 +- ...gfx10_dst_buf_128.rst => gfx8_vdst_16.rst} | 4 +- ...gfx10_dst_buf_lds.rst => gfx8_vdst_17.rst} | 4 +- .../{gfx10_vdst128_0.rst => gfx8_vdst_2.rst} | 4 +- .../{gfx10_vdst96_0.rst => gfx8_vdst_3.rst} | 4 +- ..._dst_flat_atomic32.rst => gfx8_vdst_4.rst} | 4 +- ..._dst_flat_atomic64.rst => gfx8_vdst_5.rst} | 4 +- ...8_dst_mimg_gather4.rst => gfx8_vdst_6.rst} | 4 +- ...0_dst_mimg_regular.rst => gfx8_vdst_7.rst} | 4 +- ...t_mimg_regular_d16.rst => gfx8_vdst_8.rst} | 5 +- ...fx8_dst_buf_d16_32.rst => gfx8_vdst_9.rst} | 4 +- .../{gfx10_src_exp.rst => gfx8_vsrc.rst} | 4 +- .../{gfx906_vsrc32_0.rst => gfx8_vsrc_1.rst} | 4 +- .../{gfx10_vsrc128_0.rst => gfx8_vsrc_2.rst} | 4 +- .../{gfx10_vsrc64_0.rst => gfx8_vsrc_3.rst} | 4 +- llvm/docs/AMDGPU/gfx8_waitcnt.rst | 4 +- ...mad_type_dev.rst => gfx900_fx_operand.rst} | 6 +- ...x900_mod_vop3_abs_neg.rst => gfx900_m.rst} | 4 +- llvm/docs/AMDGPU/gfx900_src.rst | 17 + llvm/docs/AMDGPU/gfx900_src32_0.rst | 17 - llvm/docs/AMDGPU/gfx900_src32_1.rst | 17 - llvm/docs/AMDGPU/gfx900_src_1.rst | 17 + llvm/docs/AMDGPU/gfx900_vdst.rst | 17 + ...mad_type_dev.rst => gfx904_fx_operand.rst} | 6 +- llvm/docs/AMDGPU/gfx904_m.rst | 13 + llvm/docs/AMDGPU/gfx904_mod_vop3_abs_neg.rst | 13 - llvm/docs/AMDGPU/gfx904_src.rst | 17 + llvm/docs/AMDGPU/gfx904_src32_0.rst | 17 - llvm/docs/AMDGPU/gfx904_src32_1.rst | 17 - llvm/docs/AMDGPU/gfx904_src_1.rst | 17 + llvm/docs/AMDGPU/gfx904_vdst.rst | 17 + llvm/docs/AMDGPU/gfx904_vdst32_0.rst | 17 - ...mad_type_dev.rst => gfx906_fx_operand.rst} | 6 +- llvm/docs/AMDGPU/gfx906_m.rst | 13 + ...fx906_mod_sdwa_sext.rst => gfx906_m_1.rst} | 4 +- .../AMDGPU/gfx906_mod_dpp_sdwa_abs_neg.rst | 13 - llvm/docs/AMDGPU/gfx906_mod_vop3_abs_neg.rst | 13 - llvm/docs/AMDGPU/gfx906_src.rst | 17 + llvm/docs/AMDGPU/gfx906_src32_0.rst | 17 - llvm/docs/AMDGPU/gfx906_src32_1.rst | 17 - llvm/docs/AMDGPU/gfx906_src32_2.rst | 17 - llvm/docs/AMDGPU/gfx906_src32_3.rst | 17 - llvm/docs/AMDGPU/gfx906_src32_4.rst | 17 - llvm/docs/AMDGPU/gfx906_src_1.rst | 17 + llvm/docs/AMDGPU/gfx906_src_2.rst | 17 + llvm/docs/AMDGPU/gfx906_src_3.rst | 17 + llvm/docs/AMDGPU/gfx906_src_4.rst | 17 + llvm/docs/AMDGPU/gfx906_type_deviation.rst | 13 + llvm/docs/AMDGPU/gfx906_vdst.rst | 17 + llvm/docs/AMDGPU/gfx906_vdst32_0.rst | 17 - llvm/docs/AMDGPU/gfx906_vsrc.rst | 17 + .../AMDGPU/{gfx908_ret.rst => gfx908_dst.rst} | 4 +- llvm/docs/AMDGPU/gfx908_fx_operand.rst | 16 + llvm/docs/AMDGPU/gfx908_m.rst | 13 + ...fx908_mod_sdwa_sext.rst => gfx908_m_1.rst} | 4 +- llvm/docs/AMDGPU/gfx908_mad_type_dev.rst | 16 - .../AMDGPU/gfx908_mod_dpp_sdwa_abs_neg.rst | 13 - llvm/docs/AMDGPU/gfx908_mod_vop3_abs_neg.rst | 13 - llvm/docs/AMDGPU/gfx908_opt.rst | 4 +- ...saddr_flat_global.rst => gfx908_saddr.rst} | 8 +- ...x908_offset_buf.rst => gfx908_soffset.rst} | 6 +- llvm/docs/AMDGPU/gfx908_src.rst | 17 + llvm/docs/AMDGPU/gfx908_src32_0.rst | 17 - llvm/docs/AMDGPU/gfx908_src32_1.rst | 17 - llvm/docs/AMDGPU/gfx908_src32_2.rst | 17 - llvm/docs/AMDGPU/gfx908_src32_4.rst | 17 - llvm/docs/AMDGPU/gfx908_src32_5.rst | 17 - llvm/docs/AMDGPU/gfx908_src_1.rst | 17 + llvm/docs/AMDGPU/gfx908_src_2.rst | 17 + .../{gfx908_src32_3.rst => gfx908_src_3.rst} | 6 +- llvm/docs/AMDGPU/gfx908_src_4.rst | 17 + llvm/docs/AMDGPU/gfx908_src_5.rst | 17 + .../{gfx908_rsrc_buf.rst => gfx908_srsrc.rst} | 4 +- llvm/docs/AMDGPU/gfx908_type_dev.rst | 13 - llvm/docs/AMDGPU/gfx908_type_deviation.rst | 13 + llvm/docs/AMDGPU/gfx908_vaddr.rst | 20 + ...gfx908_addr_buf.rst => gfx908_vaddr_1.rst} | 4 +- llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst | 20 - ...{gfx908_vdata32_0.rst => gfx908_vdata.rst} | 4 +- ...ta_buf_atomic32.rst => gfx908_vdata_1.rst} | 4 +- ..._dst_flat_atomic32.rst => gfx908_vdst.rst} | 4 +- llvm/docs/AMDGPU/gfx908_vdst32_0.rst | 17 - llvm/docs/AMDGPU/gfx908_vdst_1.rst | 17 + ...{gfx908_adst32_0.rst => gfx908_vdst_2.rst} | 6 +- ...gfx908_adst128_0.rst => gfx908_vdst_3.rst} | 6 +- ...gfx908_adst512_0.rst => gfx908_vdst_4.rst} | 6 +- ...fx908_adst1024_0.rst => gfx908_vdst_5.rst} | 6 +- llvm/docs/AMDGPU/gfx908_vsrc.rst | 17 + llvm/docs/AMDGPU/gfx908_vsrc32_0.rst | 17 - ...{gfx908_asrc32_0.rst => gfx908_vsrc_1.rst} | 6 +- ...gfx908_vasrc64_0.rst => gfx908_vsrc_2.rst} | 6 +- ...gfx908_asrc128_0.rst => gfx908_vsrc_3.rst} | 6 +- ...gfx908_vasrc32_0.rst => gfx908_vsrc_4.rst} | 6 +- ...gfx908_asrc512_0.rst => gfx908_vsrc_5.rst} | 6 +- ...fx908_asrc1024_0.rst => gfx908_vsrc_6.rst} | 6 +- llvm/docs/AMDGPU/gfx90a_src_10.rst | 2 +- llvm/docs/AMDGPU/gfx90a_src_11.rst | 2 +- llvm/docs/AMDGPU/gfx90a_src_3.rst | 2 +- llvm/docs/AMDGPU/gfx90a_src_4.rst | 2 +- llvm/docs/AMDGPU/gfx90a_src_6.rst | 2 +- llvm/docs/AMDGPU/gfx90a_src_7.rst | 2 +- llvm/docs/AMDGPU/gfx90a_src_8.rst | 2 +- llvm/docs/AMDGPU/gfx90a_src_9.rst | 2 +- llvm/docs/AMDGPU/gfx90a_type_deviation.rst | 2 +- llvm/docs/AMDGPU/gfx9_type_deviation.rst | 2 +- llvm/docs/AMDGPUInstructionNotation.rst | 29 +- llvm/docs/AMDGPUInstructionSyntax.rst | 33 +- llvm/docs/AMDGPUModifierSyntax.rst | 77 +- 430 files changed, 8329 insertions(+), 8099 deletions(-) rename llvm/docs/AMDGPU/{gfx10_src32_2.rst => gfx1011_src.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_src32_4.rst => gfx1011_src_1.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_src32_3.rst => gfx1011_src_2.rst} (81%) rename llvm/docs/AMDGPU/{gfx10_src32_1.rst => gfx1011_src_3.rst} (77%) delete mode 100644 llvm/docs/AMDGPU/gfx1011_type_dev.rst rename llvm/docs/AMDGPU/{gfx10_type_dev.rst => gfx1011_type_deviation.rst} (69%) rename llvm/docs/AMDGPU/{gfx7_vdst32_0.rst => gfx1011_vdst.rst} (86%) delete mode 100644 llvm/docs/AMDGPU/gfx1011_vdst32_0.rst rename llvm/docs/AMDGPU/{gfx8_vsrc32_0.rst => gfx1011_vsrc.rst} (86%) delete mode 100644 llvm/docs/AMDGPU/gfx1011_vsrc32_0.rst rename llvm/docs/AMDGPU/{gfx7_ret.rst => gfx10_dst.rst} (88%) rename llvm/docs/AMDGPU/{gfx10_mad_type_dev.rst => gfx10_fx_operand.rst} (89%) rename llvm/docs/AMDGPU/{gfx7_simm16.rst => gfx10_imm16.rst} (89%) rename llvm/docs/AMDGPU/{gfx8_uimm16.rst => gfx10_imm16_1.rst} (89%) rename llvm/docs/AMDGPU/{gfx8_bimm16.rst => gfx10_imm16_2.rst} (89%) rename llvm/docs/AMDGPU/{gfx7_mod.rst => gfx10_m.rst} (88%) rename llvm/docs/AMDGPU/{gfx8_mod_sdwa_sext.rst => gfx10_m_1.rst} (85%) delete mode 100644 llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst rename llvm/docs/AMDGPU/{gfx8_perm_smem.rst => gfx10_probe.rst} (93%) rename llvm/docs/AMDGPU/{gfx10_saddr_flat_global.rst => gfx10_saddr.rst} (64%) rename llvm/docs/AMDGPU/{gfx10_saddr_flat_scratch.rst => gfx10_saddr_1.rst} (62%) rename llvm/docs/AMDGPU/{gfx10_base_smem_addr.rst => gfx10_sbase.rst} (87%) rename llvm/docs/AMDGPU/{gfx7_base_smem_buf.rst => gfx10_sbase_1.rst} (88%) rename llvm/docs/AMDGPU/{gfx10_base_smem_scratch.rst => gfx10_sbase_2.rst} (88%) rename llvm/docs/AMDGPU/{gfx10_data_smem_atomic32.rst => gfx10_sdata.rst} (90%) rename llvm/docs/AMDGPU/{gfx10_data_smem_atomic64.rst => gfx10_sdata_1.rst} (90%) rename llvm/docs/AMDGPU/{gfx10_data_smem_atomic128.rst => gfx10_sdata_2.rst} (88%) rename llvm/docs/AMDGPU/{gfx10_sdata32_0.rst => gfx10_sdata_3.rst} (88%) rename llvm/docs/AMDGPU/{gfx10_sdata64_0.rst => gfx10_sdata_4.rst} (88%) rename llvm/docs/AMDGPU/{gfx8_sdata128_0.rst => gfx10_sdata_5.rst} (87%) rename llvm/docs/AMDGPU/{gfx10_wsdst.rst => gfx10_sdst.rst} (89%) rename llvm/docs/AMDGPU/{gfx10_sdst32_0.rst => gfx10_sdst_1.rst} (88%) rename llvm/docs/AMDGPU/{gfx10_sdst512_0.rst => gfx10_sdst_2.rst} (87%) rename llvm/docs/AMDGPU/{gfx10_sdst64_0.rst => gfx10_sdst_3.rst} (88%) rename llvm/docs/AMDGPU/{gfx8_sdst128_0.rst => gfx10_sdst_4.rst} (87%) rename llvm/docs/AMDGPU/{gfx8_sdst256_0.rst => gfx10_sdst_5.rst} (87%) rename llvm/docs/AMDGPU/{gfx10_sdst32_1.rst => gfx10_sdst_6.rst} (90%) rename llvm/docs/AMDGPU/{gfx10_sdst64_1.rst => gfx10_sdst_7.rst} (89%) rename llvm/docs/AMDGPU/{gfx10_sdst32_2.rst => gfx10_sdst_8.rst} (88%) rename llvm/docs/AMDGPU/{gfx8_bimm32.rst => gfx10_simm32.rst} (87%) rename llvm/docs/AMDGPU/{gfx8_fimm16.rst => gfx10_simm32_1.rst} (90%) rename llvm/docs/AMDGPU/{gfx8_fimm32.rst => gfx10_simm32_2.rst} (90%) rename llvm/docs/AMDGPU/{gfx10_offset_buf.rst => gfx10_soffset.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_offset_smem_plain.rst => gfx10_soffset_1.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_offset_smem_buf.rst => gfx10_soffset_2.rst} (90%) rename llvm/docs/AMDGPU/{gfx10_src32_0.rst => gfx10_src.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_src32_5.rst => gfx10_src_1.rst} (87%) rename llvm/docs/AMDGPU/{gfx1011_src32_0.rst => gfx10_src_2.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_src64_0.rst => gfx10_src_3.rst} (92%) rename llvm/docs/AMDGPU/{gfx1011_src32_2.rst => gfx10_src_4.rst} (81%) rename llvm/docs/AMDGPU/{gfx7_vsrc32_1.rst => gfx10_src_5.rst} (86%) rename llvm/docs/AMDGPU/{gfx1011_src32_1.rst => gfx10_src_6.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_src32_6.rst => gfx10_src_7.rst} (92%) rename llvm/docs/AMDGPU/{gfx1011_src32_3.rst => gfx10_src_8.rst} (86%) rename llvm/docs/AMDGPU/{gfx8_rsrc_mimg.rst => gfx10_srsrc.rst} (90%) rename llvm/docs/AMDGPU/{gfx8_rsrc_buf.rst => gfx10_srsrc_1.rst} (89%) rename llvm/docs/AMDGPU/{gfx8_samp_mimg.rst => gfx10_ssamp.rst} (89%) rename llvm/docs/AMDGPU/{gfx10_ssrc32_0.rst => gfx10_ssrc.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_ssrc64_0.rst => gfx10_ssrc_1.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_ssrc32_1.rst => gfx10_ssrc_2.rst} (88%) rename llvm/docs/AMDGPU/{gfx10_ssrc64_1.rst => gfx10_ssrc_3.rst} (88%) rename llvm/docs/AMDGPU/{gfx10_ssrc32_2.rst => gfx10_ssrc_4.rst} (90%) rename llvm/docs/AMDGPU/{gfx10_wssrc.rst => gfx10_ssrc_5.rst} (89%) rename llvm/docs/AMDGPU/{gfx10_ssrc32_3.rst => gfx10_ssrc_6.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_ssrc32_4.rst => gfx10_ssrc_7.rst} (89%) rename llvm/docs/AMDGPU/{gfx10_ssrc32_5.rst => gfx10_ssrc_8.rst} (92%) rename llvm/docs/AMDGPU/{gfx7_type_dev.rst => gfx10_type_deviation.rst} (69%) rename llvm/docs/AMDGPU/{gfx7_addr_ds.rst => gfx10_vaddr.rst} (87%) rename llvm/docs/AMDGPU/{gfx7_addr_flat.rst => gfx10_vaddr_1.rst} (86%) create mode 100644 llvm/docs/AMDGPU/gfx10_vaddr_2.rst rename llvm/docs/AMDGPU/{gfx10_vaddr_flat_scratch.rst => gfx10_vaddr_3.rst} (72%) rename llvm/docs/AMDGPU/{gfx10_addr_mimg.rst => gfx10_vaddr_4.rst} (94%) rename llvm/docs/AMDGPU/{gfx8_addr_buf.rst => gfx10_vaddr_5.rst} (94%) delete mode 100644 llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst rename llvm/docs/AMDGPU/{gfx10_vcc_32.rst => gfx10_vcc.rst} (89%) rename llvm/docs/AMDGPU/{gfx8_vdata32_0.rst => gfx10_vdata.rst} (86%) create mode 100644 llvm/docs/AMDGPU/gfx10_vdata0.rst create mode 100644 llvm/docs/AMDGPU/gfx10_vdata0_1.rst create mode 100644 llvm/docs/AMDGPU/gfx10_vdata1.rst create mode 100644 llvm/docs/AMDGPU/gfx10_vdata1_1.rst rename llvm/docs/AMDGPU/{gfx7_vdata64_0.rst => gfx10_vdata_1.rst} (86%) rename llvm/docs/AMDGPU/{gfx8_data_buf_atomic128.rst => gfx10_vdata_10.rst} (89%) rename llvm/docs/AMDGPU/{gfx8_vdata128_0.rst => gfx10_vdata_2.rst} (86%) rename llvm/docs/AMDGPU/{gfx7_vdata96_0.rst => gfx10_vdata_3.rst} (86%) rename llvm/docs/AMDGPU/{gfx8_data_mimg_atomic_reg.rst => gfx10_vdata_4.rst} (93%) rename llvm/docs/AMDGPU/{gfx8_data_mimg_atomic_cmp.rst => gfx10_vdata_5.rst} (93%) rename llvm/docs/AMDGPU/{gfx10_data_mimg_store_d16.rst => gfx10_vdata_6.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_data_mimg_store.rst => gfx10_vdata_7.rst} (88%) rename llvm/docs/AMDGPU/{gfx7_data_buf_atomic32.rst => gfx10_vdata_8.rst} (89%) rename llvm/docs/AMDGPU/{gfx8_data_buf_atomic64.rst => gfx10_vdata_9.rst} (89%) rename llvm/docs/AMDGPU/{gfx8_vdst32_0.rst => gfx10_vdst.rst} (86%) rename llvm/docs/AMDGPU/{gfx8_vdst64_0.rst => gfx10_vdst_1.rst} (86%) rename llvm/docs/AMDGPU/{gfx7_dst_buf_64.rst => gfx10_vdst_10.rst} (88%) rename llvm/docs/AMDGPU/{gfx8_dst_buf_96.rst => gfx10_vdst_11.rst} (88%) rename llvm/docs/AMDGPU/{gfx7_dst_buf_128.rst => gfx10_vdst_12.rst} (88%) rename llvm/docs/AMDGPU/{gfx8_dst_buf_lds.rst => gfx10_vdst_13.rst} (92%) rename llvm/docs/AMDGPU/{gfx8_vdst128_0.rst => gfx10_vdst_2.rst} (86%) rename llvm/docs/AMDGPU/{gfx7_vdst96_0.rst => gfx10_vdst_3.rst} (86%) rename llvm/docs/AMDGPU/{gfx8_dst_flat_atomic32.rst => gfx10_vdst_4.rst} (88%) rename llvm/docs/AMDGPU/{gfx7_dst_flat_atomic64.rst => gfx10_vdst_5.rst} (88%) rename llvm/docs/AMDGPU/{gfx10_dst_mimg_gather4.rst => gfx10_vdst_6.rst} (92%) rename llvm/docs/AMDGPU/{gfx7_dst_mimg_regular.rst => gfx10_vdst_7.rst} (90%) rename llvm/docs/AMDGPU/{gfx10_dst_mimg_regular_d16.rst => gfx10_vdst_8.rst} (92%) rename llvm/docs/AMDGPU/{gfx7_dst_buf_32.rst => gfx10_vdst_9.rst} (88%) rename llvm/docs/AMDGPU/{gfx7_vsrc32_0.rst => gfx10_vsrc.rst} (86%) rename llvm/docs/AMDGPU/{gfx8_src_exp.rst => gfx10_vsrc_1.rst} (94%) rename llvm/docs/AMDGPU/{gfx7_vsrc128_0.rst => gfx10_vsrc_2.rst} (86%) rename llvm/docs/AMDGPU/{gfx8_vsrc64_0.rst => gfx10_vsrc_3.rst} (86%) rename llvm/docs/AMDGPU/{gfx8_ret.rst => gfx7_dst.rst} (88%) rename llvm/docs/AMDGPU/{gfx8_simm16.rst => gfx7_imm16.rst} (89%) rename llvm/docs/AMDGPU/{gfx7_uimm16.rst => gfx7_imm16_1.rst} (89%) rename llvm/docs/AMDGPU/{gfx7_bimm16.rst => gfx7_imm16_2.rst} (89%) rename llvm/docs/AMDGPU/{gfx8_mod_vop3_abs_neg.rst => gfx7_m.rst} (86%) rename llvm/docs/AMDGPU/{gfx8_base_smem_buf.rst => gfx7_sbase.rst} (88%) rename llvm/docs/AMDGPU/{gfx7_base_smem_addr.rst => gfx7_sbase_1.rst} (89%) rename llvm/docs/AMDGPU/{gfx7_sdst32_0.rst => gfx7_sdst.rst} (89%) rename llvm/docs/AMDGPU/{gfx7_sdst512_0.rst => gfx7_sdst_1.rst} (86%) rename llvm/docs/AMDGPU/{gfx7_sdst64_0.rst => gfx7_sdst_2.rst} (89%) rename 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gfx7_ssrc_4.rst} (89%) rename llvm/docs/AMDGPU/{gfx7_ssrc32_3.rst => gfx7_ssrc_5.rst} (92%) rename llvm/docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx7_ssrc_6.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_ssrc64_3.rst => gfx7_ssrc_7.rst} (90%) rename llvm/docs/AMDGPU/{gfx7_ssrc32_4.rst => gfx7_ssrc_8.rst} (90%) rename llvm/docs/AMDGPU/{gfx7_ssrc32_5.rst => gfx7_ssrc_9.rst} (90%) rename llvm/docs/AMDGPU/{gfx8_type_dev.rst => gfx7_type_deviation.rst} (69%) rename llvm/docs/AMDGPU/{gfx8_addr_ds.rst => gfx7_vaddr.rst} (87%) rename llvm/docs/AMDGPU/{gfx8_addr_flat.rst => gfx7_vaddr_1.rst} (86%) rename llvm/docs/AMDGPU/{gfx7_addr_mimg.rst => gfx7_vaddr_2.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_addr_buf.rst => gfx7_vaddr_3.rst} (95%) rename llvm/docs/AMDGPU/{gfx7_vcc_64.rst => gfx7_vcc.rst} (87%) rename llvm/docs/AMDGPU/{gfx7_vdata32_0.rst => gfx7_vdata.rst} (86%) create mode 100644 llvm/docs/AMDGPU/gfx7_vdata0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vdata0_1.rst create mode 100644 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llvm/docs/AMDGPU/{gfx8_dst_buf_128.rst => gfx7_vdst_11.rst} (88%) rename llvm/docs/AMDGPU/{gfx7_dst_buf_lds.rst => gfx7_vdst_12.rst} (92%) rename llvm/docs/AMDGPU/{gfx7_vdst128_0.rst => gfx7_vdst_2.rst} (86%) rename llvm/docs/AMDGPU/{gfx8_vdst96_0.rst => gfx7_vdst_3.rst} (86%) rename llvm/docs/AMDGPU/{gfx7_dst_flat_atomic32.rst => gfx7_vdst_4.rst} (88%) rename llvm/docs/AMDGPU/{gfx8_dst_flat_atomic64.rst => gfx7_vdst_5.rst} (88%) rename llvm/docs/AMDGPU/{gfx7_dst_mimg_gather4.rst => gfx7_vdst_6.rst} (88%) rename llvm/docs/AMDGPU/{gfx8_dst_mimg_regular.rst => gfx7_vdst_7.rst} (90%) rename llvm/docs/AMDGPU/{gfx8_dst_buf_32.rst => gfx7_vdst_8.rst} (88%) rename llvm/docs/AMDGPU/{gfx8_dst_buf_64.rst => gfx7_vdst_9.rst} (88%) rename llvm/docs/AMDGPU/{gfx7_src_exp.rst => gfx7_vsrc.rst} (94%) rename llvm/docs/AMDGPU/{gfx10_vsrc32_0.rst => gfx7_vsrc_1.rst} (86%) rename llvm/docs/AMDGPU/{gfx8_vsrc128_0.rst => gfx7_vsrc_2.rst} (86%) rename llvm/docs/AMDGPU/{gfx7_vsrc64_0.rst => gfx7_vsrc_3.rst} (86%) rename llvm/docs/AMDGPU/{gfx10_ret.rst => gfx8_dst.rst} (88%) rename llvm/docs/AMDGPU/{gfx10_simm16.rst => gfx8_imm16.rst} (89%) rename llvm/docs/AMDGPU/{gfx10_uimm16.rst => gfx8_imm16_1.rst} (89%) rename llvm/docs/AMDGPU/{gfx10_bimm16.rst => gfx8_imm16_2.rst} (89%) rename llvm/docs/AMDGPU/{gfx10_mod_sdwa_sext.rst => gfx8_m.rst} (85%) rename llvm/docs/AMDGPU/{gfx10_mod_vop3_abs_neg.rst => gfx8_m_1.rst} (86%) delete mode 100644 llvm/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst rename llvm/docs/AMDGPU/{gfx10_perm_smem.rst => gfx8_probe.rst} (93%) rename llvm/docs/AMDGPU/{gfx8_base_smem_addr.rst => gfx8_sbase.rst} (70%) rename llvm/docs/AMDGPU/{gfx10_base_smem_buf.rst => gfx8_sbase_1.rst} (88%) rename llvm/docs/AMDGPU/{gfx8_sdata32_0.rst => gfx8_sdata.rst} (69%) rename llvm/docs/AMDGPU/{gfx8_sdata64_0.rst => gfx8_sdata_1.rst} (69%) rename llvm/docs/AMDGPU/{gfx10_sdata128_0.rst => gfx8_sdata_2.rst} (87%) rename llvm/docs/AMDGPU/{gfx8_sdst32_0.rst => gfx8_sdst.rst} (69%) delete mode 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gfx8_src_7.rst} (59%) create mode 100644 llvm/docs/AMDGPU/gfx8_src_8.rst create mode 100644 llvm/docs/AMDGPU/gfx8_src_9.rst rename llvm/docs/AMDGPU/{gfx10_rsrc_mimg.rst => gfx8_srsrc.rst} (90%) rename llvm/docs/AMDGPU/{gfx10_rsrc_buf.rst => gfx8_srsrc_1.rst} (89%) rename llvm/docs/AMDGPU/{gfx10_samp_mimg.rst => gfx8_ssamp.rst} (89%) create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc.rst delete mode 100644 llvm/docs/AMDGPU/gfx8_ssrc32_0.rst delete mode 100644 llvm/docs/AMDGPU/gfx8_ssrc32_2.rst delete mode 100644 llvm/docs/AMDGPU/gfx8_ssrc32_3.rst delete mode 100644 llvm/docs/AMDGPU/gfx8_ssrc32_4.rst delete mode 100644 llvm/docs/AMDGPU/gfx8_ssrc64_3.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc_1.rst rename llvm/docs/AMDGPU/{gfx8_ssrc32_1.rst => gfx8_ssrc_2.rst} (69%) rename llvm/docs/AMDGPU/{gfx8_ssrc64_1.rst => gfx8_ssrc_3.rst} (69%) create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc_4.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc_5.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc_6.rst 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llvm/docs/AMDGPU/{gfx8_data_buf_d16_128.rst => gfx8_vdata_11.rst} (89%) rename llvm/docs/AMDGPU/{gfx10_data_buf_atomic32.rst => gfx8_vdata_12.rst} (89%) rename llvm/docs/AMDGPU/{gfx10_data_buf_atomic64.rst => gfx8_vdata_13.rst} (89%) rename llvm/docs/AMDGPU/{gfx10_data_buf_atomic128.rst => gfx8_vdata_14.rst} (89%) rename llvm/docs/AMDGPU/{gfx10_vdata128_0.rst => gfx8_vdata_2.rst} (86%) rename llvm/docs/AMDGPU/{gfx10_vdata96_0.rst => gfx8_vdata_3.rst} (86%) rename llvm/docs/AMDGPU/{gfx10_data_mimg_atomic_reg.rst => gfx8_vdata_4.rst} (93%) rename llvm/docs/AMDGPU/{gfx10_data_mimg_atomic_cmp.rst => gfx8_vdata_5.rst} (92%) rename llvm/docs/AMDGPU/{gfx8_data_mimg_store_d16.rst => gfx8_vdata_6.rst} (93%) rename llvm/docs/AMDGPU/{gfx10_data_mimg_store.rst => gfx8_vdata_7.rst} (88%) rename llvm/docs/AMDGPU/{gfx8_data_buf_d16_32.rst => gfx8_vdata_8.rst} (86%) rename llvm/docs/AMDGPU/{gfx8_data_buf_d16_64.rst => gfx8_vdata_9.rst} (89%) rename llvm/docs/AMDGPU/{gfx900_vdst32_0.rst => gfx8_vdst.rst} (86%) rename llvm/docs/AMDGPU/{gfx10_vdst64_0.rst => gfx8_vdst_1.rst} (86%) rename llvm/docs/AMDGPU/{gfx8_dst_buf_d16_64.rst => gfx8_vdst_10.rst} (91%) rename llvm/docs/AMDGPU/{gfx8_dst_buf_d16_96.rst => gfx8_vdst_11.rst} (91%) rename llvm/docs/AMDGPU/{gfx8_dst_buf_d16_128.rst => gfx8_vdst_12.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_dst_buf_32.rst => gfx8_vdst_13.rst} (88%) rename llvm/docs/AMDGPU/{gfx10_dst_buf_64.rst => gfx8_vdst_14.rst} (88%) rename llvm/docs/AMDGPU/{gfx10_dst_buf_96.rst => gfx8_vdst_15.rst} (88%) rename llvm/docs/AMDGPU/{gfx10_dst_buf_128.rst => gfx8_vdst_16.rst} (88%) rename llvm/docs/AMDGPU/{gfx10_dst_buf_lds.rst => gfx8_vdst_17.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_vdst128_0.rst => gfx8_vdst_2.rst} (86%) rename llvm/docs/AMDGPU/{gfx10_vdst96_0.rst => gfx8_vdst_3.rst} (86%) rename llvm/docs/AMDGPU/{gfx10_dst_flat_atomic32.rst => gfx8_vdst_4.rst} (88%) rename llvm/docs/AMDGPU/{gfx10_dst_flat_atomic64.rst => gfx8_vdst_5.rst} (88%) rename llvm/docs/AMDGPU/{gfx8_dst_mimg_gather4.rst => gfx8_vdst_6.rst} (94%) rename llvm/docs/AMDGPU/{gfx10_dst_mimg_regular.rst => gfx8_vdst_7.rst} (90%) rename llvm/docs/AMDGPU/{gfx8_dst_mimg_regular_d16.rst => gfx8_vdst_8.rst} (94%) rename llvm/docs/AMDGPU/{gfx8_dst_buf_d16_32.rst => gfx8_vdst_9.rst} (88%) rename llvm/docs/AMDGPU/{gfx10_src_exp.rst => gfx8_vsrc.rst} (93%) rename llvm/docs/AMDGPU/{gfx906_vsrc32_0.rst => gfx8_vsrc_1.rst} (86%) rename llvm/docs/AMDGPU/{gfx10_vsrc128_0.rst => gfx8_vsrc_2.rst} (86%) rename llvm/docs/AMDGPU/{gfx10_vsrc64_0.rst => gfx8_vsrc_3.rst} (86%) rename llvm/docs/AMDGPU/{gfx900_mad_type_dev.rst => gfx900_fx_operand.rst} (89%) rename llvm/docs/AMDGPU/{gfx900_mod_vop3_abs_neg.rst => gfx900_m.rst} (86%) create mode 100644 llvm/docs/AMDGPU/gfx900_src.rst delete mode 100644 llvm/docs/AMDGPU/gfx900_src32_0.rst delete mode 100644 llvm/docs/AMDGPU/gfx900_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx900_src_1.rst create mode 100644 llvm/docs/AMDGPU/gfx900_vdst.rst rename llvm/docs/AMDGPU/{gfx904_mad_type_dev.rst => gfx904_fx_operand.rst} (89%) create mode 100644 llvm/docs/AMDGPU/gfx904_m.rst delete mode 100644 llvm/docs/AMDGPU/gfx904_mod_vop3_abs_neg.rst create mode 100644 llvm/docs/AMDGPU/gfx904_src.rst delete mode 100644 llvm/docs/AMDGPU/gfx904_src32_0.rst delete mode 100644 llvm/docs/AMDGPU/gfx904_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx904_src_1.rst create mode 100644 llvm/docs/AMDGPU/gfx904_vdst.rst delete mode 100644 llvm/docs/AMDGPU/gfx904_vdst32_0.rst rename llvm/docs/AMDGPU/{gfx906_mad_type_dev.rst => gfx906_fx_operand.rst} (89%) create mode 100644 llvm/docs/AMDGPU/gfx906_m.rst rename llvm/docs/AMDGPU/{gfx906_mod_sdwa_sext.rst => gfx906_m_1.rst} (85%) delete mode 100644 llvm/docs/AMDGPU/gfx906_mod_dpp_sdwa_abs_neg.rst delete mode 100644 llvm/docs/AMDGPU/gfx906_mod_vop3_abs_neg.rst create mode 100644 llvm/docs/AMDGPU/gfx906_src.rst delete mode 100644 llvm/docs/AMDGPU/gfx906_src32_0.rst delete mode 100644 llvm/docs/AMDGPU/gfx906_src32_1.rst delete mode 100644 llvm/docs/AMDGPU/gfx906_src32_2.rst delete mode 100644 llvm/docs/AMDGPU/gfx906_src32_3.rst delete mode 100644 llvm/docs/AMDGPU/gfx906_src32_4.rst create mode 100644 llvm/docs/AMDGPU/gfx906_src_1.rst create mode 100644 llvm/docs/AMDGPU/gfx906_src_2.rst create mode 100644 llvm/docs/AMDGPU/gfx906_src_3.rst create mode 100644 llvm/docs/AMDGPU/gfx906_src_4.rst create mode 100644 llvm/docs/AMDGPU/gfx906_type_deviation.rst create mode 100644 llvm/docs/AMDGPU/gfx906_vdst.rst delete mode 100644 llvm/docs/AMDGPU/gfx906_vdst32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx906_vsrc.rst rename llvm/docs/AMDGPU/{gfx908_ret.rst => gfx908_dst.rst} (88%) create mode 100644 llvm/docs/AMDGPU/gfx908_fx_operand.rst create mode 100644 llvm/docs/AMDGPU/gfx908_m.rst rename llvm/docs/AMDGPU/{gfx908_mod_sdwa_sext.rst => gfx908_m_1.rst} (85%) delete mode 100644 llvm/docs/AMDGPU/gfx908_mad_type_dev.rst delete mode 100644 llvm/docs/AMDGPU/gfx908_mod_dpp_sdwa_abs_neg.rst delete mode 100644 llvm/docs/AMDGPU/gfx908_mod_vop3_abs_neg.rst rename llvm/docs/AMDGPU/{gfx908_saddr_flat_global.rst => gfx908_saddr.rst} (57%) rename llvm/docs/AMDGPU/{gfx908_offset_buf.rst => gfx908_soffset.rst} (51%) create mode 100644 llvm/docs/AMDGPU/gfx908_src.rst delete mode 100644 llvm/docs/AMDGPU/gfx908_src32_0.rst delete mode 100644 llvm/docs/AMDGPU/gfx908_src32_1.rst delete mode 100644 llvm/docs/AMDGPU/gfx908_src32_2.rst delete mode 100644 llvm/docs/AMDGPU/gfx908_src32_4.rst delete mode 100644 llvm/docs/AMDGPU/gfx908_src32_5.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src_1.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src_2.rst rename llvm/docs/AMDGPU/{gfx908_src32_3.rst => gfx908_src_3.rst} (69%) create mode 100644 llvm/docs/AMDGPU/gfx908_src_4.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src_5.rst rename llvm/docs/AMDGPU/{gfx908_rsrc_buf.rst => gfx908_srsrc.rst} (89%) delete mode 100644 llvm/docs/AMDGPU/gfx908_type_dev.rst create mode 100644 llvm/docs/AMDGPU/gfx908_type_deviation.rst create mode 100644 llvm/docs/AMDGPU/gfx908_vaddr.rst rename llvm/docs/AMDGPU/{gfx908_addr_buf.rst => gfx908_vaddr_1.rst} (94%) delete mode 100644 llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst rename llvm/docs/AMDGPU/{gfx908_vdata32_0.rst => gfx908_vdata.rst} (85%) rename llvm/docs/AMDGPU/{gfx908_data_buf_atomic32.rst => gfx908_vdata_1.rst} (89%) rename llvm/docs/AMDGPU/{gfx908_dst_flat_atomic32.rst => gfx908_vdst.rst} (88%) delete mode 100644 llvm/docs/AMDGPU/gfx908_vdst32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx908_vdst_1.rst rename llvm/docs/AMDGPU/{gfx908_adst32_0.rst => gfx908_vdst_2.rst} (85%) rename llvm/docs/AMDGPU/{gfx908_adst128_0.rst => gfx908_vdst_3.rst} (84%) rename llvm/docs/AMDGPU/{gfx908_adst512_0.rst => gfx908_vdst_4.rst} (84%) rename llvm/docs/AMDGPU/{gfx908_adst1024_0.rst => gfx908_vdst_5.rst} (84%) create mode 100644 llvm/docs/AMDGPU/gfx908_vsrc.rst delete mode 100644 llvm/docs/AMDGPU/gfx908_vsrc32_0.rst rename llvm/docs/AMDGPU/{gfx908_asrc32_0.rst => gfx908_vsrc_1.rst} (84%) rename llvm/docs/AMDGPU/{gfx908_vasrc64_0.rst => gfx908_vsrc_2.rst} (85%) rename llvm/docs/AMDGPU/{gfx908_asrc128_0.rst => gfx908_vsrc_3.rst} (84%) rename llvm/docs/AMDGPU/{gfx908_vasrc32_0.rst => gfx908_vsrc_4.rst} (85%) rename llvm/docs/AMDGPU/{gfx908_asrc512_0.rst => gfx908_vsrc_5.rst} (84%) rename llvm/docs/AMDGPU/{gfx908_asrc1024_0.rst => gfx908_vsrc_6.rst} (84%) diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst index 1698bca952d5..10b9fba12862 100644 --- a/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst @@ -36,212 +36,212 @@ DPP16 .. parsed-literal:: - **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_add_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_add_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_add_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_and_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_ashrrev_i32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_bfrev_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_ceil_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_ceil_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cndmask_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cos_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cos_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f16_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f16_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f16_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f32_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f32_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f32_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f32_ubyte0_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f32_ubyte1_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f32_ubyte2_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f32_ubyte3_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_flr_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_norm_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_norm_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_off_f32_i4_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_rpi_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_u32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_exp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_exp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_ffbh_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_ffbh_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_ffbl_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_floor_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_floor_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_fmac_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_fmac_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_fract_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_fract_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_frexp_exp_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_frexp_exp_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_frexp_mant_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_frexp_mant_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_ldexp_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`i16` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_log_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_log_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_lshlrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_lshrrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mac_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_max_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_max_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_max_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_max_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_min_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_min_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_min_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_min_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mov_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_movreld_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_movrels_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_movrelsd_2_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_movrelsd_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mul_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mul_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mul_hi_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mul_hi_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mul_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mul_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mul_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_not_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_or_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_rcp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_rcp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_rcp_iflag_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_rndne_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_rndne_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_rsq_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_rsq_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sat_pk_u8_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sin_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sin_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sqrt_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sqrt_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sub_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sub_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sub_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sub_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_subrev_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_subrev_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_subrev_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_subrev_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_trunc_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_trunc_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_xnor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_xor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_add_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_and_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ashrrev_i32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_bfrev_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ceil_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ceil_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cndmask_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cos_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cos_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f16_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f16_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f16_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_ubyte0_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_ubyte1_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_ubyte2_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_ubyte3_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_flr_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_norm_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_norm_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_off_f32_i4_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_rpi_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_u32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_exp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_exp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ffbh_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ffbh_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ffbl_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_floor_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_floor_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fmac_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fmac_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fract_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fract_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_frexp_exp_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_frexp_exp_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_frexp_mant_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_frexp_mant_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ldexp_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`i16` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_log_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_log_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_lshlrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_lshrrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mac_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mov_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_movreld_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_movrels_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_movrelsd_2_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_movrelsd_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_hi_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_hi_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_not_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_or_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rcp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rcp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rcp_iflag_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rndne_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rndne_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rsq_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rsq_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sat_pk_u8_i16_dpp :ref:`vdst`::ref:`u8x4`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sin_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sin_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sqrt_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sqrt_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_subrev_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_subrev_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_subrev_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_subrev_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_trunc_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_trunc_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_xnor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_xor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` DPP8 ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** + **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` - v_add_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_add_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_add_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_and_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_ashrrev_i32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_bfrev_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_ceil_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_ceil_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cndmask_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` - v_cos_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cos_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f16_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f16_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f16_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f32_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f32_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f32_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f32_ubyte0_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f32_ubyte1_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f32_ubyte2_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f32_ubyte3_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_flr_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_i16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_norm_i16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_norm_u16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_off_f32_i4_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_rpi_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_u16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_u32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_exp_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_exp_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_ffbh_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_ffbh_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_ffbl_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_floor_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_floor_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_fmac_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_fmac_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_fract_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_fract_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_frexp_exp_i16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_frexp_exp_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_frexp_mant_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_frexp_mant_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_ldexp_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`::ref:`i16` :ref:`dpp8_sel` :ref:`fi` - v_log_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_log_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_lshlrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_lshrrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_mac_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_max_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_max_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_max_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_max_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_min_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_min_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_min_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_min_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_mov_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_movreld_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_movrels_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_movrelsd_2_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_movrelsd_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_mul_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_mul_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_mul_hi_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_mul_hi_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_mul_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_mul_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_mul_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_not_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_or_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_rcp_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_rcp_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_rcp_iflag_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_rndne_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_rndne_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_rsq_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_rsq_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_sat_pk_u8_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_sin_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_sin_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_sqrt_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_sqrt_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_sub_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` - v_sub_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_sub_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_sub_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_subrev_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` - v_subrev_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_subrev_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_subrev_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_trunc_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_trunc_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_xnor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_xor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_add_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` + v_add_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_add_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_add_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_and_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_ashrrev_i32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_bfrev_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ceil_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ceil_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cndmask_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` + v_cos_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cos_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f16_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f16_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f16_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_ubyte0_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_ubyte1_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_ubyte2_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_ubyte3_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_flr_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_i16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_norm_i16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_norm_u16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_off_f32_i4_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_rpi_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_u16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_u32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_exp_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_exp_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ffbh_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ffbh_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ffbl_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_floor_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_floor_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_fmac_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_fmac_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_fract_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_fract_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_frexp_exp_i16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_frexp_exp_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_frexp_mant_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_frexp_mant_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ldexp_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`::ref:`i16` :ref:`dpp8_sel` :ref:`fi` + v_log_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_log_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_lshlrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_lshrrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mac_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_max_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_max_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_max_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_max_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_min_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_min_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_min_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_min_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mov_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_movreld_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_movrels_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_movrelsd_2_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_movrelsd_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_mul_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_hi_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_hi_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_not_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_or_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_rcp_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rcp_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rcp_iflag_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rndne_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rndne_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rsq_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rsq_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sat_pk_u8_i16_dpp :ref:`vdst`::ref:`u8x4`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sin_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sin_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sqrt_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sqrt_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sub_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` + v_sub_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_sub_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_sub_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_subrev_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` + v_subrev_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_subrev_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_subrev_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_trunc_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_trunc_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_xnor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_xor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` DS ----------------------- @@ -249,161 +249,161 @@ DS .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - ds_add_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_src2_f32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_add_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_add_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_add_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_and_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_append :ref:`vdst` :ref:`offset16` :ref:`gds` - ds_bpermute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` - ds_cmpst_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_f32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_f64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_condxchg32_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_consume :ref:`vdst` :ref:`offset16` :ref:`gds` - ds_dec_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_dec_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_dec_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_dec_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_dec_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_dec_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_barrier :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_init :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_sema_br :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_sema_p :ref:`offset16` :ref:`gds` - ds_gws_sema_release_all :ref:`offset16` :ref:`gds` - ds_gws_sema_v :ref:`offset16` :ref:`gds` - ds_inc_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_inc_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_inc_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_inc_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_inc_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_inc_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_src2_f32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_f64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_i32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_i64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_src2_f32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_f64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_i32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_i64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_mskor_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_mskor_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_mskor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_mskor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + ds_add_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_add_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_add_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_add_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_and_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_append :ref:`vdst` :ref:`offset` :ref:`gds` + ds_bpermute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` + ds_cmpst_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_f32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_f64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_condxchg32_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_consume :ref:`vdst` :ref:`offset` :ref:`gds` + ds_dec_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_dec_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_dec_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_barrier :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_init :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_sema_br :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_sema_p :ref:`offset` :ref:`gds` + ds_gws_sema_release_all :ref:`offset` :ref:`gds` + ds_gws_sema_v :ref:`offset` :ref:`gds` + ds_inc_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_inc_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_inc_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_f64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_i32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_i64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_f64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_i32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_i64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_mskor_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` ds_nop - ds_or_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_or_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_ordered_count :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_permute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` - ds_read2_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read2_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read2st64_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read2st64_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read_addtid_b32 :ref:`vdst` :ref:`offset16` :ref:`gds` - ds_read_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_i8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_i8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u16_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u16_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_rsub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_rsub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_rsub_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_rsub_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_rsub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_rsub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_sub_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_sub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_swizzle_b32 :ref:`vdst`, :ref:`vaddr` :ref:`pattern` :ref:`gds` - ds_wrap_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_write2_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write2_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write2st64_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write2st64_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write_addtid_b32 :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b16_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b8_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_write_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_wrxchg2_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg2_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg2st64_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg2st64_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_wrxchg_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_xor_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds` + ds_or_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_or_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_ordered_count :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_permute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` + ds_read2_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2st64_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2st64_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read_addtid_b32 :ref:`vdst` :ref:`offset` :ref:`gds` + ds_read_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_sub_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_sub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_swizzle_b32 :ref:`vdst`, :ref:`vaddr` :ref:`pattern` :ref:`gds` + ds_wrap_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_write2_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2st64_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2st64_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write_addtid_b32 :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b16_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b8_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_write_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_wrxchg2_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2st64_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2st64_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_wrxchg_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_xor_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` EXP ----------------------- @@ -411,588 +411,591 @@ EXP .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - exp :ref:`tgt`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vsrc2`, :ref:`vsrc3` :ref:`done` :ref:`compr` :ref:`vm` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + exp :ref:`tgt`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vsrc2`, :ref:`vsrc3` :ref:`done` :ref:`compr` :ref:`vm` FLAT ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - flat_atomic_add :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_add_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_and :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_and_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_cmpswap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_cmpswap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_dec :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_dec_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_fcmpswap :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32x2` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_fcmpswap_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64x2` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_fmax :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_fmax_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_fmin :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_fmin_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_inc :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_inc_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_or :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_or_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_smax :ref:`vdst`::ref:`opt`::ref:`s32`, :ref:`vaddr`, :ref:`vdata`::ref:`s32` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_smax_x2 :ref:`vdst`::ref:`opt`::ref:`s64`, :ref:`vaddr`, :ref:`vdata`::ref:`s64` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_smin :ref:`vdst`::ref:`opt`::ref:`s32`, :ref:`vaddr`, :ref:`vdata`::ref:`s32` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_smin_x2 :ref:`vdst`::ref:`opt`::ref:`s64`, :ref:`vaddr`, :ref:`vdata`::ref:`s64` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_sub :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_sub_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_swap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_swap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_umax :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_umax_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_umin :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_umin_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_xor :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_xor_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_load_dword :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_dwordx2 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_dwordx3 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_dwordx4 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_sbyte :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_sbyte_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_sbyte_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_short_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_short_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_sshort :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_ubyte :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_ubyte_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_ubyte_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_ushort :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_store_byte :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_store_byte_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_store_dword :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_store_dwordx2 :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_store_dwordx3 :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_store_dwordx4 :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_store_short :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_store_short_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - global_atomic_add :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_add_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_and :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_and_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_cmpswap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_cmpswap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_dec :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_dec_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_fmax :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_fmax_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_fmin :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_fmin_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_inc :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_inc_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_or :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_or_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_smax :ref:`vdst`::ref:`opt`::ref:`s32`, :ref:`vaddr`, :ref:`vdata`::ref:`s32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_smax_x2 :ref:`vdst`::ref:`opt`::ref:`s64`, :ref:`vaddr`, :ref:`vdata`::ref:`s64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_smin :ref:`vdst`::ref:`opt`::ref:`s32`, :ref:`vaddr`, :ref:`vdata`::ref:`s32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_smin_x2 :ref:`vdst`::ref:`opt`::ref:`s64`, :ref:`vaddr`, :ref:`vdata`::ref:`s64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_sub :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_sub_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_swap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_swap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_umax :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_umax_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_umin :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_umin_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_xor :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_xor_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_sbyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_sbyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_short_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_short_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_ubyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_ubyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_store_byte :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_store_byte_d16_hi :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_store_dword :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_store_dwordx2 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_store_dwordx3 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_store_dwordx4 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_store_short :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_store_short_d16_hi :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_sbyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_sbyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_short_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_short_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_ubyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_ubyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_store_byte :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_store_byte_d16_hi :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_store_dword :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_store_dwordx2 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_store_dwordx3 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_store_dwordx4 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_store_short :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_store_short_d16_hi :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + flat_atomic_add :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_add_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_and :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_and_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_cmpswap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_cmpswap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_dec :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_dec_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_fcmpswap :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32x2` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_fcmpswap_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64x2` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_fmax :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_fmax_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_fmin :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_fmin_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_inc :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_inc_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_or :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_or_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_smax :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_smax_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_smin :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_smin_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_sub :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_sub_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_swap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_swap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_umax :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_umax_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_umin :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_umin_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_xor :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_atomic_xor_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` + flat_load_dword :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_dwordx2 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_dwordx3 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_dwordx4 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_sbyte :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_sbyte_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_sbyte_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_short_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_short_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_sshort :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_ubyte :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_ubyte_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_ubyte_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_ushort :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_byte :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_byte_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_dword :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_dwordx2 :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_dwordx3 :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_dwordx4 :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_short :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_short_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_add :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_add_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_and :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_and_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_cmpswap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_cmpswap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_dec :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_dec_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_fmax :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_fmax_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_fmin :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_fmin_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_inc :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_inc_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_or :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_or_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_smax :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_smax_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_smin :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_smin_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_sub :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_sub_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_swap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_swap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_umax :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_umax_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_umin :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_umin_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_xor :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_atomic_xor_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` + global_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_sbyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_sbyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_short_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_short_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_ubyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_ubyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_byte :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_byte_d16_hi :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_dword :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_dwordx2 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_dwordx3 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_dwordx4 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_short :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_short_d16_hi :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_sbyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_sbyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_short_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_short_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_ubyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_ubyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_byte :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_byte_d16_hi :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_dword :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_dwordx2 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_dwordx3 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_dwordx4 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_short :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_short_d16_hi :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` MIMG ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - image_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` - image_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` - image_atomic_cmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` - image_atomic_dec :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` - image_atomic_inc :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` - image_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` - image_atomic_smax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` - image_atomic_smin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` - image_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` - image_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` - image_atomic_umax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` - image_atomic_umin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` - image_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` - image_gather4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_gather4_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_get_lod :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` - image_get_resinfo :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`a16` :ref:`tfe` :ref:`lwe` - image_load :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_load_mip :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_load_mip_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` - image_load_mip_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` - image_load_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` - image_load_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` - image_sample :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cd_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cd_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cd_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cd_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_d_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_d_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_d_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_d_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cd_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cd_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cd_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cd_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_d_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_d_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_d_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_d_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_store :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_store_mip :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`d16` - image_store_mip_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` - image_store_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`dlc` :ref:`glc` :ref:`slc` :ref:`lwe` + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + image_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_cmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_dec :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_fcmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_fmax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_fmin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_inc :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_smax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_smin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_umax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_umin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_gather4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lwe` :ref:`d16` + image_gather4_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lwe` :ref:`d16` + image_gather4_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lwe` :ref:`d16` + image_gather4_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lwe` :ref:`d16` + image_gather4_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_get_lod :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_get_resinfo :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_load :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_load_mip :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_load_mip_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_load_mip_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_load_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_load_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_sample :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cd_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cd_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cd_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cd_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cd_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cd_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cd_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cd_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_store :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_store_mip :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_store_mip_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_store_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` MTBUF ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - tbuffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - tbuffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - tbuffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - tbuffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - tbuffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - tbuffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - tbuffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - tbuffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - tbuffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + tbuffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` MUBUF ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - buffer_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_add_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_and_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_cmpswap :ref:`vdata`::ref:`dst`::ref:`b32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_cmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`b64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_dec :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_dec_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fcmpswap :ref:`vdata`::ref:`dst`::ref:`f32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fcmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`f64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fmax :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fmax_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fmin :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fmin_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_inc :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_inc_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_or_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smax :ref:`vdata`::ref:`dst`::ref:`s32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smax_x2 :ref:`vdata`::ref:`dst`::ref:`s64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smin :ref:`vdata`::ref:`dst`::ref:`s32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smin_x2 :ref:`vdata`::ref:`dst`::ref:`s64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_sub_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_swap_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umax :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umax_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umin :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umin_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_xor_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + buffer_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_add_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_and_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_cmpswap :ref:`vdata`::ref:`dst`::ref:`b32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_cmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`b64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_dec :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_dec_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fcmpswap :ref:`vdata`::ref:`dst`::ref:`f32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fcmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`f64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fmax :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fmax_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fmin :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fmin_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_inc :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_inc_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_or_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smax :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smax_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smin :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smin_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_sub_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_swap_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umax :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umax_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umin :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umin_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_xor_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` buffer_gl0_inv buffer_gl1_inv - buffer_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` :ref:`dlc` - buffer_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` :ref:`dlc` - buffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` :ref:`dlc` - buffer_load_sbyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_sbyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_short_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_short_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` :ref:`dlc` - buffer_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` :ref:`dlc` - buffer_load_ubyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_ubyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` :ref:`dlc` - buffer_store_byte :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_byte_d16_hi :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dword :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx2 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx3 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx4 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_short :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_short_d16_hi :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` + buffer_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` + buffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` + buffer_load_sbyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_sbyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_short_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_short_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` + buffer_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` + buffer_load_ubyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_ubyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` + buffer_store_byte :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_byte_d16_hi :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dword :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx2 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx3 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx4 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_short :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_short_d16_hi :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` SDWA ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add_co_ci_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_add_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_add_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_add_nc_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_and_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_ashrrev_i32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`u32`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_bfrev_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ceil_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ceil_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cmp_class_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_class_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_f_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_f_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_f_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_f_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lg_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lg_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ne_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ne_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ne_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ne_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_neq_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_neq_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nge_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nge_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ngt_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ngt_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nle_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nle_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nlg_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nlg_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nlt_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nlt_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_o_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_o_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_t_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_t_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_tru_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_tru_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_u_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_u_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_class_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_class_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_f_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_f_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_f_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_f_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lg_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lg_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ne_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ne_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ne_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ne_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_neq_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_neq_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nge_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nge_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ngt_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ngt_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nle_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nle_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nlg_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nlg_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nlt_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nlt_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_o_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_o_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_t_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_t_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_tru_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_tru_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_u_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_u_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cndmask_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`vcc` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_cos_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cos_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f16_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f16_i16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f16_u16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_i32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_u32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_ubyte0_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_ubyte1_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_ubyte2_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_ubyte3_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_flr_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_norm_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_norm_u16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_off_f32_i4_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_rpi_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_u16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_u32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_exp_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_exp_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ffbh_i32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ffbh_u32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ffbl_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_floor_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_floor_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_fract_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_fract_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_frexp_exp_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_frexp_exp_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_frexp_mant_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_frexp_mant_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ldexp_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`i16` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_log_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_log_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_lshlrev_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`u32`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_lshrrev_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`u32`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_max_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_max_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_max_i32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_max_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_min_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_min_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_min_i32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_min_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mov_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_movreld_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_movrels_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_movrelsd_2_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_movrelsd_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_mul_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_hi_i32_i24_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_hi_u32_u24_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_i32_i24_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_legacy_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_u32_u24_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_not_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_or_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_rcp_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rcp_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rcp_iflag_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rndne_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rndne_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rsq_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rsq_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sat_pk_u8_i16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sin_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sin_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sqrt_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sqrt_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sub_co_ci_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_sub_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_sub_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_sub_nc_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_subrev_co_ci_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_subrev_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_subrev_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_subrev_nc_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_trunc_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_trunc_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_xnor_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_xor_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_add_co_ci_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_add_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_add_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_add_nc_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_and_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_ashrrev_i32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`u32`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_bfrev_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ceil_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ceil_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cmp_class_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_class_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lg_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lg_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ne_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ne_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ne_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ne_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_neq_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_neq_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nge_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nge_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ngt_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ngt_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nle_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nle_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nlg_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nlg_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nlt_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nlt_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_o_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_o_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_t_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_t_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_tru_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_tru_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_u_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_u_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_class_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_class_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lg_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lg_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ne_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ne_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ne_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ne_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_neq_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_neq_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nge_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nge_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ngt_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ngt_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nle_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nle_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nlg_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nlg_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nlt_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nlt_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_o_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_o_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_t_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_t_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_tru_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_tru_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_u_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_u_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cndmask_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`vcc` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_cos_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cos_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f16_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f16_i16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f16_u16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_i32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_u32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte0_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte1_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte2_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte3_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_flr_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_norm_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_norm_u16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_off_f32_i4_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_rpi_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_u16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_u32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_exp_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_exp_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ffbh_i32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ffbh_u32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ffbl_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_floor_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_floor_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_fract_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_fract_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_exp_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_exp_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_mant_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_mant_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ldexp_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`i16` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_log_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_log_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_lshlrev_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`u32`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_lshrrev_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`u32`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_i32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_i32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mov_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_movreld_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_movrels_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_movrelsd_2_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_movrelsd_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_mul_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_hi_i32_i24_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_hi_u32_u24_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_i32_i24_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_legacy_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_u32_u24_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_not_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_or_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_rcp_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rcp_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rcp_iflag_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rndne_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rndne_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rsq_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rsq_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sat_pk_u8_i16_sdwa :ref:`vdst`::ref:`u8x4`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sin_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sin_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sqrt_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sqrt_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sub_co_ci_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_sub_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_sub_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_sub_nc_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_co_ci_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_nc_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_trunc_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_trunc_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_xnor_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_xor_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` SMEM ----------------------- @@ -1000,91 +1003,91 @@ SMEM .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_atc_probe :ref:`imm3`, :ref:`sbase`, :ref:`soffset` - s_atc_probe_buffer :ref:`imm3`, :ref:`sbase`, :ref:`soffset` - s_atomic_add :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_add_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_and :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_and_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_cmpswap :ref:`sdata`::ref:`dst`::ref:`b32x2`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_cmpswap_x2 :ref:`sdata`::ref:`dst`::ref:`b64x2`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_dec :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_dec_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_inc :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_inc_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_or :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_or_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_smax :ref:`sdata`::ref:`dst`::ref:`s32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_smax_x2 :ref:`sdata`::ref:`dst`::ref:`s64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_smin :ref:`sdata`::ref:`dst`::ref:`s32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_smin_x2 :ref:`sdata`::ref:`dst`::ref:`s64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_sub :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_sub_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_swap :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_swap_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_umax :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_umax_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_umin :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_umin_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_xor :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_xor_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_add :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_add_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_and :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_and_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_cmpswap :ref:`sdata`::ref:`dst`::ref:`b32x2`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_cmpswap_x2 :ref:`sdata`::ref:`dst`::ref:`b64x2`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_dec :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_dec_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_inc :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_inc_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_or :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_or_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_smax :ref:`sdata`::ref:`dst`::ref:`s32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_smax_x2 :ref:`sdata`::ref:`dst`::ref:`s64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_smin :ref:`sdata`::ref:`dst`::ref:`s32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_smin_x2 :ref:`sdata`::ref:`dst`::ref:`s64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_sub :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_sub_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_swap :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_swap_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_umax :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_umax_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_umin :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_umin_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_xor :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_xor_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_buffer_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_buffer_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_buffer_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_buffer_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_buffer_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_dcache_discard :ref:`sbase`, :ref:`soffset` - s_dcache_discard_x2 :ref:`sbase`, :ref:`soffset` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_atc_probe :ref:`probe`, :ref:`sbase`, :ref:`soffset` + s_atc_probe_buffer :ref:`probe`, :ref:`sbase`, :ref:`soffset` + s_atomic_add :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_add_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_and :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_and_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_cmpswap :ref:`sdata`::ref:`dst`::ref:`b32x2`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_cmpswap_x2 :ref:`sdata`::ref:`dst`::ref:`b64x2`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_dec :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_dec_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_inc :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_inc_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_or :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_or_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_smax :ref:`sdata`::ref:`dst`::ref:`i32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_smax_x2 :ref:`sdata`::ref:`dst`::ref:`i64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_smin :ref:`sdata`::ref:`dst`::ref:`i32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_smin_x2 :ref:`sdata`::ref:`dst`::ref:`i64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_sub :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_sub_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_swap :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_swap_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_umax :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_umax_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_umin :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_umin_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_xor :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_xor_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_add :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_add_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_and :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_and_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_cmpswap :ref:`sdata`::ref:`dst`::ref:`b32x2`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_cmpswap_x2 :ref:`sdata`::ref:`dst`::ref:`b64x2`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_dec :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_dec_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_inc :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_inc_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_or :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_or_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_smax :ref:`sdata`::ref:`dst`::ref:`i32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_smax_x2 :ref:`sdata`::ref:`dst`::ref:`i64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_smin :ref:`sdata`::ref:`dst`::ref:`i32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_smin_x2 :ref:`sdata`::ref:`dst`::ref:`i64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_sub :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_sub_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_swap :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_swap_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_umax :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_umax_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_umin :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_umin_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_xor :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_xor_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_buffer_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_buffer_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_buffer_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_buffer_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_buffer_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_dcache_discard :ref:`sbase`, :ref:`soffset` + s_dcache_discard_x2 :ref:`sbase`, :ref:`soffset` s_dcache_inv s_dcache_wb - s_get_waveid_in_workgroup :ref:`sdst` + s_get_waveid_in_workgroup :ref:`sdst` s_gl1_inv - s_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_memrealtime :ref:`sdst` - s_memtime :ref:`sdst` - s_scratch_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_scratch_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_scratch_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_scratch_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_scratch_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_scratch_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_memrealtime :ref:`sdst`::ref:`b64` + s_memtime :ref:`sdst`::ref:`b64` + s_scratch_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_scratch_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_scratch_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_scratch_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_scratch_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_scratch_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` SOP1 ----------------------- @@ -1092,131 +1095,131 @@ SOP1 .. parsed-literal:: **INSTRUCTION** **DST** **SRC** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_abs_i32 :ref:`sdst`, :ref:`ssrc` - s_and_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_and_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_andn1_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_andn1_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_andn1_wrexec_b32 :ref:`sdst`, :ref:`ssrc` - s_andn1_wrexec_b64 :ref:`sdst`, :ref:`ssrc` - s_andn2_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_andn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_andn2_wrexec_b32 :ref:`sdst`, :ref:`ssrc` - s_andn2_wrexec_b64 :ref:`sdst`, :ref:`ssrc` - s_bcnt0_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_bcnt0_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_bcnt1_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_bcnt1_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_bitreplicate_b64_b32 :ref:`sdst`, :ref:`ssrc` - s_bitset0_b32 :ref:`sdst`, :ref:`ssrc` - s_bitset0_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` - s_bitset1_b32 :ref:`sdst`, :ref:`ssrc` - s_bitset1_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` - s_brev_b32 :ref:`sdst`, :ref:`ssrc` - s_brev_b64 :ref:`sdst`, :ref:`ssrc` - s_cmov_b32 :ref:`sdst`, :ref:`ssrc` - s_cmov_b64 :ref:`sdst`, :ref:`ssrc` - s_ff0_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_ff0_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_ff1_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_ff1_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32_i64 :ref:`sdst`, :ref:`ssrc` - s_getpc_b64 :ref:`sdst` - s_mov_b32 :ref:`sdst`, :ref:`ssrc` - s_mov_b64 :ref:`sdst`, :ref:`ssrc` - s_movreld_b32 :ref:`sdst`, :ref:`ssrc` - s_movreld_b64 :ref:`sdst`, :ref:`ssrc` - s_movrels_b32 :ref:`sdst`, :ref:`ssrc` - s_movrels_b64 :ref:`sdst`, :ref:`ssrc` - s_movrelsd_2_b32 :ref:`sdst`, :ref:`ssrc` - s_nand_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_nand_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_nor_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_nor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_not_b32 :ref:`sdst`, :ref:`ssrc` - s_not_b64 :ref:`sdst`, :ref:`ssrc` - s_or_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_or_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_orn1_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_orn1_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_orn2_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_orn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_quadmask_b32 :ref:`sdst`, :ref:`ssrc` - s_quadmask_b64 :ref:`sdst`, :ref:`ssrc` - s_rfe_b64 :ref:`ssrc` - s_setpc_b64 :ref:`ssrc` - s_sext_i32_i16 :ref:`sdst`, :ref:`ssrc` - s_sext_i32_i8 :ref:`sdst`, :ref:`ssrc` - s_swappc_b64 :ref:`sdst`, :ref:`ssrc` - s_wqm_b32 :ref:`sdst`, :ref:`ssrc` - s_wqm_b64 :ref:`sdst`, :ref:`ssrc` - s_xnor_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_xnor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_xor_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_xor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_abs_i32 :ref:`sdst`, :ref:`ssrc` + s_and_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_and_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_andn1_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_andn1_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_andn1_wrexec_b32 :ref:`sdst`, :ref:`ssrc` + s_andn1_wrexec_b64 :ref:`sdst`, :ref:`ssrc` + s_andn2_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_andn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_andn2_wrexec_b32 :ref:`sdst`, :ref:`ssrc` + s_andn2_wrexec_b64 :ref:`sdst`, :ref:`ssrc` + s_bcnt0_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_bcnt0_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_bcnt1_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_bcnt1_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_bitreplicate_b64_b32 :ref:`sdst`, :ref:`ssrc` + s_bitset0_b32 :ref:`sdst`, :ref:`ssrc` + s_bitset0_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` + s_bitset1_b32 :ref:`sdst`, :ref:`ssrc` + s_bitset1_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` + s_brev_b32 :ref:`sdst`, :ref:`ssrc` + s_brev_b64 :ref:`sdst`, :ref:`ssrc` + s_cmov_b32 :ref:`sdst`, :ref:`ssrc` + s_cmov_b64 :ref:`sdst`, :ref:`ssrc` + s_ff0_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_ff0_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_ff1_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_ff1_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_i64 :ref:`sdst`, :ref:`ssrc` + s_getpc_b64 :ref:`sdst` + s_mov_b32 :ref:`sdst`, :ref:`ssrc` + s_mov_b64 :ref:`sdst`, :ref:`ssrc` + s_movreld_b32 :ref:`sdst`, :ref:`ssrc` + s_movreld_b64 :ref:`sdst`, :ref:`ssrc` + s_movrels_b32 :ref:`sdst`, :ref:`ssrc` + s_movrels_b64 :ref:`sdst`, :ref:`ssrc` + s_movrelsd_2_b32 :ref:`sdst`, :ref:`ssrc` + s_nand_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_nand_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_nor_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_nor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_not_b32 :ref:`sdst`, :ref:`ssrc` + s_not_b64 :ref:`sdst`, :ref:`ssrc` + s_or_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_or_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_orn1_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_orn1_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_orn2_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_orn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_quadmask_b32 :ref:`sdst`, :ref:`ssrc` + s_quadmask_b64 :ref:`sdst`, :ref:`ssrc` + s_rfe_b64 :ref:`ssrc` + s_setpc_b64 :ref:`ssrc` + s_sext_i32_i16 :ref:`sdst`, :ref:`ssrc` + s_sext_i32_i8 :ref:`sdst`, :ref:`ssrc` + s_swappc_b64 :ref:`sdst`, :ref:`ssrc` + s_wqm_b32 :ref:`sdst`, :ref:`ssrc` + s_wqm_b64 :ref:`sdst`, :ref:`ssrc` + s_xnor_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_xnor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_xor_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_xor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` SOP2 ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_absdiff_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_add_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_addc_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_and_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_and_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_andn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_andn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_ashr_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_ashr_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfe_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfe_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfe_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_bfe_u64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfm_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_bfm_b64 :ref:`sdst`, :ref:`ssrc0`::ref:`b32`, :ref:`ssrc1`::ref:`b32` - s_cselect_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_cselect_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_lshl1_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_lshl2_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_lshl3_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_lshl4_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_lshl_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_lshl_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_lshr_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_lshr_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_max_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_max_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_min_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_min_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_mul_hi_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_mul_hi_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_mul_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nand_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nand_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_or_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_or_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_orn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_orn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_pack_hh_b32_b16 :ref:`sdst`, :ref:`ssrc0`::ref:`b16x2`, :ref:`ssrc1`::ref:`b16x2` - s_pack_lh_b32_b16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`b16x2` - s_pack_ll_b32_b16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_sub_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_sub_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_subb_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xnor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xnor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + **INSTRUCTION** **DST** **SRC0** **SRC1** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_absdiff_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_add_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_addc_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_and_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_and_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_andn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_andn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_ashr_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_ashr_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_bfe_u64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfm_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_bfm_b64 :ref:`sdst`, :ref:`ssrc0`::ref:`b32`, :ref:`ssrc1`::ref:`b32` + s_cselect_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_cselect_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl1_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl2_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl3_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl4_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshl_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshr_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshr_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_max_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_max_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_min_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_min_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_mul_hi_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_mul_hi_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_mul_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nand_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nand_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_or_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_or_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_orn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_orn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_pack_hh_b32_b16 :ref:`sdst`, :ref:`ssrc0`::ref:`b32`, :ref:`ssrc1`::ref:`b32` + s_pack_lh_b32_b16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`b32` + s_pack_ll_b32_b16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_sub_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_sub_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_subb_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xnor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xnor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` SOPC ----------------------- @@ -1224,25 +1227,25 @@ SOPC .. parsed-literal:: **INSTRUCTION** **SRC0** **SRC1** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_bitcmp0_b32 :ref:`ssrc0`, :ref:`ssrc1` - s_bitcmp0_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bitcmp1_b32 :ref:`ssrc0`, :ref:`ssrc1` - s_bitcmp1_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_cmp_eq_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_eq_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_eq_u64 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_ge_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_ge_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_gt_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_gt_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_le_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_le_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lg_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lg_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lg_u64 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lt_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lt_u32 :ref:`ssrc0`, :ref:`ssrc1` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_bitcmp0_b32 :ref:`ssrc0`, :ref:`ssrc1` + s_bitcmp0_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bitcmp1_b32 :ref:`ssrc0`, :ref:`ssrc1` + s_bitcmp1_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_cmp_eq_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_eq_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_eq_u64 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_ge_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_ge_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_gt_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_gt_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_le_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_le_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lg_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lg_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lg_u64 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lt_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lt_u32 :ref:`ssrc0`, :ref:`ssrc1` SOPK ----------------------- @@ -1250,34 +1253,34 @@ SOPK .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_addk_i32 :ref:`sdst`, :ref:`imm16` - s_call_b64 :ref:`sdst`, :ref:`label` - s_cmovk_i32 :ref:`sdst`, :ref:`imm16` - s_cmpk_eq_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_eq_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_ge_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_ge_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_gt_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_gt_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_le_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_le_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lg_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lg_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lt_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lt_u32 :ref:`ssrc`, :ref:`imm16` - s_getreg_b32 :ref:`sdst`, :ref:`hwreg` - s_movk_i32 :ref:`sdst`, :ref:`imm16` - s_mulk_i32 :ref:`sdst`, :ref:`imm16` - s_setreg_b32 :ref:`hwreg`, :ref:`ssrc` - s_setreg_imm32_b32 :ref:`hwreg`, :ref:`imm32` - s_subvector_loop_begin :ref:`sdst`, :ref:`label` - s_subvector_loop_end :ref:`sdst`, :ref:`label` - s_version :ref:`imm16` - s_waitcnt_expcnt :ref:`ssrc`, :ref:`imm16` - s_waitcnt_lgkmcnt :ref:`ssrc`, :ref:`imm16` - s_waitcnt_vmcnt :ref:`ssrc`, :ref:`imm16` - s_waitcnt_vscnt :ref:`ssrc`, :ref:`imm16` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_addk_i32 :ref:`sdst`, :ref:`imm16` + s_call_b64 :ref:`sdst`, :ref:`label` + s_cmovk_i32 :ref:`sdst`, :ref:`imm16` + s_cmpk_eq_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_eq_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_ge_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_ge_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_gt_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_gt_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_le_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_le_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lg_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lg_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lt_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lt_u32 :ref:`ssrc`, :ref:`imm16` + s_getreg_b32 :ref:`sdst`, :ref:`hwreg` + s_movk_i32 :ref:`sdst`, :ref:`imm16` + s_mulk_i32 :ref:`sdst`, :ref:`imm16` + s_setreg_b32 :ref:`hwreg`, :ref:`ssrc` + s_setreg_imm32_b32 :ref:`hwreg`, :ref:`simm32` + s_subvector_loop_begin :ref:`sdst`, :ref:`label` + s_subvector_loop_end :ref:`sdst`, :ref:`label` + s_version :ref:`imm16` + s_waitcnt_expcnt :ref:`ssrc`, :ref:`imm16` + s_waitcnt_lgkmcnt :ref:`ssrc`, :ref:`imm16` + s_waitcnt_vmcnt :ref:`ssrc`, :ref:`imm16` + s_waitcnt_vscnt :ref:`ssrc`, :ref:`imm16` SOPP ----------------------- @@ -1285,41 +1288,41 @@ SOPP .. parsed-literal:: **INSTRUCTION** **SRC** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| s_barrier - s_branch :ref:`label` - s_cbranch_cdbgsys :ref:`label` - s_cbranch_cdbgsys_and_user :ref:`label` - s_cbranch_cdbgsys_or_user :ref:`label` - s_cbranch_cdbguser :ref:`label` - s_cbranch_execnz :ref:`label` - s_cbranch_execz :ref:`label` - s_cbranch_scc0 :ref:`label` - s_cbranch_scc1 :ref:`label` - s_cbranch_vccnz :ref:`label` - s_cbranch_vccz :ref:`label` - s_clause :ref:`imm16` + s_branch :ref:`label` + s_cbranch_cdbgsys :ref:`label` + s_cbranch_cdbgsys_and_user :ref:`label` + s_cbranch_cdbgsys_or_user :ref:`label` + s_cbranch_cdbguser :ref:`label` + s_cbranch_execnz :ref:`label` + s_cbranch_execz :ref:`label` + s_cbranch_scc0 :ref:`label` + s_cbranch_scc1 :ref:`label` + s_cbranch_vccnz :ref:`label` + s_cbranch_vccz :ref:`label` + s_clause :ref:`imm16` s_code_end - s_decperflevel :ref:`imm16` - s_denorm_mode :ref:`imm16` + s_decperflevel :ref:`imm16` + s_denorm_mode :ref:`imm16` s_endpgm s_endpgm_ordered_ps_done s_endpgm_saved s_icache_inv - s_incperflevel :ref:`imm16` - s_inst_prefetch :ref:`imm16` - s_nop :ref:`imm16` - s_round_mode :ref:`imm16` - s_sendmsg :ref:`msg` - s_sendmsghalt :ref:`msg` - s_sethalt :ref:`imm16` - s_setkill :ref:`imm16` - s_setprio :ref:`imm16` - s_sleep :ref:`imm16` - s_trap :ref:`imm16` + s_incperflevel :ref:`imm16` + s_inst_prefetch :ref:`imm16` + s_nop :ref:`imm16` + s_round_mode :ref:`imm16` + s_sendmsg :ref:`msg` + s_sendmsghalt :ref:`msg` + s_sethalt :ref:`imm16` + s_setkill :ref:`imm16` + s_setprio :ref:`imm16` + s_sleep :ref:`imm16` + s_trap :ref:`imm16` s_ttracedata - s_ttracedata_imm :ref:`imm16` - s_waitcnt :ref:`waitcnt` + s_ttracedata_imm :ref:`imm16` + s_waitcnt :ref:`waitcnt` s_wakeup VINTRP @@ -1328,620 +1331,620 @@ VINTRP .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_interp_mov_f32 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` - v_interp_p1_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` - v_interp_p2_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_interp_mov_f32 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` + v_interp_p1_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` + v_interp_p2_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` VOP1 ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST** **SRC** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_bfrev_b32 :ref:`vdst`, :ref:`src` - v_ceil_f16 :ref:`vdst`, :ref:`src` - v_ceil_f32 :ref:`vdst`, :ref:`src` - v_ceil_f64 :ref:`vdst`, :ref:`src` + **INSTRUCTION** **DST** **SRC** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_bfrev_b32 :ref:`vdst`, :ref:`src` + v_ceil_f16 :ref:`vdst`, :ref:`src` + v_ceil_f32 :ref:`vdst`, :ref:`src` + v_ceil_f64 :ref:`vdst`, :ref:`src` v_clrexcp - v_cos_f16 :ref:`vdst`, :ref:`src` - v_cos_f32 :ref:`vdst`, :ref:`src` - v_cvt_f16_f32 :ref:`vdst`, :ref:`src` - v_cvt_f16_i16 :ref:`vdst`, :ref:`src` - v_cvt_f16_u16 :ref:`vdst`, :ref:`src` - v_cvt_f32_f16 :ref:`vdst`, :ref:`src` - v_cvt_f32_f64 :ref:`vdst`, :ref:`src` - v_cvt_f32_i32 :ref:`vdst`, :ref:`src` - v_cvt_f32_u32 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte0 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte1 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte2 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte3 :ref:`vdst`, :ref:`src` - v_cvt_f64_f32 :ref:`vdst`, :ref:`src` - v_cvt_f64_i32 :ref:`vdst`, :ref:`src` - v_cvt_f64_u32 :ref:`vdst`, :ref:`src` - v_cvt_flr_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_i16_f16 :ref:`vdst`, :ref:`src` - v_cvt_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_i32_f64 :ref:`vdst`, :ref:`src` - v_cvt_norm_i16_f16 :ref:`vdst`, :ref:`src` - v_cvt_norm_u16_f16 :ref:`vdst`, :ref:`src` - v_cvt_off_f32_i4 :ref:`vdst`, :ref:`src` - v_cvt_rpi_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_u16_f16 :ref:`vdst`, :ref:`src` - v_cvt_u32_f32 :ref:`vdst`, :ref:`src` - v_cvt_u32_f64 :ref:`vdst`, :ref:`src` - v_exp_f16 :ref:`vdst`, :ref:`src` - v_exp_f32 :ref:`vdst`, :ref:`src` - v_ffbh_i32 :ref:`vdst`, :ref:`src` - v_ffbh_u32 :ref:`vdst`, :ref:`src` - v_ffbl_b32 :ref:`vdst`, :ref:`src` - v_floor_f16 :ref:`vdst`, :ref:`src` - v_floor_f32 :ref:`vdst`, :ref:`src` - v_floor_f64 :ref:`vdst`, :ref:`src` - v_fract_f16 :ref:`vdst`, :ref:`src` - v_fract_f32 :ref:`vdst`, :ref:`src` - v_fract_f64 :ref:`vdst`, :ref:`src` - v_frexp_exp_i16_f16 :ref:`vdst`, :ref:`src` - v_frexp_exp_i32_f32 :ref:`vdst`, :ref:`src` - v_frexp_exp_i32_f64 :ref:`vdst`, :ref:`src` - v_frexp_mant_f16 :ref:`vdst`, :ref:`src` - v_frexp_mant_f32 :ref:`vdst`, :ref:`src` - v_frexp_mant_f64 :ref:`vdst`, :ref:`src` - v_log_f16 :ref:`vdst`, :ref:`src` - v_log_f32 :ref:`vdst`, :ref:`src` - v_mov_b32 :ref:`vdst`, :ref:`src` - v_movreld_b32 :ref:`vdst`, :ref:`src` - v_movrels_b32 :ref:`vdst`, :ref:`vsrc` - v_movrelsd_2_b32 :ref:`vdst`, :ref:`vsrc` - v_movrelsd_b32 :ref:`vdst`, :ref:`vsrc` + v_cos_f16 :ref:`vdst`, :ref:`src` + v_cos_f32 :ref:`vdst`, :ref:`src` + v_cvt_f16_f32 :ref:`vdst`, :ref:`src` + v_cvt_f16_i16 :ref:`vdst`, :ref:`src` + v_cvt_f16_u16 :ref:`vdst`, :ref:`src` + v_cvt_f32_f16 :ref:`vdst`, :ref:`src` + v_cvt_f32_f64 :ref:`vdst`, :ref:`src` + v_cvt_f32_i32 :ref:`vdst`, :ref:`src` + v_cvt_f32_u32 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte0 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte1 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte2 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte3 :ref:`vdst`, :ref:`src` + v_cvt_f64_f32 :ref:`vdst`, :ref:`src` + v_cvt_f64_i32 :ref:`vdst`, :ref:`src` + v_cvt_f64_u32 :ref:`vdst`, :ref:`src` + v_cvt_flr_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_i16_f16 :ref:`vdst`, :ref:`src` + v_cvt_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_i32_f64 :ref:`vdst`, :ref:`src` + v_cvt_norm_i16_f16 :ref:`vdst`, :ref:`src` + v_cvt_norm_u16_f16 :ref:`vdst`, :ref:`src` + v_cvt_off_f32_i4 :ref:`vdst`, :ref:`src` + v_cvt_rpi_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_u16_f16 :ref:`vdst`, :ref:`src` + v_cvt_u32_f32 :ref:`vdst`, :ref:`src` + v_cvt_u32_f64 :ref:`vdst`, :ref:`src` + v_exp_f16 :ref:`vdst`, :ref:`src` + v_exp_f32 :ref:`vdst`, :ref:`src` + v_ffbh_i32 :ref:`vdst`, :ref:`src` + v_ffbh_u32 :ref:`vdst`, :ref:`src` + v_ffbl_b32 :ref:`vdst`, :ref:`src` + v_floor_f16 :ref:`vdst`, :ref:`src` + v_floor_f32 :ref:`vdst`, :ref:`src` + v_floor_f64 :ref:`vdst`, :ref:`src` + v_fract_f16 :ref:`vdst`, :ref:`src` + v_fract_f32 :ref:`vdst`, :ref:`src` + v_fract_f64 :ref:`vdst`, :ref:`src` + v_frexp_exp_i16_f16 :ref:`vdst`, :ref:`src` + v_frexp_exp_i32_f32 :ref:`vdst`, :ref:`src` + v_frexp_exp_i32_f64 :ref:`vdst`, :ref:`src` + v_frexp_mant_f16 :ref:`vdst`, :ref:`src` + v_frexp_mant_f32 :ref:`vdst`, :ref:`src` + v_frexp_mant_f64 :ref:`vdst`, :ref:`src` + v_log_f16 :ref:`vdst`, :ref:`src` + v_log_f32 :ref:`vdst`, :ref:`src` + v_mov_b32 :ref:`vdst`, :ref:`src` + v_movreld_b32 :ref:`vdst`, :ref:`src` + v_movrels_b32 :ref:`vdst`, :ref:`vsrc` + v_movrelsd_2_b32 :ref:`vdst`, :ref:`vsrc` + v_movrelsd_b32 :ref:`vdst`, :ref:`vsrc` v_nop - v_not_b32 :ref:`vdst`, :ref:`src` + v_not_b32 :ref:`vdst`, :ref:`src` v_pipeflush - v_rcp_f16 :ref:`vdst`, :ref:`src` - v_rcp_f32 :ref:`vdst`, :ref:`src` - v_rcp_f64 :ref:`vdst`, :ref:`src` - v_rcp_iflag_f32 :ref:`vdst`, :ref:`src` - v_readfirstlane_b32 :ref:`sdst`, :ref:`vsrc` - v_rndne_f16 :ref:`vdst`, :ref:`src` - v_rndne_f32 :ref:`vdst`, :ref:`src` - v_rndne_f64 :ref:`vdst`, :ref:`src` - v_rsq_f16 :ref:`vdst`, :ref:`src` - v_rsq_f32 :ref:`vdst`, :ref:`src` - v_rsq_f64 :ref:`vdst`, :ref:`src` - v_sat_pk_u8_i16 :ref:`vdst`, :ref:`src` - v_sin_f16 :ref:`vdst`, :ref:`src` - v_sin_f32 :ref:`vdst`, :ref:`src` - v_sqrt_f16 :ref:`vdst`, :ref:`src` - v_sqrt_f32 :ref:`vdst`, :ref:`src` - v_sqrt_f64 :ref:`vdst`, :ref:`src` - v_swap_b32 :ref:`vdst`, :ref:`vsrc` - v_swaprel_b32 :ref:`vdst`, :ref:`vsrc` - v_trunc_f16 :ref:`vdst`, :ref:`src` - v_trunc_f32 :ref:`vdst`, :ref:`src` - v_trunc_f64 :ref:`vdst`, :ref:`src` + v_rcp_f16 :ref:`vdst`, :ref:`src` + v_rcp_f32 :ref:`vdst`, :ref:`src` + v_rcp_f64 :ref:`vdst`, :ref:`src` + v_rcp_iflag_f32 :ref:`vdst`, :ref:`src` + v_readfirstlane_b32 :ref:`sdst`, :ref:`src` + v_rndne_f16 :ref:`vdst`, :ref:`src` + v_rndne_f32 :ref:`vdst`, :ref:`src` + v_rndne_f64 :ref:`vdst`, :ref:`src` + v_rsq_f16 :ref:`vdst`, :ref:`src` + v_rsq_f32 :ref:`vdst`, :ref:`src` + v_rsq_f64 :ref:`vdst`, :ref:`src` + v_sat_pk_u8_i16 :ref:`vdst`::ref:`u8x4`, :ref:`src` + v_sin_f16 :ref:`vdst`, :ref:`src` + v_sin_f32 :ref:`vdst`, :ref:`src` + v_sqrt_f16 :ref:`vdst`, :ref:`src` + v_sqrt_f32 :ref:`vdst`, :ref:`src` + v_sqrt_f64 :ref:`vdst`, :ref:`src` + v_swap_b32 :ref:`vdst`, :ref:`vsrc` + v_swaprel_b32 :ref:`vdst`, :ref:`vsrc` + v_trunc_f16 :ref:`vdst`, :ref:`src` + v_trunc_f32 :ref:`vdst`, :ref:`src` + v_trunc_f64 :ref:`vdst`, :ref:`src` VOP2 ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add_co_ci_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_add_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_add_nc_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_and_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_ashrrev_i32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` - v_cndmask_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_fmaak_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`imm32` - v_fmaak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`imm32` - v_fmac_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_fmac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_fmamk_f16 :ref:`vdst`, :ref:`src0`, :ref:`imm32`, :ref:`vsrc2` - v_fmamk_f32 :ref:`vdst`, :ref:`src0`, :ref:`imm32`, :ref:`vsrc2` - v_ldexp_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`i16` - v_lshlrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` - v_lshrrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` - v_mac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mac_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_madak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`imm32` - v_madmk_f32 :ref:`vdst`, :ref:`src0`, :ref:`imm32`, :ref:`vsrc2` - v_max_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_hi_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_hi_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_pk_fmac_f16 :ref:`vdst`::ref:`f16x2`, :ref:`src0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` - v_sub_co_ci_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_sub_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_sub_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_sub_nc_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_subrev_co_ci_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_subrev_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_subrev_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_subrev_nc_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_xnor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_xor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_add_co_ci_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_add_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_add_nc_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_and_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_ashrrev_i32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_cndmask_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`f32`, :ref:`vsrc1`::ref:`f32` + v_fmaak_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` + v_fmaak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` + v_fmac_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_fmac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_fmamk_f16 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` + v_fmamk_f32 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` + v_ldexp_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`i16` + v_lshlrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_lshrrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_mac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mac_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_madak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` + v_madmk_f32 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` + v_max_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_hi_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_hi_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_pk_fmac_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_sub_co_ci_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_sub_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_sub_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_sub_nc_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_subrev_co_ci_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_subrev_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_subrev_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_subrev_nc_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_xnor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_xor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` VOP3 ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** + **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_add_co_ci_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` - v_add_co_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_add_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_add_lshl_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_add_nc_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` - v_add_nc_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_add_nc_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_add_nc_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_alignbit_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_alignbyte_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_and_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_and_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_ashrrev_i16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` - v_ashrrev_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_ashrrev_i64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_bcnt_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_bfe_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` - v_bfe_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_bfi_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_bfm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_bfrev_b32_e64 :ref:`vdst`, :ref:`src` - v_ceil_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_add3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_add_co_ci_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_add_co_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_add_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_lshl_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_add_nc_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` + v_add_nc_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_add_nc_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_add_nc_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_alignbit_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`b16` + v_alignbyte_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`b16` + v_and_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_and_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_ashrrev_i16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_ashrrev_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_ashrrev_i64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_bcnt_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_bfe_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` + v_bfe_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_bfi_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_bfm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_bfrev_b32_e64 :ref:`vdst`, :ref:`src` + v_ceil_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` v_clrexcp_e64 - v_cmp_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ge_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_gt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_le_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_class_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_class_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_class_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_eq_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_eq_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_eq_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_eq_i16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_eq_i32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_eq_i64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_eq_u16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_eq_u32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_eq_u64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_f_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_f_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_f_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_f_i32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_f_i64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_f_u32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_f_u64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ge_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ge_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ge_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ge_i16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ge_i32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ge_i64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ge_u16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ge_u32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ge_u64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_gt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_gt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_gt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_gt_i16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_gt_i32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_gt_i64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_gt_u16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_gt_u32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_gt_u64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_le_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_le_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_le_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_le_i16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_le_i32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_le_i64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_le_u16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_le_u32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_le_u64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_lg_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lg_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lg_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_i16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_lt_i32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_lt_i64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_lt_u16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_lt_u32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_lt_u64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ne_i16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ne_i32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ne_i64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ne_u16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ne_u32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ne_u64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_neq_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_neq_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_neq_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_t_i32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_t_i64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_t_u32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_t_u64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_tru_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_tru_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_tru_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` - v_cos_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f16_i16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` - v_cvt_f16_u16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` - v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f32_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte0_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte1_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte2_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte3_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f64_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f64_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f64_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_flr_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_norm_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_norm_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_off_f32_i4_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_pk_i16_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_cvt_pk_u8_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` - v_cvt_pknorm_i16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`op_sel` - v_cvt_pknorm_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cvt_pknorm_u16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`op_sel` - v_cvt_pknorm_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cvt_pkrtz_f16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_div_fixup_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_scale_f32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_div_scale_f64 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_exp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ffbh_i32_e64 :ref:`vdst`, :ref:`src` - v_ffbh_u32_e64 :ref:`vdst`, :ref:`src` - v_ffbl_b32_e64 :ref:`vdst`, :ref:`src` - v_floor_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_fmac_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_fmac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_fract_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_frexp_exp_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_mant_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_interp_mov_f32_e64 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` - v_interp_p1_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` - v_interp_p1ll_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32` :ref:`high` :ref:`clamp` :ref:`omod` - v_interp_p1lv_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f16x2` :ref:`high` :ref:`clamp` :ref:`omod` - v_interp_p2_f16 :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f32` :ref:`high` :ref:`clamp` - v_interp_p2_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` - v_ldexp_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i16` :ref:`clamp` - v_ldexp_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` - v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` - v_lerp_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` - v_log_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_lshl_add_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_lshl_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2` - v_lshlrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` - v_lshlrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_lshlrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_lshrrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` - v_lshrrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_lshrrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_mac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mac_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` - v_mad_i32_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`op_sel` :ref:`clamp` - v_mad_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`clamp` - v_mad_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i64` :ref:`clamp` - v_mad_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` - v_mad_u32_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`op_sel` :ref:`clamp` - v_mad_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_mad_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u64` :ref:`clamp` - v_max3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_max3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_max3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_max3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_max3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_max_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_max_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_max_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_max_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mbcnt_hi_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mbcnt_lo_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_med3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_med3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_med3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_med3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_med3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_min3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_min3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_min3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_min_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_min_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_min_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mov_b32_e64 :ref:`vdst`, :ref:`src` - v_movreld_b32_e64 :ref:`vdst`, :ref:`src` - v_movrels_b32_e64 :ref:`vdst`, :ref:`vsrc` - v_movrelsd_2_b32_e64 :ref:`vdst`, :ref:`vsrc` - v_movrelsd_b32_e64 :ref:`vdst`, :ref:`vsrc` - v_mqsad_pk_u16_u8 :ref:`vdst`::ref:`b64`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b64` :ref:`clamp` - v_mqsad_u32_u8 :ref:`vdst`::ref:`b128`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`vsrc2`::ref:`b128` :ref:`clamp` - v_msad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` :ref:`clamp` - v_mul_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_hi_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_mul_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_lo_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_lo_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_mullit_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cmp_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_class_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_class_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_class_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_eq_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_eq_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_eq_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_eq_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_eq_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_eq_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_eq_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_eq_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_eq_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_f_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_f_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_f_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_f_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_f_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_f_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_f_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ge_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ge_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ge_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_gt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_gt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_gt_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_le_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_le_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_le_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lg_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lg_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lg_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lt_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lt_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lt_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lt_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lt_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_neq_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_neq_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_neq_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_t_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_t_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_t_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_t_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_tru_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_tru_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_tru_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`ssrc2` + v_cos_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f16_i16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f16_u16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f32_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte0_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte1_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte2_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte3_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f64_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f64_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f64_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_flr_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_norm_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_norm_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_off_f32_i4_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_pk_i16_i32 :ref:`vdst`, :ref:`src0`::ref:`i32`, :ref:`src1`::ref:`i32` + v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1`::ref:`u32` + v_cvt_pk_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` + v_cvt_pknorm_i16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f16`, :ref:`src1`::ref:`m`::ref:`f16` :ref:`op_sel` + v_cvt_pknorm_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pknorm_u16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f16`, :ref:`src1`::ref:`m`::ref:`f16` :ref:`op_sel` + v_cvt_pknorm_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pkrtz_f16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` :ref:`clamp` + v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_div_fixup_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_scale_f32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_div_scale_f64 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_exp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ffbh_i32_e64 :ref:`vdst`, :ref:`src` + v_ffbh_u32_e64 :ref:`vdst`, :ref:`src` + v_ffbl_b32_e64 :ref:`vdst`, :ref:`src` + v_floor_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fmac_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_fmac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_exp_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_mant_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_interp_mov_f32_e64 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` + v_interp_p1_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` + v_interp_p1ll_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32` :ref:`high` :ref:`clamp` :ref:`omod` + v_interp_p1lv_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f16x2` :ref:`high` :ref:`clamp` :ref:`omod` + v_interp_p2_f16 :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f32` :ref:`high` :ref:`clamp` + v_interp_p2_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` + v_ldexp_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i16` :ref:`clamp` :ref:`omod` + v_ldexp_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_lerp_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` + v_log_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_lshl_add_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_lshl_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2` + v_lshlrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_lshlrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshlrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshrrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_lshrrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshrrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_mac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mac_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` + v_mad_i32_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`op_sel` :ref:`clamp` + v_mad_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`clamp` + v_mad_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i64` :ref:`clamp` + v_mad_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` + v_mad_u32_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`op_sel` :ref:`clamp` + v_mad_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_mad_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u64` :ref:`clamp` + v_max3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_max3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_max3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_max3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_max3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_max_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mbcnt_hi_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mbcnt_lo_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_med3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_med3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_med3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_med3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_med3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_min3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_min3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_min3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mov_b32_e64 :ref:`vdst`, :ref:`src` + v_movreld_b32_e64 :ref:`vdst`, :ref:`src` + v_movrels_b32_e64 :ref:`vdst`, :ref:`vsrc` + v_movrelsd_2_b32_e64 :ref:`vdst`, :ref:`vsrc` + v_movrelsd_b32_e64 :ref:`vdst`, :ref:`vsrc` + v_mqsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` :ref:`clamp` + v_mqsad_u32_u8 :ref:`vdst`::ref:`u32x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`vsrc2`::ref:`u32x4` :ref:`clamp` + v_msad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` :ref:`clamp` + v_mul_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_hi_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_mul_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_lo_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_lo_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_mullit_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` v_nop_e64 - v_not_b32_e64 :ref:`vdst`, :ref:`src` - v_or3_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_or_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_pack_b32_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`op_sel` - v_perm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_permlane16_b32 :ref:`vdst`, :ref:`vdata`, :ref:`ssrc1`, :ref:`ssrc2` :ref:`op_sel` - v_permlanex16_b32 :ref:`vdst`, :ref:`vdata`, :ref:`ssrc1`, :ref:`ssrc2` :ref:`op_sel` + v_not_b32_e64 :ref:`vdst`, :ref:`src` + v_or3_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_or_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_pack_b32_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`op_sel` + v_perm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_permlane16_b32 :ref:`vdst`, :ref:`vdata`, :ref:`ssrc1`, :ref:`ssrc2` :ref:`dpp_op_sel` + v_permlanex16_b32 :ref:`vdst`, :ref:`vdata`, :ref:`ssrc1`, :ref:`ssrc2` :ref:`dpp_op_sel` v_pipeflush_e64 - v_qsad_pk_u16_u8 :ref:`vdst`::ref:`b64`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b64` :ref:`clamp` - v_rcp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_readlane_b32 :ref:`sdst`, :ref:`vsrc0`, :ref:`ssrc1` - v_rndne_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sad_hi_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_sad_u16 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_sad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` - v_sad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_sat_pk_u8_i16_e64 :ref:`vdst`, :ref:`src` - v_sin_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sub_co_ci_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` - v_sub_co_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_sub_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_sub_nc_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` - v_sub_nc_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_sub_nc_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_sub_nc_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_subrev_co_ci_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` - v_subrev_co_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_subrev_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_subrev_nc_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod` - v_trunc_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_writelane_b32 :ref:`vdst`, :ref:`ssrc0`, :ref:`ssrc1` - v_xad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_xnor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_xor3_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_xor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_qsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` :ref:`clamp` + v_rcp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_readlane_b32 :ref:`sdst`, :ref:`src0`, :ref:`ssrc1` + v_rndne_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sad_hi_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sad_u16 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` + v_sad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sat_pk_u8_i16_e64 :ref:`vdst`::ref:`u8x4`, :ref:`src` + v_sin_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_co_ci_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_sub_co_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_sub_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_nc_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` + v_sub_nc_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_sub_nc_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_sub_nc_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_subrev_co_ci_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_subrev_co_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_subrev_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_subrev_nc_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod` + v_trunc_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_writelane_b32 :ref:`vdst`, :ref:`ssrc0`, :ref:`ssrc1` + v_xad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_xnor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_xor3_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_xor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` VOP3P ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_fma_mix_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` - v_fma_mixhi_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` - v_fma_mixlo_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` - v_pk_add_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` - v_pk_add_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` - v_pk_add_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` - v_pk_ashrrev_i16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` - v_pk_fma_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` - v_pk_lshlrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` - v_pk_lshrrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` - v_pk_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` - v_pk_mad_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` - v_pk_max_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` - v_pk_max_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` - v_pk_max_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` - v_pk_min_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` - v_pk_min_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` - v_pk_min_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` - v_pk_mul_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` - v_pk_mul_lo_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` - v_pk_sub_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` - v_pk_sub_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_fma_mix_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_fma_mixhi_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_fma_mixlo_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_pk_add_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_pk_add_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + v_pk_add_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + v_pk_ashrrev_i16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_fma_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_pk_lshlrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_lshrrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + v_pk_mad_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + v_pk_max_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_pk_max_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_max_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_min_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_pk_min_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_min_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_mul_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_pk_mul_lo_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_sub_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + v_pk_sub_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` VOPC ----------------------- @@ -1949,302 +1952,304 @@ VOPC .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_cmp_class_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmp_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmp_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmp_eq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_neq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ngt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nle_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_o_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_tru_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_u_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_class_f16 :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmpx_class_f32 :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmpx_class_f64 :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmpx_eq_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_i16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_i32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_i64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_u16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_u32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_u64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_i32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_i64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_u32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_u64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_i16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_i32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_i64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_u16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_u32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_u64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_i16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_i32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_i64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_u16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_u32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_u64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_i16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_i32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_i64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_u16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_u32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_u64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lg_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lg_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lg_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_i16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_i32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_i64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_u16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_u32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_u64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_i16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_i32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_i64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_u16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_u32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_u64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_neq_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_neq_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_neq_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nge_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nge_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nge_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ngt_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ngt_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ngt_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nle_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nle_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nle_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlg_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlg_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlg_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlt_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlt_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlt_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_o_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_o_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_o_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_i32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_i64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_u32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_u64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_tru_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_tru_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_tru_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_u_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_u_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_u_f64 :ref:`src0`, :ref:`vsrc1` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_cmp_class_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmp_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmp_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmp_eq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_neq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ngt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nle_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_o_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_tru_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_u_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_class_f16 :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmpx_class_f32 :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmpx_class_f64 :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmpx_eq_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lg_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lg_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lg_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_neq_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_neq_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_neq_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nge_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nge_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nge_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ngt_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ngt_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ngt_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nle_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nle_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nle_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlg_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlg_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlg_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlt_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlt_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlt_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_o_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_o_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_o_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_tru_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_tru_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_tru_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_u_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_u_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_u_f64 :ref:`src0`, :ref:`vsrc1` .. |---| unicode:: U+02014 .. em dash - .. toctree:: :hidden: gfx10_attr - gfx10_bimm16 - gfx10_bimm32 - gfx10_fimm16 - gfx10_fimm32 + gfx10_dst + gfx10_fx_operand gfx10_hwreg + gfx10_imm16 + gfx10_imm16_1 + gfx10_imm16_2 gfx10_label + gfx10_m + gfx10_m_1 gfx10_msg - gfx10_param - gfx10_perm_smem - gfx10_simm16 - gfx10_tgt - gfx10_uimm16 - gfx10_vcc_32 - gfx10_waitcnt - gfx10_addr_buf - gfx10_addr_ds - gfx10_addr_flat - gfx10_addr_mimg - gfx10_base_smem_addr - gfx10_base_smem_buf - gfx10_base_smem_scratch - gfx10_data_buf_atomic128 - gfx10_data_buf_atomic32 - gfx10_data_buf_atomic64 - gfx10_data_mimg_atomic_cmp - gfx10_data_mimg_atomic_reg - gfx10_data_mimg_store - gfx10_data_mimg_store_d16 - gfx10_data_smem_atomic128 - gfx10_data_smem_atomic32 - gfx10_data_smem_atomic64 - gfx10_dst_buf_128 - gfx10_dst_buf_32 - gfx10_dst_buf_64 - gfx10_dst_buf_96 - gfx10_dst_buf_lds - gfx10_dst_flat_atomic32 - gfx10_dst_flat_atomic64 - gfx10_dst_mimg_gather4 - gfx10_dst_mimg_regular - gfx10_dst_mimg_regular_d16 - gfx10_offset_buf - gfx10_offset_smem_buf - gfx10_offset_smem_plain - gfx10_rsrc_buf - gfx10_rsrc_mimg - gfx10_saddr_flat_global - gfx10_saddr_flat_scratch - gfx10_samp_mimg - gfx10_sdata128_0 - gfx10_sdata32_0 - gfx10_sdata64_0 - gfx10_sdst128_0 - gfx10_sdst256_0 - gfx10_sdst32_0 - gfx10_sdst32_1 - gfx10_sdst32_2 - gfx10_sdst512_0 - gfx10_sdst64_0 - gfx10_sdst64_1 - gfx10_src32_0 - gfx10_src32_1 - gfx10_src32_2 - gfx10_src32_3 - gfx10_src32_4 - gfx10_src32_5 - gfx10_src32_6 - gfx10_src64_0 - gfx10_src_exp - gfx10_ssrc32_0 - gfx10_ssrc32_1 - gfx10_ssrc32_2 - gfx10_ssrc32_3 - gfx10_ssrc32_4 - gfx10_ssrc32_5 - gfx10_ssrc64_0 - gfx10_ssrc64_1 - gfx10_vaddr_flat_global - gfx10_vaddr_flat_scratch - gfx10_vdata128_0 - gfx10_vdata32_0 - gfx10_vdata64_0 - gfx10_vdata96_0 - gfx10_vdst128_0 - gfx10_vdst32_0 - gfx10_vdst64_0 - gfx10_vdst96_0 - gfx10_vsrc128_0 - gfx10_vsrc32_0 - gfx10_vsrc32_1 - gfx10_vsrc64_0 - gfx10_wsdst - gfx10_wssrc - gfx10_mad_type_dev - gfx10_mod_dpp_sdwa_abs_neg - gfx10_mod_sdwa_sext - gfx10_mod_vop3_abs_neg gfx10_opt - gfx10_ret - gfx10_type_dev + gfx10_param + gfx10_probe + gfx10_saddr + gfx10_saddr_1 + gfx10_sbase + gfx10_sbase_1 + gfx10_sbase_2 + gfx10_sdata + gfx10_sdata_1 + gfx10_sdata_2 + gfx10_sdata_3 + gfx10_sdata_4 + gfx10_sdata_5 + gfx10_sdst + gfx10_sdst_1 + gfx10_sdst_2 + gfx10_sdst_3 + gfx10_sdst_4 + gfx10_sdst_5 + gfx10_sdst_6 + gfx10_sdst_7 + gfx10_sdst_8 + gfx10_simm32 + gfx10_simm32_1 + gfx10_simm32_2 + gfx10_soffset + gfx10_soffset_1 + gfx10_soffset_2 + gfx10_src + gfx10_src_1 + gfx10_src_2 + gfx10_src_3 + gfx10_src_4 + gfx10_src_5 + gfx10_src_6 + gfx10_src_7 + gfx10_src_8 + gfx10_srsrc + gfx10_srsrc_1 + gfx10_ssamp + gfx10_ssrc + gfx10_ssrc_1 + gfx10_ssrc_2 + gfx10_ssrc_3 + gfx10_ssrc_4 + gfx10_ssrc_5 + gfx10_ssrc_6 + gfx10_ssrc_7 + gfx10_ssrc_8 + gfx10_tgt + gfx10_type_deviation + gfx10_vaddr + gfx10_vaddr_1 + gfx10_vaddr_2 + gfx10_vaddr_3 + gfx10_vaddr_4 + gfx10_vaddr_5 + gfx10_vcc + gfx10_vdata + gfx10_vdata0 + gfx10_vdata0_1 + gfx10_vdata1 + gfx10_vdata1_1 + gfx10_vdata_1 + gfx10_vdata_10 + gfx10_vdata_2 + gfx10_vdata_3 + gfx10_vdata_4 + gfx10_vdata_5 + gfx10_vdata_6 + gfx10_vdata_7 + gfx10_vdata_8 + gfx10_vdata_9 + gfx10_vdst + gfx10_vdst_1 + gfx10_vdst_10 + gfx10_vdst_11 + gfx10_vdst_12 + gfx10_vdst_13 + gfx10_vdst_2 + gfx10_vdst_3 + gfx10_vdst_4 + gfx10_vdst_5 + gfx10_vdst_6 + gfx10_vdst_7 + gfx10_vdst_8 + gfx10_vdst_9 + gfx10_vsrc + gfx10_vsrc_1 + gfx10_vsrc_2 + gfx10_vsrc_3 + gfx10_waitcnt diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst index f2ea91f92163..8180202950f8 100644 --- a/llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst @@ -38,10 +38,10 @@ DPP16 .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_dot2c_f32_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_dot4c_i32_i8_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`i8x4`, :ref:`vsrc1`::ref:`i8x4` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_dot2c_f32_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_dot4c_i32_i8_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`i8x4`, :ref:`vsrc1`::ref:`i8x4` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` DPP8 ----------------------- @@ -49,9 +49,9 @@ DPP8 .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_dot2c_f32_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` :ref:`dpp8_sel` :ref:`fi` - v_dot4c_i32_i8_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`i8x4`, :ref:`vsrc1`::ref:`i8x4` :ref:`dpp8_sel` :ref:`fi` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_dot2c_f32_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` :ref:`dpp8_sel` :ref:`fi` + v_dot4c_i32_i8_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`i8x4`, :ref:`vsrc1`::ref:`i8x4` :ref:`dpp8_sel` :ref:`fi` VOP2 ----------------------- @@ -59,9 +59,9 @@ VOP2 .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_dot2c_f32_f16 :ref:`vdst`, :ref:`src0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` - v_dot4c_i32_i8 :ref:`vdst`, :ref:`src0`::ref:`i8x4`, :ref:`vsrc1`::ref:`i8x4` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_dot2c_f32_f16 :ref:`vdst`, :ref:`src0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` + v_dot4c_i32_i8 :ref:`vdst`, :ref:`src0`::ref:`i8x4`, :ref:`vsrc1`::ref:`i8x4` VOP3P ----------------------- @@ -69,26 +69,24 @@ VOP3P .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_dot2_f32_f16 :ref:`vdst`, :ref:`src0`::ref:`f16x2`, :ref:`src1`::ref:`f16x2`, :ref:`src2`::ref:`f32` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` - v_dot2_i32_i16 :ref:`vdst`, :ref:`src0`::ref:`i16x2`, :ref:`src1`::ref:`i16x2`, :ref:`src2`::ref:`i32` :ref:`clamp` - v_dot2_u32_u16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_dot4_i32_i8 :ref:`vdst`, :ref:`src0`::ref:`i8x4`, :ref:`src1`::ref:`i8x4`, :ref:`src2`::ref:`i32` :ref:`clamp` - v_dot4_u32_u8 :ref:`vdst`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_dot8_i32_i4 :ref:`vdst`, :ref:`src0`::ref:`i4x8`, :ref:`src1`::ref:`i4x8`, :ref:`src2`::ref:`i32` :ref:`clamp` - v_dot8_u32_u4 :ref:`vdst`, :ref:`src0`::ref:`u4x8`, :ref:`src1`::ref:`u4x8`, :ref:`src2`::ref:`u32` :ref:`clamp` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_dot2_f32_f16 :ref:`vdst`, :ref:`src0`::ref:`f16x2`, :ref:`src1`::ref:`f16x2`, :ref:`src2`::ref:`f32` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_dot2_i32_i16 :ref:`vdst`, :ref:`src0`::ref:`i16x2`, :ref:`src1`::ref:`i16x2`, :ref:`src2`::ref:`i32` :ref:`clamp` + v_dot2_u32_u16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_dot4_i32_i8 :ref:`vdst`, :ref:`src0`::ref:`i8x4`, :ref:`src1`::ref:`i8x4`, :ref:`src2`::ref:`i32` :ref:`clamp` + v_dot4_u32_u8 :ref:`vdst`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_dot8_i32_i4 :ref:`vdst`, :ref:`src0`::ref:`i4x8`, :ref:`src1`::ref:`i4x8`, :ref:`src2`::ref:`i32` :ref:`clamp` + v_dot8_u32_u4 :ref:`vdst`, :ref:`src0`::ref:`u4x8`, :ref:`src1`::ref:`u4x8`, :ref:`src2`::ref:`u32` :ref:`clamp` .. |---| unicode:: U+02014 .. em dash - .. toctree:: :hidden: - AMDGPUAsmGFX10 - gfx1011_src32_0 - gfx1011_src32_1 - gfx1011_src32_2 - gfx1011_src32_3 - gfx1011_vdst32_0 - gfx1011_vsrc32_0 - gfx1011_type_dev + gfx1011_src + gfx1011_src_1 + gfx1011_src_2 + gfx1011_src_3 + gfx1011_type_deviation + gfx1011_vdst + gfx1011_vsrc diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst index 348285e329b4..2456ce359fe7 100644 --- a/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst @@ -6,7 +6,7 @@ ************************************************** ==================================================================================== -Syntax of Core GFX7 Instructions +Syntax of GFX7 Instructions ==================================================================================== .. contents:: @@ -15,7 +15,7 @@ Syntax of Core GFX7 Instructions Introduction ============ -This document describes the syntax of *core* GFX7 instructions. +This document describes the syntax of GFX7 instructions. Notation ======== @@ -37,146 +37,146 @@ DS .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - ds_add_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_add_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_add_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_and_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_append :ref:`vdst` :ref:`offset16` :ref:`gds` - ds_cmpst_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_f32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_f64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_condxchg32_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_consume :ref:`vdst` :ref:`offset16` :ref:`gds` - ds_dec_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_dec_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_dec_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_dec_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_dec_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_dec_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_barrier :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_init :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_sema_br :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_sema_p :ref:`offset16` :ref:`gds` - ds_gws_sema_release_all :ref:`offset16` :ref:`gds` - ds_gws_sema_v :ref:`offset16` :ref:`gds` - ds_inc_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_inc_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_inc_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_inc_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_inc_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_inc_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_src2_f32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_f64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_i32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_i64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_src2_f32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_f64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_i32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_i64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_mskor_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_mskor_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_mskor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_mskor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + ds_add_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_add_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_add_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_and_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_append :ref:`vdst` :ref:`offset` :ref:`gds` + ds_cmpst_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_f32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_f64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_condxchg32_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_consume :ref:`vdst` :ref:`offset` :ref:`gds` + ds_dec_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_dec_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_dec_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_barrier :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_init :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_sema_br :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_sema_p :ref:`offset` :ref:`gds` + ds_gws_sema_release_all :ref:`offset` :ref:`gds` + ds_gws_sema_v :ref:`offset` :ref:`gds` + ds_inc_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_inc_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_inc_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_f64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_i32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_i64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_f64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_i32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_i64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_mskor_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` ds_nop - ds_or_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_or_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_ordered_count :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read2_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read2_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read2st64_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read2st64_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_rsub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_rsub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_rsub_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_rsub_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_rsub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_rsub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_sub_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_sub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_swizzle_b32 :ref:`vdst`, :ref:`vaddr` :ref:`pattern` :ref:`gds` - ds_wrap_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_write2_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write2_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write2st64_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write2st64_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_write_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_wrxchg2_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg2_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg2st64_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg2st64_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_wrxchg_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_xor_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds` + ds_or_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_or_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_ordered_count :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read2_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2st64_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2st64_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_sub_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_sub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_swizzle_b32 :ref:`vdst`, :ref:`vaddr` :ref:`pattern` :ref:`gds` + ds_wrap_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_write2_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2st64_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2st64_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_write_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_wrxchg2_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2st64_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2st64_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_wrxchg_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_xor_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` EXP ----------------------- @@ -184,8 +184,8 @@ EXP .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - exp :ref:`tgt`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vsrc2`, :ref:`vsrc3` :ref:`done` :ref:`compr` :ref:`vm` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + exp :ref:`tgt`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vsrc2`, :ref:`vsrc3` :ref:`done` :ref:`compr` :ref:`vm` FLAT ----------------------- @@ -193,228 +193,231 @@ FLAT .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - flat_atomic_add :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_add_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_and :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_and_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_cmpswap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2` :ref:`glc` :ref:`slc` - flat_atomic_cmpswap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2` :ref:`glc` :ref:`slc` - flat_atomic_dec :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` - flat_atomic_dec_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` - flat_atomic_fcmpswap :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32x2` :ref:`glc` :ref:`slc` - flat_atomic_fcmpswap_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64x2` :ref:`glc` :ref:`slc` - flat_atomic_fmax :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`glc` :ref:`slc` - flat_atomic_fmax_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`glc` :ref:`slc` - flat_atomic_fmin :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`glc` :ref:`slc` - flat_atomic_fmin_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`glc` :ref:`slc` - flat_atomic_inc :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` - flat_atomic_inc_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` - flat_atomic_or :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_or_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_smax :ref:`vdst`::ref:`opt`::ref:`s32`, :ref:`vaddr`, :ref:`vdata`::ref:`s32` :ref:`glc` :ref:`slc` - flat_atomic_smax_x2 :ref:`vdst`::ref:`opt`::ref:`s64`, :ref:`vaddr`, :ref:`vdata`::ref:`s64` :ref:`glc` :ref:`slc` - flat_atomic_smin :ref:`vdst`::ref:`opt`::ref:`s32`, :ref:`vaddr`, :ref:`vdata`::ref:`s32` :ref:`glc` :ref:`slc` - flat_atomic_smin_x2 :ref:`vdst`::ref:`opt`::ref:`s64`, :ref:`vaddr`, :ref:`vdata`::ref:`s64` :ref:`glc` :ref:`slc` - flat_atomic_sub :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_sub_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_swap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_swap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_umax :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` - flat_atomic_umax_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` - flat_atomic_umin :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` - flat_atomic_umin_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` - flat_atomic_xor :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_xor_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_load_dword :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_dwordx2 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_dwordx3 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_dwordx4 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_sbyte :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_sshort :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_ubyte :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_ushort :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_store_byte :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_store_dword :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_store_dwordx2 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_store_dwordx3 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_store_dwordx4 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_store_short :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + flat_atomic_add :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_add_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_and :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_and_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_cmpswap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2` :ref:`glc` :ref:`slc` + flat_atomic_cmpswap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2` :ref:`glc` :ref:`slc` + flat_atomic_dec :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` + flat_atomic_dec_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` + flat_atomic_fcmpswap :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32x2` :ref:`glc` :ref:`slc` + flat_atomic_fcmpswap_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64x2` :ref:`glc` :ref:`slc` + flat_atomic_fmax :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`glc` :ref:`slc` + flat_atomic_fmax_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`glc` :ref:`slc` + flat_atomic_fmin :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`glc` :ref:`slc` + flat_atomic_fmin_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`glc` :ref:`slc` + flat_atomic_inc :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` + flat_atomic_inc_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` + flat_atomic_or :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_or_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_smax :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32` :ref:`glc` :ref:`slc` + flat_atomic_smax_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64` :ref:`glc` :ref:`slc` + flat_atomic_smin :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32` :ref:`glc` :ref:`slc` + flat_atomic_smin_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64` :ref:`glc` :ref:`slc` + flat_atomic_sub :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_sub_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_swap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_swap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_umax :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` + flat_atomic_umax_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` + flat_atomic_umin :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` + flat_atomic_umin_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` + flat_atomic_xor :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_xor_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_load_dword :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_dwordx2 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_dwordx3 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_dwordx4 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_sbyte :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_sshort :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_ubyte :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_ushort :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_store_byte :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_store_dword :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_store_dwordx2 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_store_dwordx3 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_store_dwordx4 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_store_short :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` MIMG ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - image_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_cmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_dec :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_inc :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_smax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_smin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_umax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_umin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_gather4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_get_lod :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_get_resinfo :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load_mip :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load_mip_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load_mip_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_store :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_store_mip :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_store_mip_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_store_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + image_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_cmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_dec :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_fcmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_fmax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_fmin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_inc :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_smax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_smin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_umax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_umin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_gather4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_get_lod :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_get_resinfo :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load_mip :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load_mip_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load_mip_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_store :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_store_mip :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_store_mip_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_store_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` MTBUF ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - tbuffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + tbuffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` MUBUF ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - buffer_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_add_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_and_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_cmpswap :ref:`vdata`::ref:`dst`::ref:`b32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_cmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`b64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_dec :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_dec_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fcmpswap :ref:`vdata`::ref:`dst`::ref:`f32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fcmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`f64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fmax :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fmax_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fmin :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fmin_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_inc :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_inc_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_or_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smax :ref:`vdata`::ref:`dst`::ref:`s32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smax_x2 :ref:`vdata`::ref:`dst`::ref:`s64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smin :ref:`vdata`::ref:`dst`::ref:`s32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smin_x2 :ref:`vdata`::ref:`dst`::ref:`s64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_sub_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_swap_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umax :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umax_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umin :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umin_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_xor_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_store_byte :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dword :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx2 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx3 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx4 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_short :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + buffer_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_add_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_and_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_cmpswap :ref:`vdata`::ref:`dst`::ref:`b32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_cmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`b64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_dec :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_dec_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fcmpswap :ref:`vdata`::ref:`dst`::ref:`f32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fcmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`f64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fmax :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fmax_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fmin :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fmin_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_inc :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_inc_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_or_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smax :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smax_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smin :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smin_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_sub_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_swap_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umax :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umax_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umin :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umin_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_xor_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_store_byte :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dword :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx2 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx3 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx4 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_short :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` buffer_wbinvl1 buffer_wbinvl1_vol @@ -424,20 +427,20 @@ SMRD .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_buffer_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_buffer_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_buffer_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_buffer_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_buffer_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_buffer_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_buffer_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_buffer_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_buffer_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_buffer_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` s_dcache_inv s_dcache_inv_vol - s_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_memtime :ref:`sdst` + s_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_memtime :ref:`sdst`::ref:`b64` SOP1 ----------------------- @@ -445,55 +448,55 @@ SOP1 .. parsed-literal:: **INSTRUCTION** **DST** **SRC** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_abs_i32 :ref:`sdst`, :ref:`ssrc` - s_and_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_andn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_bcnt0_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_bcnt0_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_bcnt1_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_bcnt1_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_bitset0_b32 :ref:`sdst`, :ref:`ssrc` - s_bitset0_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` - s_bitset1_b32 :ref:`sdst`, :ref:`ssrc` - s_bitset1_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` - s_brev_b32 :ref:`sdst`, :ref:`ssrc` - s_brev_b64 :ref:`sdst`, :ref:`ssrc` - s_cbranch_join :ref:`ssrc` - s_cmov_b32 :ref:`sdst`, :ref:`ssrc` - s_cmov_b64 :ref:`sdst`, :ref:`ssrc` - s_ff0_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_ff0_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_ff1_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_ff1_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32_i64 :ref:`sdst`, :ref:`ssrc` - s_getpc_b64 :ref:`sdst` - s_mov_b32 :ref:`sdst`, :ref:`ssrc` - s_mov_b64 :ref:`sdst`, :ref:`ssrc` - s_movreld_b32 :ref:`sdst`, :ref:`ssrc` - s_movreld_b64 :ref:`sdst`, :ref:`ssrc` - s_movrels_b32 :ref:`sdst`, :ref:`ssrc` - s_movrels_b64 :ref:`sdst`, :ref:`ssrc` - s_nand_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_nor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_not_b32 :ref:`sdst`, :ref:`ssrc` - s_not_b64 :ref:`sdst`, :ref:`ssrc` - s_or_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_orn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_quadmask_b32 :ref:`sdst`, :ref:`ssrc` - s_quadmask_b64 :ref:`sdst`, :ref:`ssrc` - s_rfe_b64 :ref:`ssrc` - s_setpc_b64 :ref:`ssrc` - s_sext_i32_i16 :ref:`sdst`, :ref:`ssrc` - s_sext_i32_i8 :ref:`sdst`, :ref:`ssrc` - s_swappc_b64 :ref:`sdst`, :ref:`ssrc` - s_wqm_b32 :ref:`sdst`, :ref:`ssrc` - s_wqm_b64 :ref:`sdst`, :ref:`ssrc` - s_xnor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_xor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_abs_i32 :ref:`sdst`, :ref:`ssrc` + s_and_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_andn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_bcnt0_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_bcnt0_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_bcnt1_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_bcnt1_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_bitset0_b32 :ref:`sdst`, :ref:`ssrc` + s_bitset0_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` + s_bitset1_b32 :ref:`sdst`, :ref:`ssrc` + s_bitset1_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` + s_brev_b32 :ref:`sdst`, :ref:`ssrc` + s_brev_b64 :ref:`sdst`, :ref:`ssrc` + s_cbranch_join :ref:`ssrc` + s_cmov_b32 :ref:`sdst`, :ref:`ssrc` + s_cmov_b64 :ref:`sdst`, :ref:`ssrc` + s_ff0_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_ff0_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_ff1_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_ff1_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_i64 :ref:`sdst`, :ref:`ssrc` + s_getpc_b64 :ref:`sdst` + s_mov_b32 :ref:`sdst`, :ref:`ssrc` + s_mov_b64 :ref:`sdst`, :ref:`ssrc` + s_movreld_b32 :ref:`sdst`, :ref:`ssrc` + s_movreld_b64 :ref:`sdst`, :ref:`ssrc` + s_movrels_b32 :ref:`sdst`, :ref:`ssrc` + s_movrels_b64 :ref:`sdst`, :ref:`ssrc` + s_nand_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_nor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_not_b32 :ref:`sdst`, :ref:`ssrc` + s_not_b64 :ref:`sdst`, :ref:`ssrc` + s_or_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_orn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_quadmask_b32 :ref:`sdst`, :ref:`ssrc` + s_quadmask_b64 :ref:`sdst`, :ref:`ssrc` + s_rfe_b64 :ref:`ssrc` + s_setpc_b64 :ref:`ssrc` + s_sext_i32_i16 :ref:`sdst`, :ref:`ssrc` + s_sext_i32_i8 :ref:`sdst`, :ref:`ssrc` + s_swappc_b64 :ref:`sdst`, :ref:`ssrc` + s_wqm_b32 :ref:`sdst`, :ref:`ssrc` + s_wqm_b64 :ref:`sdst`, :ref:`ssrc` + s_xnor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_xor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` SOP2 ----------------------- @@ -501,50 +504,50 @@ SOP2 .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_absdiff_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_add_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_addc_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_and_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_and_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_andn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_andn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_ashr_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_ashr_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfe_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfe_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfe_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_bfe_u64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfm_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_bfm_b64 :ref:`sdst`, :ref:`ssrc0`::ref:`b32`, :ref:`ssrc1`::ref:`b32` - s_cbranch_g_fork :ref:`ssrc0`, :ref:`ssrc1` - s_cselect_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_cselect_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_lshl_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_lshl_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_lshr_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_lshr_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_max_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_max_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_min_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_min_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_mul_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nand_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nand_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_or_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_or_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_orn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_orn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_sub_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_sub_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_subb_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xnor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xnor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_absdiff_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_add_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_addc_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_and_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_and_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_andn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_andn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_ashr_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_ashr_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_bfe_u64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfm_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_bfm_b64 :ref:`sdst`, :ref:`ssrc0`::ref:`b32`, :ref:`ssrc1`::ref:`b32` + s_cbranch_g_fork :ref:`ssrc0`, :ref:`ssrc1` + s_cselect_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_cselect_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshl_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshr_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshr_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_max_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_max_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_min_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_min_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_mul_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nand_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nand_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_or_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_or_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_orn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_orn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_sub_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_sub_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_subb_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xnor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xnor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` SOPC ----------------------- @@ -552,24 +555,24 @@ SOPC .. parsed-literal:: **INSTRUCTION** **SRC0** **SRC1** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_bitcmp0_b32 :ref:`ssrc0`, :ref:`ssrc1` - s_bitcmp0_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bitcmp1_b32 :ref:`ssrc0`, :ref:`ssrc1` - s_bitcmp1_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_cmp_eq_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_eq_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_ge_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_ge_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_gt_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_gt_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_le_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_le_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lg_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lg_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lt_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lt_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_setvskip :ref:`ssrc0`, :ref:`ssrc1` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_bitcmp0_b32 :ref:`ssrc0`, :ref:`ssrc1` + s_bitcmp0_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bitcmp1_b32 :ref:`ssrc0`, :ref:`ssrc1` + s_bitcmp1_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_cmp_eq_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_eq_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_ge_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_ge_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_gt_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_gt_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_le_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_le_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lg_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lg_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lt_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lt_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_setvskip :ref:`ssrc0`, :ref:`ssrc1` SOPK ----------------------- @@ -577,27 +580,27 @@ SOPK .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_addk_i32 :ref:`sdst`, :ref:`imm16` - s_cbranch_i_fork :ref:`ssrc`, :ref:`label` - s_cmovk_i32 :ref:`sdst`, :ref:`imm16` - s_cmpk_eq_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_eq_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_ge_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_ge_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_gt_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_gt_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_le_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_le_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lg_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lg_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lt_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lt_u32 :ref:`ssrc`, :ref:`imm16` - s_getreg_b32 :ref:`sdst`, :ref:`hwreg` - s_movk_i32 :ref:`sdst`, :ref:`imm16` - s_mulk_i32 :ref:`sdst`, :ref:`imm16` - s_setreg_b32 :ref:`hwreg`, :ref:`ssrc` - s_setreg_imm32_b32 :ref:`hwreg`, :ref:`imm32` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_addk_i32 :ref:`sdst`, :ref:`imm16` + s_cbranch_i_fork :ref:`ssrc`, :ref:`label` + s_cmovk_i32 :ref:`sdst`, :ref:`imm16` + s_cmpk_eq_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_eq_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_ge_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_ge_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_gt_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_gt_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_le_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_le_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lg_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lg_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lt_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lt_u32 :ref:`ssrc`, :ref:`imm16` + s_getreg_b32 :ref:`sdst`, :ref:`hwreg` + s_movk_i32 :ref:`sdst`, :ref:`imm16` + s_mulk_i32 :ref:`sdst`, :ref:`imm16` + s_setreg_b32 :ref:`hwreg`, :ref:`ssrc` + s_setreg_imm32_b32 :ref:`hwreg`, :ref:`simm32` SOPP ----------------------- @@ -605,33 +608,33 @@ SOPP .. parsed-literal:: **INSTRUCTION** **SRC** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| s_barrier - s_branch :ref:`label` - s_cbranch_cdbgsys :ref:`label` - s_cbranch_cdbgsys_and_user :ref:`label` - s_cbranch_cdbgsys_or_user :ref:`label` - s_cbranch_cdbguser :ref:`label` - s_cbranch_execnz :ref:`label` - s_cbranch_execz :ref:`label` - s_cbranch_scc0 :ref:`label` - s_cbranch_scc1 :ref:`label` - s_cbranch_vccnz :ref:`label` - s_cbranch_vccz :ref:`label` - s_decperflevel :ref:`imm16` + s_branch :ref:`label` + s_cbranch_cdbgsys :ref:`label` + s_cbranch_cdbgsys_and_user :ref:`label` + s_cbranch_cdbgsys_or_user :ref:`label` + s_cbranch_cdbguser :ref:`label` + s_cbranch_execnz :ref:`label` + s_cbranch_execz :ref:`label` + s_cbranch_scc0 :ref:`label` + s_cbranch_scc1 :ref:`label` + s_cbranch_vccnz :ref:`label` + s_cbranch_vccz :ref:`label` + s_decperflevel :ref:`imm16` s_endpgm s_icache_inv - s_incperflevel :ref:`imm16` - s_nop :ref:`imm16` - s_sendmsg :ref:`msg` - s_sendmsghalt :ref:`msg` - s_sethalt :ref:`imm16` - s_setkill :ref:`imm16` - s_setprio :ref:`imm16` - s_sleep :ref:`imm16` - s_trap :ref:`imm16` + s_incperflevel :ref:`imm16` + s_nop :ref:`imm16` + s_sendmsg :ref:`msg` + s_sendmsghalt :ref:`msg` + s_sethalt :ref:`imm16` + s_setkill :ref:`imm16` + s_setprio :ref:`imm16` + s_sleep :ref:`imm16` + s_trap :ref:`imm16` s_ttracedata - s_waitcnt :ref:`waitcnt` + s_waitcnt :ref:`waitcnt` VINTRP ----------------------- @@ -639,10 +642,10 @@ VINTRP .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_interp_mov_f32 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` - v_interp_p1_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` - v_interp_p2_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_interp_mov_f32 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` + v_interp_p1_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` + v_interp_p2_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` VOP1 ----------------------- @@ -650,72 +653,72 @@ VOP1 .. parsed-literal:: **INSTRUCTION** **DST** **SRC** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_bfrev_b32 :ref:`vdst`, :ref:`src` - v_ceil_f32 :ref:`vdst`, :ref:`src` - v_ceil_f64 :ref:`vdst`, :ref:`src` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_bfrev_b32 :ref:`vdst`, :ref:`src` + v_ceil_f32 :ref:`vdst`, :ref:`src` + v_ceil_f64 :ref:`vdst`, :ref:`src` v_clrexcp - v_cos_f32 :ref:`vdst`, :ref:`src` - v_cvt_f16_f32 :ref:`vdst`, :ref:`src` - v_cvt_f32_f16 :ref:`vdst`, :ref:`src` - v_cvt_f32_f64 :ref:`vdst`, :ref:`src` - v_cvt_f32_i32 :ref:`vdst`, :ref:`src` - v_cvt_f32_u32 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte0 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte1 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte2 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte3 :ref:`vdst`, :ref:`src` - v_cvt_f64_f32 :ref:`vdst`, :ref:`src` - v_cvt_f64_i32 :ref:`vdst`, :ref:`src` - v_cvt_f64_u32 :ref:`vdst`, :ref:`src` - v_cvt_flr_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_i32_f64 :ref:`vdst`, :ref:`src` - v_cvt_off_f32_i4 :ref:`vdst`, :ref:`src` - v_cvt_rpi_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_u32_f32 :ref:`vdst`, :ref:`src` - v_cvt_u32_f64 :ref:`vdst`, :ref:`src` - v_exp_f32 :ref:`vdst`, :ref:`src` - v_exp_legacy_f32 :ref:`vdst`, :ref:`src` - v_ffbh_i32 :ref:`vdst`, :ref:`src` - v_ffbh_u32 :ref:`vdst`, :ref:`src` - v_ffbl_b32 :ref:`vdst`, :ref:`src` - v_floor_f32 :ref:`vdst`, :ref:`src` - v_floor_f64 :ref:`vdst`, :ref:`src` - v_fract_f32 :ref:`vdst`, :ref:`src` - v_fract_f64 :ref:`vdst`, :ref:`src` - v_frexp_exp_i32_f32 :ref:`vdst`, :ref:`src` - v_frexp_exp_i32_f64 :ref:`vdst`, :ref:`src` - v_frexp_mant_f32 :ref:`vdst`, :ref:`src` - v_frexp_mant_f64 :ref:`vdst`, :ref:`src` - v_log_clamp_f32 :ref:`vdst`, :ref:`src` - v_log_f32 :ref:`vdst`, :ref:`src` - v_log_legacy_f32 :ref:`vdst`, :ref:`src` - v_mov_b32 :ref:`vdst`, :ref:`src` - v_movreld_b32 :ref:`vdst`, :ref:`src` - v_movrels_b32 :ref:`vdst`, :ref:`vsrc` - v_movrelsd_b32 :ref:`vdst`, :ref:`vsrc` + v_cos_f32 :ref:`vdst`, :ref:`src` + v_cvt_f16_f32 :ref:`vdst`, :ref:`src` + v_cvt_f32_f16 :ref:`vdst`, :ref:`src` + v_cvt_f32_f64 :ref:`vdst`, :ref:`src` + v_cvt_f32_i32 :ref:`vdst`, :ref:`src` + v_cvt_f32_u32 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte0 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte1 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte2 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte3 :ref:`vdst`, :ref:`src` + v_cvt_f64_f32 :ref:`vdst`, :ref:`src` + v_cvt_f64_i32 :ref:`vdst`, :ref:`src` + v_cvt_f64_u32 :ref:`vdst`, :ref:`src` + v_cvt_flr_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_i32_f64 :ref:`vdst`, :ref:`src` + v_cvt_off_f32_i4 :ref:`vdst`, :ref:`src` + v_cvt_rpi_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_u32_f32 :ref:`vdst`, :ref:`src` + v_cvt_u32_f64 :ref:`vdst`, :ref:`src` + v_exp_f32 :ref:`vdst`, :ref:`src` + v_exp_legacy_f32 :ref:`vdst`, :ref:`src` + v_ffbh_i32 :ref:`vdst`, :ref:`src` + v_ffbh_u32 :ref:`vdst`, :ref:`src` + v_ffbl_b32 :ref:`vdst`, :ref:`src` + v_floor_f32 :ref:`vdst`, :ref:`src` + v_floor_f64 :ref:`vdst`, :ref:`src` + v_fract_f32 :ref:`vdst`, :ref:`src` + v_fract_f64 :ref:`vdst`, :ref:`src` + v_frexp_exp_i32_f32 :ref:`vdst`, :ref:`src` + v_frexp_exp_i32_f64 :ref:`vdst`, :ref:`src` + v_frexp_mant_f32 :ref:`vdst`, :ref:`src` + v_frexp_mant_f64 :ref:`vdst`, :ref:`src` + v_log_clamp_f32 :ref:`vdst`, :ref:`src` + v_log_f32 :ref:`vdst`, :ref:`src` + v_log_legacy_f32 :ref:`vdst`, :ref:`src` + v_mov_b32 :ref:`vdst`, :ref:`src` + v_movreld_b32 :ref:`vdst`, :ref:`src` + v_movrels_b32 :ref:`vdst`, :ref:`vsrc` + v_movrelsd_b32 :ref:`vdst`, :ref:`vsrc` v_nop - v_not_b32 :ref:`vdst`, :ref:`src` - v_rcp_clamp_f32 :ref:`vdst`, :ref:`src` - v_rcp_clamp_f64 :ref:`vdst`, :ref:`src` - v_rcp_f32 :ref:`vdst`, :ref:`src` - v_rcp_f64 :ref:`vdst`, :ref:`src` - v_rcp_iflag_f32 :ref:`vdst`, :ref:`src` - v_rcp_legacy_f32 :ref:`vdst`, :ref:`src` - v_readfirstlane_b32 :ref:`sdst`, :ref:`vsrc` - v_rndne_f32 :ref:`vdst`, :ref:`src` - v_rndne_f64 :ref:`vdst`, :ref:`src` - v_rsq_clamp_f32 :ref:`vdst`, :ref:`src` - v_rsq_clamp_f64 :ref:`vdst`, :ref:`src` - v_rsq_f32 :ref:`vdst`, :ref:`src` - v_rsq_f64 :ref:`vdst`, :ref:`src` - v_rsq_legacy_f32 :ref:`vdst`, :ref:`src` - v_sin_f32 :ref:`vdst`, :ref:`src` - v_sqrt_f32 :ref:`vdst`, :ref:`src` - v_sqrt_f64 :ref:`vdst`, :ref:`src` - v_trunc_f32 :ref:`vdst`, :ref:`src` - v_trunc_f64 :ref:`vdst`, :ref:`src` + v_not_b32 :ref:`vdst`, :ref:`src` + v_rcp_clamp_f32 :ref:`vdst`, :ref:`src` + v_rcp_clamp_f64 :ref:`vdst`, :ref:`src` + v_rcp_f32 :ref:`vdst`, :ref:`src` + v_rcp_f64 :ref:`vdst`, :ref:`src` + v_rcp_iflag_f32 :ref:`vdst`, :ref:`src` + v_rcp_legacy_f32 :ref:`vdst`, :ref:`src` + v_readfirstlane_b32 :ref:`sdst`, :ref:`src` + v_rndne_f32 :ref:`vdst`, :ref:`src` + v_rndne_f64 :ref:`vdst`, :ref:`src` + v_rsq_clamp_f32 :ref:`vdst`, :ref:`src` + v_rsq_clamp_f64 :ref:`vdst`, :ref:`src` + v_rsq_f32 :ref:`vdst`, :ref:`src` + v_rsq_f64 :ref:`vdst`, :ref:`src` + v_rsq_legacy_f32 :ref:`vdst`, :ref:`src` + v_sin_f32 :ref:`vdst`, :ref:`src` + v_sqrt_f32 :ref:`vdst`, :ref:`src` + v_sqrt_f64 :ref:`vdst`, :ref:`src` + v_trunc_f32 :ref:`vdst`, :ref:`src` + v_trunc_f64 :ref:`vdst`, :ref:`src` VOP2 ----------------------- @@ -723,427 +726,427 @@ VOP2 .. parsed-literal:: **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_add_i32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_addc_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_and_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_ashr_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`u32` - v_ashrrev_i32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` - v_bcnt_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_bfm_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_cndmask_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_cvt_pk_i16_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_cvt_pkaccum_u8_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`u32` - v_cvt_pknorm_i16_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_cvt_pknorm_u16_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_ldexp_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`i32` - v_lshl_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`u32` - v_lshlrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` - v_lshr_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`u32` - v_lshrrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` - v_mac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mac_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_madak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`imm32` - v_madmk_f32 :ref:`vdst`, :ref:`src0`, :ref:`imm32`, :ref:`vsrc2` - v_max_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mbcnt_hi_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mbcnt_lo_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_hi_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_hi_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_readlane_b32 :ref:`sdst`, :ref:`vsrc0`, :ref:`ssrc1` - v_sub_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_sub_i32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_subb_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_subbrev_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_subrev_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_subrev_i32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_writelane_b32 :ref:`vdst`, :ref:`ssrc0`, :ref:`ssrc1` - v_xor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_add_i32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_addc_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_and_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_ashr_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`u32` + v_ashrrev_i32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_bcnt_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_bfm_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_cndmask_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_cvt_pk_i16_i32 :ref:`vdst`, :ref:`src0`::ref:`i32`, :ref:`vsrc1`::ref:`i32` + v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1`::ref:`u32` + v_cvt_pkaccum_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`f32`, :ref:`vsrc1`::ref:`u32` + v_cvt_pknorm_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`f32`, :ref:`vsrc1`::ref:`f32` + v_cvt_pknorm_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`f32`, :ref:`vsrc1`::ref:`f32` + v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`f32`, :ref:`vsrc1`::ref:`f32` + v_ldexp_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`i32` + v_lshl_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`u32` + v_lshlrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_lshr_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`u32` + v_lshrrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_mac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mac_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_madak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` + v_madmk_f32 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` + v_max_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mbcnt_hi_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mbcnt_lo_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_hi_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_hi_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_readlane_b32 :ref:`sdst`, :ref:`src0`, :ref:`ssrc1` + v_sub_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_sub_i32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_subb_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_subbrev_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_subrev_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_subrev_i32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_writelane_b32 :ref:`vdst`, :ref:`ssrc0`, :ref:`ssrc1` + v_xor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` VOP3 ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_add_i32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_addc_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` - v_alignbit_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_alignbyte_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_and_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_ashr_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` - v_ashr_i64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` - v_ashrrev_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_bcnt_u32_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_bfe_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` - v_bfe_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_bfi_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_bfm_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_bfrev_b32_e64 :ref:`vdst`, :ref:`src` - v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_i32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_addc_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` + v_alignbit_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_alignbyte_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_and_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_ashr_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` + v_ashr_i64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` + v_ashrrev_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_bcnt_u32_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_bfe_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` + v_bfe_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_bfi_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_bfm_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_bfrev_b32_e64 :ref:`vdst`, :ref:`src` + v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` v_clrexcp_e64 - v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` - v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f32_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte0_e64 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte1_e64 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte2_e64 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte3_e64 :ref:`vdst`, :ref:`src` - v_cvt_f64_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f64_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f64_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_flr_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_off_f32_i4_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_pk_i16_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_cvt_pk_u16_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_cvt_pk_u8_f32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` - v_cvt_pkaccum_u8_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` - v_cvt_pknorm_i16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cvt_pknorm_u16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cvt_pkrtz_f16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_scale_f32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_div_scale_f64 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_exp_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ffbh_i32_e64 :ref:`vdst`, :ref:`src` - v_ffbh_u32_e64 :ref:`vdst`, :ref:`src` - v_ffbl_b32_e64 :ref:`vdst`, :ref:`src` - v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src` - v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src` - v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ldexp_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` - v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` - v_lerp_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` - v_log_clamp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_log_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_lshl_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` - v_lshl_b64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` - v_lshlrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_lshr_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` - v_lshr_b64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` - v_lshrrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_mac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mac_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` - v_mad_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i64` - v_mad_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` - v_mad_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u64` - v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_max3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_max3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_max_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mbcnt_hi_u32_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mbcnt_lo_u32_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_med3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_med3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_min3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_min_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mov_b32_e64 :ref:`vdst`, :ref:`src` - v_movreld_b32_e64 :ref:`vdst`, :ref:`src` - v_movrels_b32_e64 :ref:`vdst`, :ref:`vsrc` - v_movrelsd_b32_e64 :ref:`vdst`, :ref:`vsrc` - v_mqsad_pk_u16_u8 :ref:`vdst`::ref:`b64`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b64` - v_mqsad_u32_u8 :ref:`vdst`::ref:`b128`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`vsrc2`::ref:`b128` - v_msad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` - v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_hi_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_lo_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_lo_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mullit_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` + v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f32_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte0_e64 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte1_e64 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte2_e64 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte3_e64 :ref:`vdst`, :ref:`src` + v_cvt_f64_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f64_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f64_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_flr_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_off_f32_i4_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_pk_i16_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`i32`, :ref:`src1`::ref:`i32` + v_cvt_pk_u16_u32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1`::ref:`u32` + v_cvt_pk_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`f32`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` + v_cvt_pkaccum_u8_f32_e64 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32` + v_cvt_pknorm_i16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pknorm_u16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pkrtz_f16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_scale_f32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_div_scale_f64 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_exp_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ffbh_i32_e64 :ref:`vdst`, :ref:`src` + v_ffbh_u32_e64 :ref:`vdst`, :ref:`src` + v_ffbl_b32_e64 :ref:`vdst`, :ref:`src` + v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src` + v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src` + v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ldexp_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_lerp_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` + v_log_clamp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_log_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_lshl_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` + v_lshl_b64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` + v_lshlrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshr_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` + v_lshr_b64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` + v_lshrrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_mac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mac_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` + v_mad_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i64` + v_mad_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` + v_mad_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u64` + v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_max3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_max3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mbcnt_hi_u32_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mbcnt_lo_u32_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_med3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_med3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_min3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mov_b32_e64 :ref:`vdst`, :ref:`src` + v_movreld_b32_e64 :ref:`vdst`, :ref:`src` + v_movrels_b32_e64 :ref:`vdst`, :ref:`vsrc` + v_movrelsd_b32_e64 :ref:`vdst`, :ref:`vsrc` + v_mqsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` + v_mqsad_u32_u8 :ref:`vdst`::ref:`u32x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`vsrc2`::ref:`u32x4` + v_msad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` + v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_hi_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_lo_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_lo_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mullit_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` v_nop_e64 - v_not_b32_e64 :ref:`vdst`, :ref:`src` - v_or_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_qsad_pk_u16_u8 :ref:`vdst`::ref:`b64`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b64` - v_rcp_clamp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_clamp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_clamp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_clamp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sad_hi_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` - v_sad_u16 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` - v_sad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_sad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` - v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_sub_i32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_subb_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` - v_subbrev_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` - v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_subrev_i32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod` - v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_xor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_not_b32_e64 :ref:`vdst`, :ref:`src` + v_or_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_qsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` + v_rcp_clamp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_clamp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_clamp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_clamp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sad_hi_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` + v_sad_u16 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` + v_sad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_sad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` + v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_i32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_subb_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` + v_subbrev_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` + v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_subrev_i32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod` + v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_xor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` VOPC ----------------------- @@ -1151,292 +1154,295 @@ VOPC .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_cmp_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmp_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmp_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmpx_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmpx_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_cmp_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmp_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmp_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmpx_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmpx_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` .. |---| unicode:: U+02014 .. em dash - .. toctree:: :hidden: gfx7_attr - gfx7_bimm16 - gfx7_bimm32 - gfx7_fimm32 + gfx7_dst gfx7_hwreg + gfx7_imm16 + gfx7_imm16_1 + gfx7_imm16_2 gfx7_label + gfx7_m gfx7_msg - gfx7_param - gfx7_simm16 - gfx7_tgt - gfx7_uimm16 - gfx7_waitcnt - gfx7_addr_buf - gfx7_addr_ds - gfx7_addr_flat - gfx7_addr_mimg - gfx7_base_smem_addr - gfx7_base_smem_buf - gfx7_data_buf_atomic128 - gfx7_data_buf_atomic32 - gfx7_data_buf_atomic64 - gfx7_data_mimg_atomic_cmp - gfx7_data_mimg_atomic_reg - gfx7_data_mimg_store - gfx7_dst_buf_128 - gfx7_dst_buf_32 - gfx7_dst_buf_64 - gfx7_dst_buf_96 - gfx7_dst_buf_lds - gfx7_dst_flat_atomic32 - gfx7_dst_flat_atomic64 - gfx7_dst_mimg_gather4 - gfx7_dst_mimg_regular - gfx7_offset_buf - gfx7_offset_smem - gfx7_rsrc_buf - gfx7_rsrc_mimg - gfx7_samp_mimg - gfx7_sdst128_0 - gfx7_sdst256_0 - gfx7_sdst32_0 - gfx7_sdst32_1 - gfx7_sdst32_2 - gfx7_sdst512_0 - gfx7_sdst64_0 - gfx7_sdst64_1 - gfx7_src32_0 - gfx7_src32_1 - gfx7_src32_2 - gfx7_src32_3 - gfx7_src32_4 - gfx7_src32_5 - gfx7_src32_6 - gfx7_src64_0 - gfx7_src64_1 - gfx7_src64_2 - gfx7_src_exp - gfx7_ssrc32_0 - gfx7_ssrc32_1 - gfx7_ssrc32_2 - gfx7_ssrc32_3 - gfx7_ssrc32_4 - gfx7_ssrc32_5 - gfx7_ssrc32_6 - gfx7_ssrc64_0 - gfx7_ssrc64_1 - gfx7_ssrc64_2 - gfx7_ssrc64_3 - gfx7_vcc_64 - gfx7_vdata128_0 - gfx7_vdata32_0 - gfx7_vdata64_0 - gfx7_vdata96_0 - gfx7_vdst128_0 - gfx7_vdst32_0 - gfx7_vdst64_0 - gfx7_vdst96_0 - gfx7_vsrc128_0 - gfx7_vsrc32_0 - gfx7_vsrc32_1 - gfx7_vsrc64_0 - gfx7_mod gfx7_opt - gfx7_ret - gfx7_type_dev + gfx7_param + gfx7_sbase + gfx7_sbase_1 + gfx7_sdst + gfx7_sdst_1 + gfx7_sdst_2 + gfx7_sdst_3 + gfx7_sdst_4 + gfx7_sdst_5 + gfx7_sdst_6 + gfx7_sdst_7 + gfx7_simm32 + gfx7_simm32_1 + gfx7_soffset + gfx7_soffset_1 + gfx7_src + gfx7_src_1 + gfx7_src_10 + gfx7_src_2 + gfx7_src_3 + gfx7_src_4 + gfx7_src_5 + gfx7_src_6 + gfx7_src_7 + gfx7_src_8 + gfx7_src_9 + gfx7_srsrc + gfx7_srsrc_1 + gfx7_ssamp + gfx7_ssrc + gfx7_ssrc_1 + gfx7_ssrc_10 + gfx7_ssrc_2 + gfx7_ssrc_3 + gfx7_ssrc_4 + gfx7_ssrc_5 + gfx7_ssrc_6 + gfx7_ssrc_7 + gfx7_ssrc_8 + gfx7_ssrc_9 + gfx7_tgt + gfx7_type_deviation + gfx7_vaddr + gfx7_vaddr_1 + gfx7_vaddr_2 + gfx7_vaddr_3 + gfx7_vcc + gfx7_vdata + gfx7_vdata0 + gfx7_vdata0_1 + gfx7_vdata1 + gfx7_vdata1_1 + gfx7_vdata_1 + gfx7_vdata_2 + gfx7_vdata_3 + gfx7_vdata_4 + gfx7_vdata_5 + gfx7_vdata_6 + gfx7_vdata_7 + gfx7_vdata_8 + gfx7_vdata_9 + gfx7_vdst + gfx7_vdst_1 + gfx7_vdst_10 + gfx7_vdst_11 + gfx7_vdst_12 + gfx7_vdst_2 + gfx7_vdst_3 + gfx7_vdst_4 + gfx7_vdst_5 + gfx7_vdst_6 + gfx7_vdst_7 + gfx7_vdst_8 + gfx7_vdst_9 + gfx7_vsrc + gfx7_vsrc_1 + gfx7_vsrc_2 + gfx7_vsrc_3 + gfx7_waitcnt diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst index f08457e3db23..967eaa768ff0 100644 --- a/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst @@ -6,7 +6,7 @@ ************************************************** ==================================================================================== -Syntax of Core GFX8 Instructions +Syntax of GFX8 Instructions ==================================================================================== .. contents:: @@ -15,7 +15,7 @@ Syntax of Core GFX8 Instructions Introduction ============ -This document describes the syntax of *core* GFX8 instructions. +This document describes the syntax of GFX8 instructions. Notation ======== @@ -37,151 +37,151 @@ DS .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - ds_add_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_src2_f32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_add_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_add_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_add_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_and_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_append :ref:`vdst` :ref:`offset16` :ref:`gds` - ds_bpermute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` - ds_cmpst_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_f32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_f64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_condxchg32_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_consume :ref:`vdst` :ref:`offset16` :ref:`gds` - ds_dec_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_dec_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_dec_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_dec_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_dec_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_dec_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_barrier :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_init :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_sema_br :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_sema_p :ref:`offset16` :ref:`gds` - ds_gws_sema_release_all :ref:`offset16` :ref:`gds` - ds_gws_sema_v :ref:`offset16` :ref:`gds` - ds_inc_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_inc_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_inc_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_inc_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_inc_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_inc_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_src2_f32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_f64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_i32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_i64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_src2_f32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_f64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_i32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_i64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_mskor_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_mskor_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_mskor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_mskor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + ds_add_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_add_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_add_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_add_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_and_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_append :ref:`vdst` :ref:`offset` :ref:`gds` + ds_bpermute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` + ds_cmpst_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_f32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_f64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_condxchg32_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_consume :ref:`vdst` :ref:`offset` :ref:`gds` + ds_dec_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_dec_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_dec_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_barrier :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_init :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_sema_br :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_sema_p :ref:`offset` :ref:`gds` + ds_gws_sema_release_all :ref:`offset` :ref:`gds` + ds_gws_sema_v :ref:`offset` :ref:`gds` + ds_inc_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_inc_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_inc_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_f64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_i32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_i64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_f64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_i32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_i64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_mskor_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` ds_nop - ds_or_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_or_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_ordered_count :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_permute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` - ds_read2_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read2_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read2st64_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read2st64_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_rsub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_rsub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_rsub_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_rsub_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_rsub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_rsub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_sub_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_sub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_swizzle_b32 :ref:`vdst`, :ref:`vaddr` :ref:`pattern` :ref:`gds` - ds_wrap_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_write2_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write2_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write2st64_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write2st64_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_write_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_wrxchg2_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg2_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg2st64_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg2st64_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_wrxchg_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_xor_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds` + ds_or_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_or_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_ordered_count :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_permute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` + ds_read2_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2st64_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2st64_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_sub_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_sub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_swizzle_b32 :ref:`vdst`, :ref:`vaddr` :ref:`pattern` :ref:`gds` + ds_wrap_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_write2_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2st64_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2st64_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_write_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_wrxchg2_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2st64_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2st64_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_wrxchg_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_xor_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` EXP ----------------------- @@ -189,8 +189,8 @@ EXP .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - exp :ref:`tgt`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vsrc2`, :ref:`vsrc3` :ref:`done` :ref:`compr` :ref:`vm` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + exp :ref:`tgt`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vsrc2`, :ref:`vsrc3` :ref:`done` :ref:`compr` :ref:`vm` FLAT ----------------------- @@ -198,233 +198,233 @@ FLAT .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - flat_atomic_add :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_add_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_and :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_and_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_cmpswap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2` :ref:`glc` :ref:`slc` - flat_atomic_cmpswap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2` :ref:`glc` :ref:`slc` - flat_atomic_dec :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` - flat_atomic_dec_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` - flat_atomic_inc :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` - flat_atomic_inc_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` - flat_atomic_or :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_or_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_smax :ref:`vdst`::ref:`opt`::ref:`s32`, :ref:`vaddr`, :ref:`vdata`::ref:`s32` :ref:`glc` :ref:`slc` - flat_atomic_smax_x2 :ref:`vdst`::ref:`opt`::ref:`s64`, :ref:`vaddr`, :ref:`vdata`::ref:`s64` :ref:`glc` :ref:`slc` - flat_atomic_smin :ref:`vdst`::ref:`opt`::ref:`s32`, :ref:`vaddr`, :ref:`vdata`::ref:`s32` :ref:`glc` :ref:`slc` - flat_atomic_smin_x2 :ref:`vdst`::ref:`opt`::ref:`s64`, :ref:`vaddr`, :ref:`vdata`::ref:`s64` :ref:`glc` :ref:`slc` - flat_atomic_sub :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_sub_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_swap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_swap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_umax :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` - flat_atomic_umax_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` - flat_atomic_umin :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` - flat_atomic_umin_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` - flat_atomic_xor :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_xor_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_load_dword :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_dwordx2 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_dwordx3 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_dwordx4 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_sbyte :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_sshort :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_ubyte :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_ushort :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_store_byte :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_store_dword :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_store_dwordx2 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_store_dwordx3 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_store_dwordx4 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_store_short :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + flat_atomic_add :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_add_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_and :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_and_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_cmpswap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2` :ref:`glc` :ref:`slc` + flat_atomic_cmpswap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2` :ref:`glc` :ref:`slc` + flat_atomic_dec :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` + flat_atomic_dec_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` + flat_atomic_inc :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` + flat_atomic_inc_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` + flat_atomic_or :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_or_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_smax :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32` :ref:`glc` :ref:`slc` + flat_atomic_smax_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64` :ref:`glc` :ref:`slc` + flat_atomic_smin :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32` :ref:`glc` :ref:`slc` + flat_atomic_smin_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64` :ref:`glc` :ref:`slc` + flat_atomic_sub :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_sub_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_swap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_swap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_umax :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` + flat_atomic_umax_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` + flat_atomic_umin :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` + flat_atomic_umin_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` + flat_atomic_xor :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_xor_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_load_dword :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_dwordx2 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_dwordx3 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_dwordx4 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_sbyte :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_sshort :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_ubyte :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_ushort :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_store_byte :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_store_dword :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_store_dwordx2 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_store_dwordx3 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_store_dwordx4 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_store_short :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` MIMG ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - image_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_cmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_dec :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_inc :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_smax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_smin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_umax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_umin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_gather4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_get_lod :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_get_resinfo :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_load_mip :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_load_mip_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load_mip_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_store :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16` - image_store_mip :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16` - image_store_mip_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_store_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + image_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_cmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_dec :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_inc :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_smax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_smin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_umax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_umin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_gather4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_get_lod :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_get_resinfo :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_load_mip :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_load_mip_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load_mip_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_store :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16` + image_store_mip :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16` + image_store_mip_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_store_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` MTBUF ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - tbuffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + tbuffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` MUBUF ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - buffer_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_add_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_and_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_cmpswap :ref:`vdata`::ref:`dst`::ref:`b32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_cmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`b64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_dec :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_dec_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_inc :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_inc_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_or_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smax :ref:`vdata`::ref:`dst`::ref:`s32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smax_x2 :ref:`vdata`::ref:`dst`::ref:`s64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smin :ref:`vdata`::ref:`dst`::ref:`s32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smin_x2 :ref:`vdata`::ref:`dst`::ref:`s64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_sub_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_swap_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umax :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umax_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umin :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umin_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_xor_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_store_byte :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dword :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx2 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx3 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx4 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_lds_dword :ref:`srsrc`, :ref:`soffset` :ref:`offset12` :ref:`lds` :ref:`glc` :ref:`slc` - buffer_store_short :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + buffer_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_add_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_and_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_cmpswap :ref:`vdata`::ref:`dst`::ref:`b32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_cmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`b64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_dec :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_dec_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_inc :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_inc_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_or_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smax :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smax_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smin :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smin_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_sub_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_swap_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umax :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umax_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umin :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umin_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_xor_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_store_byte :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dword :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx2 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx3 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx4 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_lds_dword :ref:`srsrc`, :ref:`soffset` :ref:`offset12` :ref:`lds` :ref:`glc` :ref:`slc` + buffer_store_short :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` buffer_wbinvl1 buffer_wbinvl1_vol @@ -434,31 +434,31 @@ SMEM .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_atc_probe :ref:`imm3`, :ref:`sbase`, :ref:`soffset` - s_atc_probe_buffer :ref:`imm3`, :ref:`sbase`, :ref:`soffset` - s_buffer_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_atc_probe :ref:`probe`, :ref:`sbase`, :ref:`soffset` + s_atc_probe_buffer :ref:`probe`, :ref:`sbase`, :ref:`soffset` + s_buffer_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` s_dcache_inv s_dcache_inv_vol s_dcache_wb s_dcache_wb_vol - s_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_memrealtime :ref:`sdst` - s_memtime :ref:`sdst` - s_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_memrealtime :ref:`sdst`::ref:`b64` + s_memtime :ref:`sdst`::ref:`b64` + s_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` SOP1 ----------------------- @@ -466,56 +466,56 @@ SOP1 .. parsed-literal:: **INSTRUCTION** **DST** **SRC** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_abs_i32 :ref:`sdst`, :ref:`ssrc` - s_and_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_andn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_bcnt0_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_bcnt0_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_bcnt1_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_bcnt1_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_bitset0_b32 :ref:`sdst`, :ref:`ssrc` - s_bitset0_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` - s_bitset1_b32 :ref:`sdst`, :ref:`ssrc` - s_bitset1_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` - s_brev_b32 :ref:`sdst`, :ref:`ssrc` - s_brev_b64 :ref:`sdst`, :ref:`ssrc` - s_cbranch_join :ref:`ssrc` - s_cmov_b32 :ref:`sdst`, :ref:`ssrc` - s_cmov_b64 :ref:`sdst`, :ref:`ssrc` - s_ff0_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_ff0_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_ff1_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_ff1_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32_i64 :ref:`sdst`, :ref:`ssrc` - s_getpc_b64 :ref:`sdst` - s_mov_b32 :ref:`sdst`, :ref:`ssrc` - s_mov_b64 :ref:`sdst`, :ref:`ssrc` - s_movreld_b32 :ref:`sdst`, :ref:`ssrc` - s_movreld_b64 :ref:`sdst`, :ref:`ssrc` - s_movrels_b32 :ref:`sdst`, :ref:`ssrc` - s_movrels_b64 :ref:`sdst`, :ref:`ssrc` - s_nand_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_nor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_not_b32 :ref:`sdst`, :ref:`ssrc` - s_not_b64 :ref:`sdst`, :ref:`ssrc` - s_or_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_orn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_quadmask_b32 :ref:`sdst`, :ref:`ssrc` - s_quadmask_b64 :ref:`sdst`, :ref:`ssrc` - s_rfe_b64 :ref:`ssrc` - s_set_gpr_idx_idx :ref:`ssrc` - s_setpc_b64 :ref:`ssrc` - s_sext_i32_i16 :ref:`sdst`, :ref:`ssrc` - s_sext_i32_i8 :ref:`sdst`, :ref:`ssrc` - s_swappc_b64 :ref:`sdst`, :ref:`ssrc` - s_wqm_b32 :ref:`sdst`, :ref:`ssrc` - s_wqm_b64 :ref:`sdst`, :ref:`ssrc` - s_xnor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_xor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_abs_i32 :ref:`sdst`, :ref:`ssrc` + s_and_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_andn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_bcnt0_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_bcnt0_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_bcnt1_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_bcnt1_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_bitset0_b32 :ref:`sdst`, :ref:`ssrc` + s_bitset0_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` + s_bitset1_b32 :ref:`sdst`, :ref:`ssrc` + s_bitset1_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` + s_brev_b32 :ref:`sdst`, :ref:`ssrc` + s_brev_b64 :ref:`sdst`, :ref:`ssrc` + s_cbranch_join :ref:`ssrc` + s_cmov_b32 :ref:`sdst`, :ref:`ssrc` + s_cmov_b64 :ref:`sdst`, :ref:`ssrc` + s_ff0_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_ff0_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_ff1_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_ff1_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_i64 :ref:`sdst`, :ref:`ssrc` + s_getpc_b64 :ref:`sdst` + s_mov_b32 :ref:`sdst`, :ref:`ssrc` + s_mov_b64 :ref:`sdst`, :ref:`ssrc` + s_movreld_b32 :ref:`sdst`, :ref:`ssrc` + s_movreld_b64 :ref:`sdst`, :ref:`ssrc` + s_movrels_b32 :ref:`sdst`, :ref:`ssrc` + s_movrels_b64 :ref:`sdst`, :ref:`ssrc` + s_nand_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_nor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_not_b32 :ref:`sdst`, :ref:`ssrc` + s_not_b64 :ref:`sdst`, :ref:`ssrc` + s_or_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_orn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_quadmask_b32 :ref:`sdst`, :ref:`ssrc` + s_quadmask_b64 :ref:`sdst`, :ref:`ssrc` + s_rfe_b64 :ref:`ssrc` + s_set_gpr_idx_idx :ref:`ssrc` + s_setpc_b64 :ref:`ssrc` + s_sext_i32_i16 :ref:`sdst`, :ref:`ssrc` + s_sext_i32_i8 :ref:`sdst`, :ref:`ssrc` + s_swappc_b64 :ref:`sdst`, :ref:`ssrc` + s_wqm_b32 :ref:`sdst`, :ref:`ssrc` + s_wqm_b64 :ref:`sdst`, :ref:`ssrc` + s_xnor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_xor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` SOP2 ----------------------- @@ -523,51 +523,51 @@ SOP2 .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_absdiff_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_add_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_addc_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_and_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_and_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_andn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_andn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_ashr_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_ashr_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfe_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfe_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfe_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_bfe_u64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfm_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_bfm_b64 :ref:`sdst`, :ref:`ssrc0`::ref:`b32`, :ref:`ssrc1`::ref:`b32` - s_cbranch_g_fork :ref:`ssrc0`, :ref:`ssrc1` - s_cselect_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_cselect_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_lshl_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_lshl_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_lshr_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_lshr_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_max_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_max_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_min_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_min_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_mul_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nand_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nand_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_or_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_or_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_orn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_orn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_rfe_restore_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`b32` - s_sub_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_sub_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_subb_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xnor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xnor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_absdiff_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_add_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_addc_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_and_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_and_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_andn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_andn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_ashr_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_ashr_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_bfe_u64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfm_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_bfm_b64 :ref:`sdst`, :ref:`ssrc0`::ref:`b32`, :ref:`ssrc1`::ref:`b32` + s_cbranch_g_fork :ref:`ssrc0`, :ref:`ssrc1` + s_cselect_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_cselect_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshl_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshr_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshr_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_max_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_max_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_min_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_min_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_mul_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nand_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nand_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_or_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_or_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_orn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_orn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_rfe_restore_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`b32` + s_sub_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_sub_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_subb_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xnor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xnor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` SOPC ----------------------- @@ -575,27 +575,27 @@ SOPC .. parsed-literal:: **INSTRUCTION** **SRC0** **SRC1** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_bitcmp0_b32 :ref:`ssrc0`, :ref:`ssrc1` - s_bitcmp0_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bitcmp1_b32 :ref:`ssrc0`, :ref:`ssrc1` - s_bitcmp1_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_cmp_eq_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_eq_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_eq_u64 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_ge_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_ge_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_gt_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_gt_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_le_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_le_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lg_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lg_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lg_u64 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lt_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lt_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_set_gpr_idx_on :ref:`ssrc`, :ref:`imask` - s_setvskip :ref:`ssrc0`, :ref:`ssrc1` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_bitcmp0_b32 :ref:`ssrc0`, :ref:`ssrc1` + s_bitcmp0_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bitcmp1_b32 :ref:`ssrc0`, :ref:`ssrc1` + s_bitcmp1_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_cmp_eq_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_eq_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_eq_u64 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_ge_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_ge_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_gt_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_gt_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_le_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_le_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lg_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lg_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lg_u64 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lt_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lt_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_set_gpr_idx_on :ref:`ssrc`, :ref:`imask` + s_setvskip :ref:`ssrc0`, :ref:`ssrc1` SOPK ----------------------- @@ -603,27 +603,27 @@ SOPK .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_addk_i32 :ref:`sdst`, :ref:`imm16` - s_cbranch_i_fork :ref:`ssrc`, :ref:`label` - s_cmovk_i32 :ref:`sdst`, :ref:`imm16` - s_cmpk_eq_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_eq_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_ge_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_ge_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_gt_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_gt_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_le_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_le_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lg_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lg_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lt_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lt_u32 :ref:`ssrc`, :ref:`imm16` - s_getreg_b32 :ref:`sdst`, :ref:`hwreg` - s_movk_i32 :ref:`sdst`, :ref:`imm16` - s_mulk_i32 :ref:`sdst`, :ref:`imm16` - s_setreg_b32 :ref:`hwreg`, :ref:`ssrc` - s_setreg_imm32_b32 :ref:`hwreg`, :ref:`imm32` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + s_addk_i32 :ref:`sdst`, :ref:`imm16` + s_cbranch_i_fork :ref:`ssrc`, :ref:`label` + s_cmovk_i32 :ref:`sdst`, :ref:`imm16` + s_cmpk_eq_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_eq_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_ge_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_ge_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_gt_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_gt_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_le_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_le_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lg_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lg_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lt_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lt_u32 :ref:`ssrc`, :ref:`imm16` + s_getreg_b32 :ref:`sdst`, :ref:`hwreg` + s_movk_i32 :ref:`sdst`, :ref:`imm16` + s_mulk_i32 :ref:`sdst`, :ref:`imm16` + s_setreg_b32 :ref:`hwreg`, :ref:`ssrc` + s_setreg_imm32_b32 :ref:`hwreg`, :ref:`simm32` SOPP ----------------------- @@ -631,36 +631,36 @@ SOPP .. parsed-literal:: **INSTRUCTION** **SRC** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| s_barrier - s_branch :ref:`label` - s_cbranch_cdbgsys :ref:`label` - s_cbranch_cdbgsys_and_user :ref:`label` - s_cbranch_cdbgsys_or_user :ref:`label` - s_cbranch_cdbguser :ref:`label` - s_cbranch_execnz :ref:`label` - s_cbranch_execz :ref:`label` - s_cbranch_scc0 :ref:`label` - s_cbranch_scc1 :ref:`label` - s_cbranch_vccnz :ref:`label` - s_cbranch_vccz :ref:`label` - s_decperflevel :ref:`imm16` + s_branch :ref:`label` + s_cbranch_cdbgsys :ref:`label` + s_cbranch_cdbgsys_and_user :ref:`label` + s_cbranch_cdbgsys_or_user :ref:`label` + s_cbranch_cdbguser :ref:`label` + s_cbranch_execnz :ref:`label` + s_cbranch_execz :ref:`label` + s_cbranch_scc0 :ref:`label` + s_cbranch_scc1 :ref:`label` + s_cbranch_vccnz :ref:`label` + s_cbranch_vccz :ref:`label` + s_decperflevel :ref:`imm16` s_endpgm s_endpgm_saved s_icache_inv - s_incperflevel :ref:`imm16` - s_nop :ref:`imm16` - s_sendmsg :ref:`msg` - s_sendmsghalt :ref:`msg` - s_set_gpr_idx_mode :ref:`imask` + s_incperflevel :ref:`imm16` + s_nop :ref:`imm16` + s_sendmsg :ref:`msg` + s_sendmsghalt :ref:`msg` + s_set_gpr_idx_mode :ref:`imask` s_set_gpr_idx_off - s_sethalt :ref:`imm16` - s_setkill :ref:`imm16` - s_setprio :ref:`imm16` - s_sleep :ref:`imm16` - s_trap :ref:`imm16` + s_sethalt :ref:`imm16` + s_setkill :ref:`imm16` + s_setprio :ref:`imm16` + s_sleep :ref:`imm16` + s_trap :ref:`imm16` s_ttracedata - s_waitcnt :ref:`waitcnt` + s_waitcnt :ref:`waitcnt` s_wakeup VINTRP @@ -669,10 +669,10 @@ VINTRP .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_interp_mov_f32 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` - v_interp_p1_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` - v_interp_p2_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_interp_mov_f32 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` + v_interp_p1_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` + v_interp_p2_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` VOP1 ----------------------- @@ -680,755 +680,749 @@ VOP1 .. parsed-literal:: **INSTRUCTION** **DST** **SRC** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_bfrev_b32 :ref:`vdst`, :ref:`src` - v_bfrev_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_bfrev_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ceil_f16 :ref:`vdst`, :ref:`src` - v_ceil_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ceil_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ceil_f32 :ref:`vdst`, :ref:`src` - v_ceil_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ceil_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ceil_f64 :ref:`vdst`, :ref:`src` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_bfrev_b32 :ref:`vdst`, :ref:`src` + v_bfrev_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_bfrev_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ceil_f16 :ref:`vdst`, :ref:`src` + v_ceil_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_ceil_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ceil_f32 :ref:`vdst`, :ref:`src` + v_ceil_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_ceil_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ceil_f64 :ref:`vdst`, :ref:`src` v_clrexcp - v_cos_f16 :ref:`vdst`, :ref:`src` - v_cos_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cos_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cos_f32 :ref:`vdst`, :ref:`src` - v_cos_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cos_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f16_f32 :ref:`vdst`, :ref:`src` - v_cvt_f16_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f16_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f16_i16 :ref:`vdst`, :ref:`src` - v_cvt_f16_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f16_i16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f16_u16 :ref:`vdst`, :ref:`src` - v_cvt_f16_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f16_u16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_f16 :ref:`vdst`, :ref:`src` - v_cvt_f32_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_f64 :ref:`vdst`, :ref:`src` - v_cvt_f32_i32 :ref:`vdst`, :ref:`src` - v_cvt_f32_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_i32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_u32 :ref:`vdst`, :ref:`src` - v_cvt_f32_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_u32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_ubyte0 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte0_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_ubyte0_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_ubyte1 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte1_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_ubyte1_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_ubyte2 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte2_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_ubyte2_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_ubyte3 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte3_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_ubyte3_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f64_f32 :ref:`vdst`, :ref:`src` - v_cvt_f64_i32 :ref:`vdst`, :ref:`src` - v_cvt_f64_u32 :ref:`vdst`, :ref:`src` - v_cvt_flr_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_flr_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_flr_i32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_i16_f16 :ref:`vdst`, :ref:`src` - v_cvt_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_i16_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_i32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_i32_f64 :ref:`vdst`, :ref:`src` - v_cvt_off_f32_i4 :ref:`vdst`, :ref:`src` - v_cvt_off_f32_i4_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_off_f32_i4_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_rpi_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_rpi_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_rpi_i32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_u16_f16 :ref:`vdst`, :ref:`src` - v_cvt_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_u16_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_u32_f32 :ref:`vdst`, :ref:`src` - v_cvt_u32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_u32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_u32_f64 :ref:`vdst`, :ref:`src` - v_exp_f16 :ref:`vdst`, :ref:`src` - v_exp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_exp_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_exp_f32 :ref:`vdst`, :ref:`src` - v_exp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_exp_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_exp_legacy_f32 :ref:`vdst`, :ref:`src` - v_exp_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_exp_legacy_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ffbh_i32 :ref:`vdst`, :ref:`src` - v_ffbh_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ffbh_i32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ffbh_u32 :ref:`vdst`, :ref:`src` - v_ffbh_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ffbh_u32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ffbl_b32 :ref:`vdst`, :ref:`src` - v_ffbl_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ffbl_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_floor_f16 :ref:`vdst`, :ref:`src` - v_floor_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_floor_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_floor_f32 :ref:`vdst`, :ref:`src` - v_floor_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_floor_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_floor_f64 :ref:`vdst`, :ref:`src` - v_fract_f16 :ref:`vdst`, :ref:`src` - v_fract_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_fract_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_fract_f32 :ref:`vdst`, :ref:`src` - v_fract_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_fract_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_fract_f64 :ref:`vdst`, :ref:`src` - v_frexp_exp_i16_f16 :ref:`vdst`, :ref:`src` - v_frexp_exp_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_frexp_exp_i16_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_frexp_exp_i32_f32 :ref:`vdst`, :ref:`src` - v_frexp_exp_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_frexp_exp_i32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_frexp_exp_i32_f64 :ref:`vdst`, :ref:`src` - v_frexp_mant_f16 :ref:`vdst`, :ref:`src` - v_frexp_mant_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_frexp_mant_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_frexp_mant_f32 :ref:`vdst`, :ref:`src` - v_frexp_mant_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_frexp_mant_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_frexp_mant_f64 :ref:`vdst`, :ref:`src` - v_log_f16 :ref:`vdst`, :ref:`src` - v_log_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_log_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_log_f32 :ref:`vdst`, :ref:`src` - v_log_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_log_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_log_legacy_f32 :ref:`vdst`, :ref:`src` - v_log_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_log_legacy_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_mov_b32 :ref:`vdst`, :ref:`src` - v_mov_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mov_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_movreld_b32 :ref:`vdst`, :ref:`src` - v_movrels_b32 :ref:`vdst`, :ref:`vsrc` - v_movrelsd_b32 :ref:`vdst`, :ref:`vsrc` + v_cos_f16 :ref:`vdst`, :ref:`src` + v_cos_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cos_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cos_f32 :ref:`vdst`, :ref:`src` + v_cos_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cos_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f16_f32 :ref:`vdst`, :ref:`src` + v_cvt_f16_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f16_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f16_i16 :ref:`vdst`, :ref:`src` + v_cvt_f16_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f16_i16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f16_u16 :ref:`vdst`, :ref:`src` + v_cvt_f16_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f16_u16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_f16 :ref:`vdst`, :ref:`src` + v_cvt_f32_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f32_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_f64 :ref:`vdst`, :ref:`src` + v_cvt_f32_i32 :ref:`vdst`, :ref:`src` + v_cvt_f32_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f32_i32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_u32 :ref:`vdst`, :ref:`src` + v_cvt_f32_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f32_u32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte0 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte0_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f32_ubyte0_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte1 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte1_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f32_ubyte1_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte2 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte2_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f32_ubyte2_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte3 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte3_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f32_ubyte3_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f64_f32 :ref:`vdst`, :ref:`src` + v_cvt_f64_i32 :ref:`vdst`, :ref:`src` + v_cvt_f64_u32 :ref:`vdst`, :ref:`src` + v_cvt_flr_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_flr_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_flr_i32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_i16_f16 :ref:`vdst`, :ref:`src` + v_cvt_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_i16_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_i32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_i32_f64 :ref:`vdst`, :ref:`src` + v_cvt_off_f32_i4 :ref:`vdst`, :ref:`src` + v_cvt_off_f32_i4_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_off_f32_i4_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_rpi_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_rpi_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_rpi_i32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_u16_f16 :ref:`vdst`, :ref:`src` + v_cvt_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_u16_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_u32_f32 :ref:`vdst`, :ref:`src` + v_cvt_u32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_u32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_u32_f64 :ref:`vdst`, :ref:`src` + v_exp_f16 :ref:`vdst`, :ref:`src` + v_exp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_exp_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_exp_f32 :ref:`vdst`, :ref:`src` + v_exp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_exp_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_exp_legacy_f32 :ref:`vdst`, :ref:`src` + v_exp_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_exp_legacy_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ffbh_i32 :ref:`vdst`, :ref:`src` + v_ffbh_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_ffbh_i32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ffbh_u32 :ref:`vdst`, :ref:`src` + v_ffbh_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_ffbh_u32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ffbl_b32 :ref:`vdst`, :ref:`src` + v_ffbl_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_ffbl_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_floor_f16 :ref:`vdst`, :ref:`src` + v_floor_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_floor_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_floor_f32 :ref:`vdst`, :ref:`src` + v_floor_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_floor_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_floor_f64 :ref:`vdst`, :ref:`src` + v_fract_f16 :ref:`vdst`, :ref:`src` + v_fract_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_fract_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_fract_f32 :ref:`vdst`, :ref:`src` + v_fract_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_fract_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_fract_f64 :ref:`vdst`, :ref:`src` + v_frexp_exp_i16_f16 :ref:`vdst`, :ref:`src` + v_frexp_exp_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_frexp_exp_i16_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_exp_i32_f32 :ref:`vdst`, :ref:`src` + v_frexp_exp_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_frexp_exp_i32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_exp_i32_f64 :ref:`vdst`, :ref:`src` + v_frexp_mant_f16 :ref:`vdst`, :ref:`src` + v_frexp_mant_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_frexp_mant_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_mant_f32 :ref:`vdst`, :ref:`src` + v_frexp_mant_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_frexp_mant_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_mant_f64 :ref:`vdst`, :ref:`src` + v_log_f16 :ref:`vdst`, :ref:`src` + v_log_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_log_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_log_f32 :ref:`vdst`, :ref:`src` + v_log_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_log_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_log_legacy_f32 :ref:`vdst`, :ref:`src` + v_log_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_log_legacy_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_mov_b32 :ref:`vdst`, :ref:`src` + v_mov_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_mov_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_nop - v_not_b32 :ref:`vdst`, :ref:`src` - v_not_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_not_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rcp_f16 :ref:`vdst`, :ref:`src` - v_rcp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rcp_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rcp_f32 :ref:`vdst`, :ref:`src` - v_rcp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rcp_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rcp_f64 :ref:`vdst`, :ref:`src` - v_rcp_iflag_f32 :ref:`vdst`, :ref:`src` - v_rcp_iflag_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rcp_iflag_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_readfirstlane_b32 :ref:`sdst`, :ref:`vsrc` - v_rndne_f16 :ref:`vdst`, :ref:`src` - v_rndne_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rndne_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rndne_f32 :ref:`vdst`, :ref:`src` - v_rndne_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rndne_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rndne_f64 :ref:`vdst`, :ref:`src` - v_rsq_f16 :ref:`vdst`, :ref:`src` - v_rsq_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rsq_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rsq_f32 :ref:`vdst`, :ref:`src` - v_rsq_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rsq_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rsq_f64 :ref:`vdst`, :ref:`src` - v_sin_f16 :ref:`vdst`, :ref:`src` - v_sin_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sin_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sin_f32 :ref:`vdst`, :ref:`src` - v_sin_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sin_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sqrt_f16 :ref:`vdst`, :ref:`src` - v_sqrt_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sqrt_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sqrt_f32 :ref:`vdst`, :ref:`src` - v_sqrt_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sqrt_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sqrt_f64 :ref:`vdst`, :ref:`src` - v_trunc_f16 :ref:`vdst`, :ref:`src` - v_trunc_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_trunc_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_trunc_f32 :ref:`vdst`, :ref:`src` - v_trunc_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_trunc_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_trunc_f64 :ref:`vdst`, :ref:`src` + v_not_b32 :ref:`vdst`, :ref:`src` + v_not_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_not_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rcp_f16 :ref:`vdst`, :ref:`src` + v_rcp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rcp_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rcp_f32 :ref:`vdst`, :ref:`src` + v_rcp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rcp_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rcp_f64 :ref:`vdst`, :ref:`src` + v_rcp_iflag_f32 :ref:`vdst`, :ref:`src` + v_rcp_iflag_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rcp_iflag_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_readfirstlane_b32 :ref:`sdst`, :ref:`src` + v_rndne_f16 :ref:`vdst`, :ref:`src` + v_rndne_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rndne_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rndne_f32 :ref:`vdst`, :ref:`src` + v_rndne_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rndne_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rndne_f64 :ref:`vdst`, :ref:`src` + v_rsq_f16 :ref:`vdst`, :ref:`src` + v_rsq_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rsq_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rsq_f32 :ref:`vdst`, :ref:`src` + v_rsq_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rsq_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rsq_f64 :ref:`vdst`, :ref:`src` + v_sin_f16 :ref:`vdst`, :ref:`src` + v_sin_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sin_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sin_f32 :ref:`vdst`, :ref:`src` + v_sin_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sin_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sqrt_f16 :ref:`vdst`, :ref:`src` + v_sqrt_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sqrt_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sqrt_f32 :ref:`vdst`, :ref:`src` + v_sqrt_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sqrt_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sqrt_f64 :ref:`vdst`, :ref:`src` + v_trunc_f16 :ref:`vdst`, :ref:`src` + v_trunc_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_trunc_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_trunc_f32 :ref:`vdst`, :ref:`src` + v_trunc_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_trunc_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_trunc_f64 :ref:`vdst`, :ref:`src` VOP2 ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_add_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_add_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_add_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_add_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_add_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_add_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_add_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_add_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_add_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_add_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_addc_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_addc_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_addc_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_and_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_and_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_and_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_ashrrev_i16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`vsrc1` - v_ashrrev_i16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u16`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ashrrev_i16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u16`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_ashrrev_i32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` - v_ashrrev_i32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ashrrev_i32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u32`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_cndmask_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_cndmask_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cndmask_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_ldexp_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`i16` - v_ldexp_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`i16` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ldexp_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`i16` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_lshlrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`vsrc1` - v_lshlrev_b16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u16`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_lshlrev_b16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u16`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_lshlrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` - v_lshlrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_lshlrev_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u32`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_lshrrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`vsrc1` - v_lshrrev_b16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u16`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_lshrrev_b16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u16`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_lshrrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` - v_lshrrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_lshrrev_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u32`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mac_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mac_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mac_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mac_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mac_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_madak_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`imm32` - v_madak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`imm32` - v_madmk_f16 :ref:`vdst`, :ref:`src0`, :ref:`imm32`, :ref:`vsrc2` - v_madmk_f32 :ref:`vdst`, :ref:`src0`, :ref:`imm32`, :ref:`vsrc2` - v_max_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_max_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_max_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_max_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_max_i16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_i16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_max_i16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_max_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_max_i32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_max_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_max_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_max_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_max_u32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_min_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_min_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_min_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_min_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_min_i16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_i16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_min_i16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_min_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_min_i32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_min_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_min_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_min_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_min_u32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_hi_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_hi_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_hi_i32_i24_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_hi_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_hi_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_hi_u32_u24_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_i32_i24_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_legacy_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_lo_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_lo_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_lo_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_u32_u24_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_or_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_or_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_sub_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_sub_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sub_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_sub_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_sub_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sub_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_sub_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_sub_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sub_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_sub_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_sub_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sub_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_subb_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_subb_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_subb_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_subbrev_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_subbrev_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_subbrev_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_subrev_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_subrev_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_subrev_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_subrev_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_subrev_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_subrev_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_subrev_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_subrev_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_subrev_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_subrev_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_subrev_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_subrev_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_xor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_xor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_xor_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_add_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_add_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_add_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_add_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_add_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_add_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_add_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_add_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_add_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_add_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_add_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_addc_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_addc_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_addc_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_and_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_and_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_and_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_ashrrev_i16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`vsrc1` + v_ashrrev_i16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u16`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_ashrrev_i16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u16`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_ashrrev_i32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_ashrrev_i32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_ashrrev_i32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u32`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_cndmask_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_cndmask_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cndmask_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_ldexp_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`i16` + v_ldexp_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`i16` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_ldexp_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`i16` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_lshlrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`vsrc1` + v_lshlrev_b16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u16`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_lshlrev_b16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u16`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_lshlrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_lshlrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_lshlrev_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u32`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_lshrrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`vsrc1` + v_lshrrev_b16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u16`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_lshrrev_b16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u16`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_lshrrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_lshrrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_lshrrev_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u32`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mac_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mac_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_mac_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mac_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_mac_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_madak_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` + v_madak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` + v_madmk_f16 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` + v_madmk_f32 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` + v_max_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_max_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_max_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_i16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_i16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_max_i16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_max_i32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_max_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_max_u32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_min_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_min_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_i16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_i16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_min_i16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_min_i32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_min_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_min_u32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_mul_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_mul_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_hi_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_hi_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_mul_hi_i32_i24_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_hi_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_hi_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_mul_hi_u32_u24_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_mul_i32_i24_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_mul_legacy_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_lo_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_lo_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_mul_lo_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_mul_u32_u24_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_or_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_or_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_sub_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_sub_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sub_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_sub_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_sub_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sub_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_sub_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_sub_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sub_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_sub_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_sub_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sub_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subb_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_subb_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_subb_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subbrev_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_subbrev_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_subbrev_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_subrev_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_subrev_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_subrev_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_subrev_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_subrev_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_subrev_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_subrev_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_subrev_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_xor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_xor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_xor_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` VOP3 ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** + **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_add_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_add_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_addc_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` - v_alignbit_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_alignbyte_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_and_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_ashrrev_i16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` - v_ashrrev_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_ashrrev_i64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_bcnt_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_bfe_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` - v_bfe_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_bfi_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_bfm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_bfrev_b32_e64 :ref:`vdst`, :ref:`src` - v_ceil_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_add_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_addc_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_alignbit_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_alignbyte_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_and_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_ashrrev_i16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_ashrrev_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_ashrrev_i64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_bcnt_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_bfe_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` + v_bfe_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_bfi_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_bfm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_bfrev_b32_e64 :ref:`vdst`, :ref:`src` + v_ceil_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` v_clrexcp_e64 - v_cmp_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_f_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ge_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_gt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_le_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_t_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_f_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ge_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_gt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_le_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_t_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` - v_cos_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f16_i16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` - v_cvt_f16_u16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` - v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f32_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte0_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte1_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte2_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte3_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f64_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f64_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f64_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_flr_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_off_f32_i4_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_pk_i16_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_cvt_pk_u8_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` - v_cvt_pkaccum_u8_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` - v_cvt_pknorm_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cvt_pknorm_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_div_fixup_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` - v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_scale_f32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_div_scale_f64 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_exp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_exp_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ffbh_i32_e64 :ref:`vdst`, :ref:`src` - v_ffbh_u32_e64 :ref:`vdst`, :ref:`src` - v_ffbl_b32_e64 :ref:`vdst`, :ref:`src` - v_floor_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` - v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_fract_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_frexp_exp_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_mant_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_interp_mov_f32_e64 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` - v_interp_p1_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` - v_interp_p1ll_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32` :ref:`high` :ref:`clamp` :ref:`omod` - v_interp_p1lv_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f16x2` :ref:`high` :ref:`clamp` :ref:`omod` - v_interp_p2_f16 :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f32` :ref:`high` :ref:`clamp` - v_interp_p2_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` - v_ldexp_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i16` :ref:`clamp` - v_ldexp_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` - v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` - v_lerp_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` - v_log_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_log_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_lshlrev_b16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` - v_lshlrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_lshlrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_lshrrev_b16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` - v_lshrrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_lshrrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_mac_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_mac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` - v_mad_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` - v_mad_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`clamp` - v_mad_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i64` :ref:`clamp` - v_mad_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` - v_mad_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_mad_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u64` :ref:`clamp` - v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_max3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_max3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_max_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_i16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_max_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_max_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_max_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mbcnt_hi_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mbcnt_lo_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_med3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_med3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_min3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_i16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_min_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_min_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_min_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mov_b32_e64 :ref:`vdst`, :ref:`src` - v_movreld_b32_e64 :ref:`vdst`, :ref:`src` - v_movrels_b32_e64 :ref:`vdst`, :ref:`vsrc` - v_movrelsd_b32_e64 :ref:`vdst`, :ref:`vsrc` - v_mqsad_pk_u16_u8 :ref:`vdst`::ref:`b64`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b64` :ref:`clamp` - v_mqsad_u32_u8 :ref:`vdst`::ref:`b128`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`vsrc2`::ref:`b128` :ref:`clamp` - v_msad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` :ref:`clamp` - v_mul_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_hi_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_mul_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_lo_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_lo_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_cmp_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_t_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_eq_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_f_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_f_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ge_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ge_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_gt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_gt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_le_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_le_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_lt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ne_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ne_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_t_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` + v_cos_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f16_i16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f16_u16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f32_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte0_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte1_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte2_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte3_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f64_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f64_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f64_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_flr_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_off_f32_i4_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_pk_i16_i32 :ref:`vdst`, :ref:`src0`::ref:`i32`, :ref:`src1`::ref:`i32` + v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1`::ref:`u32` + v_cvt_pk_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` + v_cvt_pkaccum_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32` + v_cvt_pknorm_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pknorm_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_div_fixup_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_scale_f32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_div_scale_f64 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_exp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_exp_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ffbh_i32_e64 :ref:`vdst`, :ref:`src` + v_ffbh_u32_e64 :ref:`vdst`, :ref:`src` + v_ffbl_b32_e64 :ref:`vdst`, :ref:`src` + v_floor_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_exp_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_mant_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_interp_mov_f32_e64 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` + v_interp_p1_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` + v_interp_p1ll_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32` :ref:`high` :ref:`clamp` :ref:`omod` + v_interp_p1lv_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f16x2` :ref:`high` :ref:`clamp` :ref:`omod` + v_interp_p2_f16 :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f32` :ref:`high` :ref:`clamp` + v_interp_p2_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` + v_ldexp_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i16` :ref:`clamp` :ref:`omod` + v_ldexp_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_lerp_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` + v_log_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_log_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_lshlrev_b16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_lshlrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshlrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshrrev_b16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_lshrrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshrrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_mac_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` + v_mad_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`clamp` + v_mad_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i64` :ref:`clamp` + v_mad_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` + v_mad_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_mad_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u64` :ref:`clamp` + v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_max3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_max3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_max_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_i16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mbcnt_hi_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mbcnt_lo_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_med3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_med3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_min3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_i16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mov_b32_e64 :ref:`vdst`, :ref:`src` + v_mqsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` :ref:`clamp` + v_mqsad_u32_u8 :ref:`vdst`::ref:`u32x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`vsrc2`::ref:`u32x4` :ref:`clamp` + v_msad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_mul_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_hi_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_mul_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_lo_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_lo_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` v_nop_e64 - v_not_b32_e64 :ref:`vdst`, :ref:`src` - v_or_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_perm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_qsad_pk_u16_u8 :ref:`vdst`::ref:`b64`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b64` :ref:`clamp` - v_rcp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_readlane_b32 :ref:`sdst`, :ref:`vsrc0`, :ref:`ssrc1` - v_rndne_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sad_hi_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_sad_u16 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_sad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` - v_sad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_sin_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sub_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_sub_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_sub_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_subb_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` - v_subbrev_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` - v_subrev_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_subrev_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_subrev_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod` - v_trunc_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_writelane_b32 :ref:`vdst`, :ref:`ssrc0`, :ref:`ssrc1` - v_xor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_not_b32_e64 :ref:`vdst`, :ref:`src` + v_or_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_perm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_qsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` :ref:`clamp` + v_rcp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_readlane_b32 :ref:`sdst`, :ref:`src0`, :ref:`ssrc1` + v_rndne_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sad_hi_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sad_u16 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` + v_sad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sin_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_sub_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_subb_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_subbrev_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_subrev_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_subrev_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_subrev_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod` + v_trunc_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_writelane_b32 :ref:`vdst`, :ref:`ssrc0`, :ref:`ssrc1` + v_xor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` VOPC ----------------------- @@ -1436,443 +1430,445 @@ VOPC .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_cmp_class_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmp_class_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmp_class_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmp_eq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lg_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lg_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_neq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_neq_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_neq_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nge_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nge_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ngt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ngt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ngt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nle_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nle_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nle_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlg_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlg_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_o_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_o_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_o_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_tru_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_tru_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_tru_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_u_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_u_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_u_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_class_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmpx_class_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmpx_class_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmpx_eq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lg_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lg_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_neq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_neq_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_neq_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nge_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nge_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ngt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ngt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ngt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nle_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nle_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nle_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlg_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlg_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_o_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_o_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_o_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_tru_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_tru_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_tru_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_u_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_u_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_u_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_cmp_class_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmp_class_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmp_class_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmp_eq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lg_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lg_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_neq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_neq_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_neq_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nge_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nge_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ngt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ngt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ngt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nle_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nle_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nle_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlg_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlg_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_o_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_o_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_o_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_tru_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_tru_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_tru_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_u_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_u_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_u_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_class_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmpx_class_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmpx_class_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmpx_eq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lg_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lg_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_neq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_neq_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_neq_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nge_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nge_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ngt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ngt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ngt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nle_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nle_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nle_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlg_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlg_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_o_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_o_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_o_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_tru_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_tru_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_tru_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_u_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_u_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_u_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` .. |---| unicode:: U+02014 .. em dash - .. toctree:: :hidden: gfx8_attr - gfx8_bimm16 - gfx8_bimm32 - gfx8_fimm16 - gfx8_fimm32 + gfx8_dst gfx8_hwreg gfx8_imask + gfx8_imm16 + gfx8_imm16_1 + gfx8_imm16_2 gfx8_label + gfx8_m + gfx8_m_1 gfx8_msg - gfx8_param - gfx8_perm_smem - gfx8_simm16 - gfx8_tgt - gfx8_uimm16 - gfx8_waitcnt - gfx8_addr_buf - gfx8_addr_ds - gfx8_addr_flat - gfx8_addr_mimg - gfx8_base_smem_addr - gfx8_base_smem_buf - gfx8_data_buf_atomic128 - gfx8_data_buf_atomic32 - gfx8_data_buf_atomic64 - gfx8_data_buf_d16_128 - gfx8_data_buf_d16_32 - gfx8_data_buf_d16_64 - gfx8_data_buf_d16_96 - gfx8_data_mimg_atomic_cmp - gfx8_data_mimg_atomic_reg - gfx8_data_mimg_store - gfx8_data_mimg_store_d16 - gfx8_dst_buf_128 - gfx8_dst_buf_32 - gfx8_dst_buf_64 - gfx8_dst_buf_96 - gfx8_dst_buf_d16_128 - gfx8_dst_buf_d16_32 - gfx8_dst_buf_d16_64 - gfx8_dst_buf_d16_96 - gfx8_dst_buf_lds - gfx8_dst_flat_atomic32 - gfx8_dst_flat_atomic64 - gfx8_dst_mimg_gather4 - gfx8_dst_mimg_regular - gfx8_dst_mimg_regular_d16 - gfx8_offset_buf - gfx8_offset_smem_load - gfx8_offset_smem_store - gfx8_rsrc_buf - gfx8_rsrc_mimg - gfx8_samp_mimg - gfx8_sdata128_0 - gfx8_sdata32_0 - gfx8_sdata64_0 - gfx8_sdst128_0 - gfx8_sdst256_0 - gfx8_sdst32_0 - gfx8_sdst32_1 - gfx8_sdst32_2 - gfx8_sdst512_0 - gfx8_sdst64_0 - gfx8_sdst64_1 - gfx8_src32_0 - gfx8_src32_1 - gfx8_src32_2 - gfx8_src32_3 - gfx8_src32_4 - gfx8_src32_5 - gfx8_src32_6 - gfx8_src32_7 - gfx8_src64_0 - gfx8_src64_1 - gfx8_src_exp - gfx8_ssrc32_0 - gfx8_ssrc32_1 - gfx8_ssrc32_2 - gfx8_ssrc32_3 - gfx8_ssrc32_4 - gfx8_ssrc64_0 - gfx8_ssrc64_1 - gfx8_ssrc64_2 - gfx8_ssrc64_3 - gfx8_vcc_64 - gfx8_vdata128_0 - gfx8_vdata32_0 - gfx8_vdata64_0 - gfx8_vdata96_0 - gfx8_vdst128_0 - gfx8_vdst32_0 - gfx8_vdst64_0 - gfx8_vdst96_0 - gfx8_vsrc128_0 - gfx8_vsrc32_0 - gfx8_vsrc32_1 - gfx8_vsrc64_0 - gfx8_mod_dpp_sdwa_abs_neg - gfx8_mod_sdwa_sext - gfx8_mod_vop3_abs_neg gfx8_opt - gfx8_ret - gfx8_type_dev + gfx8_param + gfx8_probe + gfx8_sbase + gfx8_sbase_1 + gfx8_sdata + gfx8_sdata_1 + gfx8_sdata_2 + gfx8_sdst + gfx8_sdst_1 + gfx8_sdst_2 + gfx8_sdst_3 + gfx8_sdst_4 + gfx8_sdst_5 + gfx8_sdst_6 + gfx8_sdst_7 + gfx8_simm32 + gfx8_simm32_1 + gfx8_simm32_2 + gfx8_soffset + gfx8_soffset_1 + gfx8_soffset_2 + gfx8_src + gfx8_src_1 + gfx8_src_10 + gfx8_src_2 + gfx8_src_3 + gfx8_src_4 + gfx8_src_5 + gfx8_src_6 + gfx8_src_7 + gfx8_src_8 + gfx8_src_9 + gfx8_srsrc + gfx8_srsrc_1 + gfx8_ssamp + gfx8_ssrc + gfx8_ssrc_1 + gfx8_ssrc_2 + gfx8_ssrc_3 + gfx8_ssrc_4 + gfx8_ssrc_5 + gfx8_ssrc_6 + gfx8_ssrc_7 + gfx8_ssrc_8 + gfx8_tgt + gfx8_type_deviation + gfx8_vaddr + gfx8_vaddr_1 + gfx8_vaddr_2 + gfx8_vaddr_3 + gfx8_vcc + gfx8_vdata + gfx8_vdata0 + gfx8_vdata0_1 + gfx8_vdata1 + gfx8_vdata1_1 + gfx8_vdata_1 + gfx8_vdata_10 + gfx8_vdata_11 + gfx8_vdata_12 + gfx8_vdata_13 + gfx8_vdata_14 + gfx8_vdata_2 + gfx8_vdata_3 + gfx8_vdata_4 + gfx8_vdata_5 + gfx8_vdata_6 + gfx8_vdata_7 + gfx8_vdata_8 + gfx8_vdata_9 + gfx8_vdst + gfx8_vdst_1 + gfx8_vdst_10 + gfx8_vdst_11 + gfx8_vdst_12 + gfx8_vdst_13 + gfx8_vdst_14 + gfx8_vdst_15 + gfx8_vdst_16 + gfx8_vdst_17 + gfx8_vdst_2 + gfx8_vdst_3 + gfx8_vdst_4 + gfx8_vdst_5 + gfx8_vdst_6 + gfx8_vdst_7 + gfx8_vdst_8 + gfx8_vdst_9 + gfx8_vsrc + gfx8_vsrc_1 + gfx8_vsrc_2 + gfx8_vsrc_3 + gfx8_waitcnt diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst index 338b192ac0d6..e343d14f1d24 100644 --- a/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst @@ -38,160 +38,160 @@ DS **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - ds_add_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_src2_f32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_add_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_add_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_add_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_and_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_append :ref:`vdst` :ref:`offset16` :ref:`gds` - ds_bpermute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` - ds_cmpst_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_f32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_f64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_condxchg32_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_consume :ref:`vdst` :ref:`offset16` :ref:`gds` - ds_dec_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_dec_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_dec_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_dec_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_dec_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_dec_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_barrier :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_init :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_sema_br :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_sema_p :ref:`offset16` :ref:`gds` - ds_gws_sema_release_all :ref:`offset16` :ref:`gds` - ds_gws_sema_v :ref:`offset16` :ref:`gds` - ds_inc_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_inc_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_inc_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_inc_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_inc_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_inc_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_src2_f32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_f64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_i32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_i64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_max_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_src2_f32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_f64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_i32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_i64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_min_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_mskor_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_mskor_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_mskor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_mskor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` + ds_add_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_add_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_add_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_add_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_and_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_append :ref:`vdst` :ref:`offset` :ref:`gds` + ds_bpermute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` + ds_cmpst_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_f32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_f64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_condxchg32_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_consume :ref:`vdst` :ref:`offset` :ref:`gds` + ds_dec_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_dec_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_dec_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_barrier :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_init :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_sema_br :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_sema_p :ref:`offset` :ref:`gds` + ds_gws_sema_release_all :ref:`offset` :ref:`gds` + ds_gws_sema_v :ref:`offset` :ref:`gds` + ds_inc_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_inc_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_inc_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_f64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_i32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_i64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_f64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_i32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_i64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_mskor_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` ds_nop - ds_or_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_or_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_ordered_count :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_permute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` - ds_read2_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read2_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read2st64_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read2st64_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read_addtid_b32 :ref:`vdst` :ref:`offset16` :ref:`gds` - ds_read_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_i8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_i8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u16_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u16_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_rsub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_rsub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_rsub_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_rsub_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_rsub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_rsub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_src2_u32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_sub_src2_u64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_sub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` + ds_or_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_or_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_ordered_count :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_permute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` + ds_read2_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2st64_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2st64_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read_addtid_b32 :ref:`vdst` :ref:`offset` :ref:`gds` + ds_read_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_sub_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_sub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` ds_swizzle_b32 :ref:`vdst`, :ref:`vaddr` :ref:`pattern` :ref:`gds` - ds_wrap_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_write2_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write2_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write2st64_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write2st64_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write_addtid_b32 :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b16_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b8_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_write_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_wrxchg2_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg2_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg2st64_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg2st64_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_wrxchg_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_src2_b32 :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_xor_src2_b64 :ref:`vaddr` :ref:`offset16` :ref:`gds` + ds_wrap_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_write2_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2st64_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2st64_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write_addtid_b32 :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b16_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b8_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_write_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_wrxchg2_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2st64_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2st64_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_wrxchg_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_xor_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` EXP ----------------------- @@ -860,7 +860,7 @@ VOP1 v_bfrev_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_ceil_f16 :ref:`vdst`, :ref:`src` v_ceil_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ceil_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ceil_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_ceil_f32 :ref:`vdst`, :ref:`src` v_ceil_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_ceil_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` @@ -868,7 +868,7 @@ VOP1 v_clrexcp v_cos_f16 :ref:`vdst`, :ref:`src` v_cos_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cos_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cos_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cos_f32 :ref:`vdst`, :ref:`src` v_cos_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_cos_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` @@ -877,10 +877,10 @@ VOP1 v_cvt_f16_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_f16_i16 :ref:`vdst`, :ref:`src` v_cvt_f16_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f16_i16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f16_i16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_f16_u16 :ref:`vdst`, :ref:`src` v_cvt_f16_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f16_u16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f16_u16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_f32_f16 :ref:`vdst`, :ref:`src` v_cvt_f32_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_cvt_f32_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` @@ -937,7 +937,7 @@ VOP1 v_cvt_u32_f64 :ref:`vdst`, :ref:`src` v_exp_f16 :ref:`vdst`, :ref:`src` v_exp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_exp_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_exp_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_exp_f32 :ref:`vdst`, :ref:`src` v_exp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_exp_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` @@ -955,14 +955,14 @@ VOP1 v_ffbl_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_floor_f16 :ref:`vdst`, :ref:`src` v_floor_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_floor_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_floor_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_floor_f32 :ref:`vdst`, :ref:`src` v_floor_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_floor_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_floor_f64 :ref:`vdst`, :ref:`src` v_fract_f16 :ref:`vdst`, :ref:`src` v_fract_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_fract_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_fract_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_fract_f32 :ref:`vdst`, :ref:`src` v_fract_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_fract_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` @@ -976,14 +976,14 @@ VOP1 v_frexp_exp_i32_f64 :ref:`vdst`, :ref:`src` v_frexp_mant_f16 :ref:`vdst`, :ref:`src` v_frexp_mant_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_frexp_mant_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_mant_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_frexp_mant_f32 :ref:`vdst`, :ref:`src` v_frexp_mant_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_frexp_mant_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_frexp_mant_f64 :ref:`vdst`, :ref:`src` v_log_f16 :ref:`vdst`, :ref:`src` v_log_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_log_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_log_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_log_f32 :ref:`vdst`, :ref:`src` v_log_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_log_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` @@ -999,7 +999,7 @@ VOP1 v_not_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_rcp_f16 :ref:`vdst`, :ref:`src` v_rcp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rcp_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rcp_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_rcp_f32 :ref:`vdst`, :ref:`src` v_rcp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_rcp_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` @@ -1010,14 +1010,14 @@ VOP1 v_readfirstlane_b32 :ref:`sdst`, :ref:`src` v_rndne_f16 :ref:`vdst`, :ref:`src` v_rndne_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rndne_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rndne_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_rndne_f32 :ref:`vdst`, :ref:`src` v_rndne_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_rndne_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_rndne_f64 :ref:`vdst`, :ref:`src` v_rsq_f16 :ref:`vdst`, :ref:`src` v_rsq_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rsq_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rsq_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_rsq_f32 :ref:`vdst`, :ref:`src` v_rsq_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_rsq_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` @@ -1030,13 +1030,13 @@ VOP1 v_screen_partition_4se_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_sin_f16 :ref:`vdst`, :ref:`src` v_sin_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sin_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sin_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_sin_f32 :ref:`vdst`, :ref:`src` v_sin_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_sin_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_sqrt_f16 :ref:`vdst`, :ref:`src` v_sqrt_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sqrt_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sqrt_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_sqrt_f32 :ref:`vdst`, :ref:`src` v_sqrt_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_sqrt_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` @@ -1044,7 +1044,7 @@ VOP1 v_swap_b32 :ref:`vdst`, :ref:`vsrc` v_trunc_f16 :ref:`vdst`, :ref:`src` v_trunc_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_trunc_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_trunc_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_trunc_f32 :ref:`vdst`, :ref:`src` v_trunc_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_trunc_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` @@ -1062,7 +1062,7 @@ VOP2 v_add_co_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_add_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_add_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_add_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_add_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_add_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_add_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` @@ -1089,7 +1089,7 @@ VOP2 v_cndmask_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`vcc` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_ldexp_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`i16` v_ldexp_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`i16` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ldexp_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`i16` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_ldexp_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`i16` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_lshlrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`vsrc1` v_lshlrev_b16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u16`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_lshlrev_b16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`u16`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` @@ -1112,7 +1112,7 @@ VOP2 v_madmk_f32 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` v_max_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_max_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_max_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_max_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_max_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_max_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` @@ -1130,7 +1130,7 @@ VOP2 v_max_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_min_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_min_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_min_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_min_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_min_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_min_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` @@ -1148,7 +1148,7 @@ VOP2 v_min_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_mul_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_mul_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_mul_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_mul_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` @@ -1178,7 +1178,7 @@ VOP2 v_sub_co_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_sub_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_sub_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sub_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_sub_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_sub_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_sub_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_sub_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` @@ -1199,7 +1199,7 @@ VOP2 v_subrev_co_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_subrev_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_subrev_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_subrev_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_subrev_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_subrev_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_subrev_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` @@ -1218,443 +1218,443 @@ VOP3 .. parsed-literal:: - **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_add_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_add_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_add_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` - v_add_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_add_lshl_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_add_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_add_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_addc_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` - v_alignbit_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`b16` - v_alignbyte_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`b16` - v_and_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_and_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_ashrrev_i16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` - v_ashrrev_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_ashrrev_i64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_bcnt_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_bfe_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` - v_bfe_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_bfi_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_bfm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_bfrev_b32_e64 :ref:`vdst`, :ref:`src` - v_ceil_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_add3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_add_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_add_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` + v_add_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_add_lshl_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_add_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_add_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_addc_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_alignbit_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`b16` + v_alignbyte_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`b16` + v_and_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_and_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_ashrrev_i16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_ashrrev_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_ashrrev_i64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_bcnt_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_bfe_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` + v_bfe_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_bfi_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_bfm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_bfrev_b32_e64 :ref:`vdst`, :ref:`src` + v_ceil_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` v_clrexcp_e64 - v_cmp_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_f_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ge_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_gt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_le_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_t_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_f_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ge_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_gt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_le_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_t_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` - v_cos_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f16_i16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` - v_cvt_f16_u16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` - v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f32_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte0_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte1_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte2_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte3_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f64_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f64_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f64_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_flr_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_norm_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_norm_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_off_f32_i4_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_pk_i16_i32 :ref:`vdst`, :ref:`src0`::ref:`i32`, :ref:`src1`::ref:`i32` - v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1`::ref:`u32` - v_cvt_pk_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` - v_cvt_pkaccum_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32` - v_cvt_pknorm_i16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f16`, :ref:`src1`::ref:`m`::ref:`f16` :ref:`op_sel` - v_cvt_pknorm_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` - v_cvt_pknorm_u16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f16`, :ref:`src1`::ref:`m`::ref:`f16` :ref:`op_sel` - v_cvt_pknorm_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` - v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` - v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_div_fixup_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fixup_legacy_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` - v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_scale_f32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_div_scale_f64 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_exp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_exp_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ffbh_i32_e64 :ref:`vdst`, :ref:`src` - v_ffbh_u32_e64 :ref:`vdst`, :ref:`src` - v_ffbl_b32_e64 :ref:`vdst`, :ref:`src` - v_floor_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_legacy_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` - v_fract_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_frexp_exp_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_mant_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_interp_mov_f32_e64 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` - v_interp_p1_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` - v_interp_p1ll_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32` :ref:`high` :ref:`clamp` :ref:`omod` - v_interp_p1lv_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f16x2` :ref:`high` :ref:`clamp` :ref:`omod` - v_interp_p2_f16 :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f32` :ref:`high` :ref:`clamp` - v_interp_p2_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` - v_interp_p2_legacy_f16 :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f32` :ref:`high` :ref:`clamp` - v_ldexp_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i16` :ref:`clamp` - v_ldexp_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` - v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` - v_lerp_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` - v_log_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_log_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_lshl_add_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_lshl_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2` - v_lshlrev_b16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` - v_lshlrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_lshlrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_lshrrev_b16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` - v_lshrrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_lshrrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_mac_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_mac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_mad_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` - v_mad_i32_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`op_sel` :ref:`clamp` - v_mad_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`clamp` - v_mad_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i64` :ref:`clamp` - v_mad_legacy_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` - v_mad_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_legacy_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` - v_mad_legacy_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` - v_mad_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` - v_mad_u32_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`op_sel` :ref:`clamp` - v_mad_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_mad_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u64` :ref:`clamp` - v_max3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_max3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_max3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_max3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_max3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_max_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_i16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_max_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_max_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_max_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mbcnt_hi_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mbcnt_lo_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_med3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_med3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_med3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_med3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_med3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_min3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_min3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_min3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_i16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_min_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_min_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_min_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mov_b32_e64 :ref:`vdst`, :ref:`src` - v_mqsad_pk_u16_u8 :ref:`vdst`::ref:`b64`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b64` :ref:`clamp` - v_mqsad_u32_u8 :ref:`vdst`::ref:`b128`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`vsrc2`::ref:`b128` :ref:`clamp` - v_msad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` :ref:`clamp` - v_mul_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_hi_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_mul_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_lo_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_lo_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_cmp_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_t_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + 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:ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_t_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` + v_cos_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f16_i16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f16_u16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f32_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte0_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` 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v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1`::ref:`u32` + v_cvt_pk_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` + v_cvt_pkaccum_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32` + v_cvt_pknorm_i16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f16`, :ref:`src1`::ref:`m`::ref:`f16` :ref:`op_sel` + v_cvt_pknorm_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pknorm_u16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f16`, :ref:`src1`::ref:`m`::ref:`f16` :ref:`op_sel` + v_cvt_pknorm_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_div_fixup_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fixup_legacy_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_scale_f32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_div_scale_f64 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_exp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_exp_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ffbh_i32_e64 :ref:`vdst`, :ref:`src` + v_ffbh_u32_e64 :ref:`vdst`, :ref:`src` + v_ffbl_b32_e64 :ref:`vdst`, :ref:`src` + v_floor_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_legacy_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_exp_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_mant_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_interp_mov_f32_e64 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` + v_interp_p1_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` + v_interp_p1ll_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32` :ref:`high` :ref:`clamp` :ref:`omod` + v_interp_p1lv_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f16x2` :ref:`high` :ref:`clamp` :ref:`omod` + v_interp_p2_f16 :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f32` :ref:`high` :ref:`clamp` + v_interp_p2_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` + v_interp_p2_legacy_f16 :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f32` :ref:`high` :ref:`clamp` + v_ldexp_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i16` :ref:`clamp` :ref:`omod` + v_ldexp_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_lerp_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` + v_log_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_log_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_lshl_add_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_lshl_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2` + v_lshlrev_b16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_lshlrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshlrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshrrev_b16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_lshrrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshrrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_mac_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_mad_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` + v_mad_i32_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`op_sel` :ref:`clamp` + v_mad_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`clamp` + v_mad_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i64` :ref:`clamp` + v_mad_legacy_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_legacy_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` + v_mad_legacy_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` + v_mad_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` + v_mad_u32_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`op_sel` :ref:`clamp` + v_mad_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_mad_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u64` :ref:`clamp` + v_max3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_max3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_max3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_max3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_max3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_max_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_i16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mbcnt_hi_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mbcnt_lo_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_med3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_med3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_med3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_med3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_med3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_min3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_min3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_min3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_i16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mov_b32_e64 :ref:`vdst`, :ref:`src` + v_mqsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` :ref:`clamp` + v_mqsad_u32_u8 :ref:`vdst`::ref:`u32x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`vsrc2`::ref:`u32x4` :ref:`clamp` + v_msad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_mul_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_hi_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_mul_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_lo_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_lo_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` v_nop_e64 - v_not_b32_e64 :ref:`vdst`, :ref:`src` - v_or3_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_or_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_pack_b32_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`op_sel` - v_perm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_qsad_pk_u16_u8 :ref:`vdst`::ref:`b64`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b64` :ref:`clamp` - v_rcp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_readlane_b32 :ref:`sdst`, :ref:`src0`, :ref:`ssrc1` - v_rndne_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sad_hi_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_sad_u16 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_sad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` - v_sad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_sat_pk_u8_i16_e64 :ref:`vdst`::ref:`u8x4`, :ref:`src` - v_screen_partition_4se_b32_e64 :ref:`vdst`, :ref:`src` - v_sin_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sub_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_sub_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_sub_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` - v_sub_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_sub_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_sub_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_subb_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` - v_subbrev_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` - v_subrev_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_subrev_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_subrev_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_subrev_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod` - v_trunc_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_writelane_b32 :ref:`vdst`, :ref:`ssrc0`, :ref:`ssrc1` - v_xad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_xor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_not_b32_e64 :ref:`vdst`, :ref:`src` + v_or3_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_or_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_pack_b32_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`op_sel` + v_perm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_qsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` :ref:`clamp` + v_rcp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_readlane_b32 :ref:`sdst`, :ref:`src0`, :ref:`ssrc1` + v_rndne_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sad_hi_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sad_u16 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` + v_sad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sat_pk_u8_i16_e64 :ref:`vdst`::ref:`u8x4`, :ref:`src` + v_screen_partition_4se_b32_e64 :ref:`vdst`, :ref:`src` + v_sin_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_sub_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` + v_sub_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_sub_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_sub_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_subb_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_subbrev_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_subrev_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_subrev_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_subrev_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_subrev_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod` + v_trunc_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_writelane_b32 :ref:`vdst`, :ref:`ssrc0`, :ref:`ssrc1` + v_xad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_xor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` VOP3P ----------------------- diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst index 4e81f974ad73..c85163069615 100644 --- a/llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst @@ -38,21 +38,19 @@ VOP3P .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_mad_mix_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` - v_mad_mixhi_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` - v_mad_mixlo_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_mad_mix_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_mad_mixhi_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_mad_mixlo_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` .. |---| unicode:: U+02014 .. em dash - .. toctree:: :hidden: - AMDGPUAsmGFX9 - gfx900_src32_0 - gfx900_src32_1 - gfx900_vdst32_0 - gfx900_mad_type_dev - gfx900_mod_vop3_abs_neg + gfx900_fx_operand + gfx900_m + gfx900_src + gfx900_src_1 + gfx900_vdst diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst index 230d689f3a0e..8bbb4c283203 100644 --- a/llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst @@ -38,21 +38,19 @@ VOP3P .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_fma_mix_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` - v_fma_mixhi_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` - v_fma_mixlo_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_fma_mix_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_fma_mixhi_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_fma_mixlo_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` .. |---| unicode:: U+02014 .. em dash - .. toctree:: :hidden: - AMDGPUAsmGFX9 - gfx904_src32_0 - gfx904_src32_1 - gfx904_vdst32_0 - gfx904_mad_type_dev - gfx904_mod_vop3_abs_neg + gfx904_fx_operand + gfx904_m + gfx904_src + gfx904_src_1 + gfx904_vdst diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst index 7cb3c38bd356..92ca062ab975 100644 --- a/llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst @@ -38,13 +38,13 @@ VOP2 .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_fmac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_fmac_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_xnor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_xnor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_xnor_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_fmac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_fmac_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_xnor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_xnor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_xnor_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` VOP3 ----------------------- @@ -52,44 +52,41 @@ VOP3 .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_fmac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_xnor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_fmac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_xnor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` VOP3P ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_dot2_f32_f16 :ref:`vdst`, :ref:`src0`::ref:`f16x2`, :ref:`src1`::ref:`f16x2`, :ref:`src2`::ref:`f32` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` - v_dot2_i32_i16 :ref:`vdst`, :ref:`src0`::ref:`i16x2`, :ref:`src1`::ref:`i16x2`, :ref:`src2`::ref:`i32` :ref:`clamp` - v_dot2_u32_u16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_dot4_i32_i8 :ref:`vdst`, :ref:`src0`::ref:`i8x4`, :ref:`src1`::ref:`i8x4`, :ref:`src2`::ref:`i32` :ref:`clamp` - v_dot4_u32_u8 :ref:`vdst`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_dot8_i32_i4 :ref:`vdst`, :ref:`src0`::ref:`i4x8`, :ref:`src1`::ref:`i4x8`, :ref:`src2`::ref:`i32` :ref:`clamp` - v_dot8_u32_u4 :ref:`vdst`, :ref:`src0`::ref:`u4x8`, :ref:`src1`::ref:`u4x8`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_fma_mix_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` - v_fma_mixhi_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` - v_fma_mixlo_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_dot2_f32_f16 :ref:`vdst`, :ref:`src0`::ref:`f16x2`, :ref:`src1`::ref:`f16x2`, :ref:`src2`::ref:`f32` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_dot2_i32_i16 :ref:`vdst`, :ref:`src0`::ref:`i16x2`, :ref:`src1`::ref:`i16x2`, :ref:`src2`::ref:`i32` :ref:`clamp` + v_dot2_u32_u16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_dot4_i32_i8 :ref:`vdst`, :ref:`src0`::ref:`i8x4`, :ref:`src1`::ref:`i8x4`, :ref:`src2`::ref:`i32` :ref:`clamp` + v_dot4_u32_u8 :ref:`vdst`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_dot8_i32_i4 :ref:`vdst`, :ref:`src0`::ref:`i4x8`, :ref:`src1`::ref:`i4x8`, :ref:`src2`::ref:`i32` :ref:`clamp` + v_dot8_u32_u4 :ref:`vdst`, :ref:`src0`::ref:`u4x8`, :ref:`src1`::ref:`u4x8`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_fma_mix_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_fma_mixhi_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_fma_mixlo_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` .. |---| unicode:: U+02014 .. em dash - .. toctree:: :hidden: - AMDGPUAsmGFX9 - gfx906_src32_0 - gfx906_src32_1 - gfx906_src32_2 - gfx906_src32_3 - gfx906_src32_4 - gfx906_vdst32_0 - gfx906_vsrc32_0 - gfx906_mad_type_dev - gfx906_mod_dpp_sdwa_abs_neg - gfx906_mod_sdwa_sext - gfx906_mod_vop3_abs_neg - gfx906_type_dev + gfx906_fx_operand + gfx906_m + gfx906_m_1 + gfx906_src + gfx906_src_1 + gfx906_src_2 + gfx906_src_3 + gfx906_src_4 + gfx906_type_deviation + gfx906_vdst + gfx906_vsrc diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst index 979c0f2d1738..7185a2de971e 100644 --- a/llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst @@ -38,42 +38,42 @@ FLAT .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - global_atomic_add_f32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`slc` - global_atomic_pk_add_f16 :ref:`vdst`::ref:`opt`::ref:`f16x2`, :ref:`vaddr`, :ref:`vdata`::ref:`f16x2`, :ref:`saddr` :ref:`offset13s` :ref:`slc` + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + global_atomic_add_f32 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`slc` + global_atomic_pk_add_f16 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset13s` :ref:`slc` MUBUF ----------------------- .. parsed-literal:: - **INSTRUCTION** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - buffer_atomic_add_f32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`slc` - buffer_atomic_pk_add_f16 :ref:`vdata`::ref:`dst`::ref:`f16x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`slc` + **INSTRUCTION** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + buffer_atomic_add_f32 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`slc` + buffer_atomic_pk_add_f16 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`slc` VOP2 ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_dot2c_f32_f16 :ref:`vdst`, :ref:`src0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` - v_dot2c_f32_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_dot2c_i32_i16 :ref:`vdst`, :ref:`src0`::ref:`i16x2`, :ref:`vsrc1`::ref:`i16x2` - v_dot2c_i32_i16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`i16x2`, :ref:`vsrc1`::ref:`i16x2` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_dot4c_i32_i8 :ref:`vdst`, :ref:`src0`::ref:`i8x4`, :ref:`vsrc1`::ref:`i8x4` - v_dot4c_i32_i8_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`i8x4`, :ref:`vsrc1`::ref:`i8x4` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_dot8c_i32_i4 :ref:`vdst`, :ref:`src0`::ref:`i4x8`, :ref:`vsrc1`::ref:`i4x8` - v_dot8c_i32_i4_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`i4x8`, :ref:`vsrc1`::ref:`i4x8` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_fmac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_fmac_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_pk_fmac_f16 :ref:`vdst`::ref:`f16x2`, :ref:`src0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` - v_xnor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_xnor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_xnor_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_dot2c_f32_f16 :ref:`vdst`, :ref:`src0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` + v_dot2c_f32_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`f16x2`, :ref:`vsrc1`::ref:`f16x2` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_dot2c_i32_i16 :ref:`vdst`, :ref:`src0`::ref:`i16x2`, :ref:`vsrc1`::ref:`i16x2` + v_dot2c_i32_i16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`i16x2`, :ref:`vsrc1`::ref:`i16x2` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_dot4c_i32_i8 :ref:`vdst`, :ref:`src0`::ref:`i8x4`, :ref:`vsrc1`::ref:`i8x4` + v_dot4c_i32_i8_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`i8x4`, :ref:`vsrc1`::ref:`i8x4` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_dot8c_i32_i4 :ref:`vdst`, :ref:`src0`::ref:`i4x8`, :ref:`vsrc1`::ref:`i4x8` + v_dot8c_i32_i4_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`i4x8`, :ref:`vsrc1`::ref:`i4x8` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_fmac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_fmac_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_pk_fmac_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_xnor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_xnor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_xnor_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` VOP3 ----------------------- @@ -81,87 +81,84 @@ VOP3 .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_fmac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_xnor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_fmac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_xnor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` VOP3P ----------------------- .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_accvgpr_read_b32 :ref:`vdst`, :ref:`asrc` - v_accvgpr_write_b32 :ref:`adst`, :ref:`src` - v_dot2_f32_f16 :ref:`vdst`, :ref:`src0`::ref:`f16x2`, :ref:`src1`::ref:`f16x2`, :ref:`src2`::ref:`f32` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` - v_dot2_i32_i16 :ref:`vdst`, :ref:`src0`::ref:`i16x2`, :ref:`src1`::ref:`i16x2`, :ref:`src2`::ref:`i32` :ref:`clamp` - v_dot2_u32_u16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_dot4_i32_i8 :ref:`vdst`, :ref:`src0`::ref:`i8x4`, :ref:`src1`::ref:`i8x4`, :ref:`src2`::ref:`i32` :ref:`clamp` - v_dot4_u32_u8 :ref:`vdst`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_dot8_i32_i4 :ref:`vdst`, :ref:`src0`::ref:`i4x8`, :ref:`src1`::ref:`i4x8`, :ref:`src2`::ref:`i32` :ref:`clamp` - v_dot8_u32_u4 :ref:`vdst`, :ref:`src0`::ref:`u4x8`, :ref:`src1`::ref:`u4x8`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_fma_mix_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` - v_fma_mixhi_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` - v_fma_mixlo_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` - v_mfma_f32_16x16x16f16 :ref:`adst`::ref:`f32x4`, :ref:`vasrc0`::ref:`f16x4`, :ref:`vasrc1`::ref:`f16x4`, :ref:`asrc2`::ref:`f32x4` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_f32_16x16x1f32 :ref:`adst`::ref:`f32x16`, :ref:`vasrc0`::ref:`f32`, :ref:`vasrc1`::ref:`f32`, :ref:`asrc2`::ref:`f32x16` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_f32_16x16x2bf16 :ref:`adst`::ref:`f32x16`, :ref:`vasrc0`::ref:`bf16x2`, :ref:`vasrc1`::ref:`bf16x2`, :ref:`asrc2`::ref:`f32x16` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_f32_16x16x4f16 :ref:`adst`::ref:`f32x16`, :ref:`vasrc0`::ref:`f16x4`, :ref:`vasrc1`::ref:`f16x4`, :ref:`asrc2`::ref:`f32x16` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_f32_16x16x4f32 :ref:`adst`::ref:`f32x4`, :ref:`vasrc0`::ref:`f32`, :ref:`vasrc1`::ref:`f32`, :ref:`asrc2`::ref:`f32x4` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_f32_16x16x8bf16 :ref:`adst`::ref:`f32x4`, :ref:`vasrc0`::ref:`bf16x2`, :ref:`vasrc1`::ref:`bf16x2`, :ref:`asrc2`::ref:`f32x4` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_f32_32x32x1f32 :ref:`adst`::ref:`f32x32`, :ref:`vasrc0`::ref:`f32`, :ref:`vasrc1`::ref:`f32`, :ref:`asrc2`::ref:`f32x32` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_f32_32x32x2bf16 :ref:`adst`::ref:`f32x32`, :ref:`vasrc0`::ref:`bf16x2`, :ref:`vasrc1`::ref:`bf16x2`, :ref:`asrc2`::ref:`f32x32` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_f32_32x32x2f32 :ref:`adst`::ref:`f32x16`, :ref:`vasrc0`::ref:`f32`, :ref:`vasrc1`::ref:`f32`, :ref:`asrc2`::ref:`f32x16` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_f32_32x32x4bf16 :ref:`adst`::ref:`f32x16`, :ref:`vasrc0`::ref:`bf16x2`, :ref:`vasrc1`::ref:`bf16x2`, :ref:`asrc2`::ref:`f32x16` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_f32_32x32x4f16 :ref:`adst`::ref:`f32x32`, :ref:`vasrc0`::ref:`f16x4`, :ref:`vasrc1`::ref:`f16x4`, :ref:`asrc2`::ref:`f32x32` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_f32_32x32x8f16 :ref:`adst`::ref:`f32x16`, :ref:`vasrc0`::ref:`f16x4`, :ref:`vasrc1`::ref:`f16x4`, :ref:`asrc2`::ref:`f32x16` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_f32_4x4x1f32 :ref:`adst`::ref:`f32x4`, :ref:`vasrc0`::ref:`f32`, :ref:`vasrc1`::ref:`f32`, :ref:`asrc2`::ref:`f32x4` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_f32_4x4x2bf16 :ref:`adst`::ref:`f32x4`, :ref:`vasrc0`::ref:`bf16x2`, :ref:`vasrc1`::ref:`bf16x2`, :ref:`asrc2`::ref:`f32x4` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_f32_4x4x4f16 :ref:`adst`::ref:`f32x4`, :ref:`vasrc0`::ref:`f16x4`, :ref:`vasrc1`::ref:`f16x4`, :ref:`asrc2`::ref:`f32x4` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_i32_16x16x16i8 :ref:`adst`::ref:`i32x4`, :ref:`vasrc0`::ref:`i8x4`, :ref:`vasrc1`::ref:`i8x4`, :ref:`asrc2`::ref:`i32x4` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_i32_16x16x4i8 :ref:`adst`::ref:`i32x16`, :ref:`vasrc0`::ref:`i8x4`, :ref:`vasrc1`::ref:`i8x4`, :ref:`asrc2`::ref:`i32x16` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_i32_32x32x4i8 :ref:`adst`::ref:`i32x32`, :ref:`vasrc0`::ref:`i8x4`, :ref:`vasrc1`::ref:`i8x4`, :ref:`asrc2`::ref:`i32x32` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_i32_32x32x8i8 :ref:`adst`::ref:`i32x16`, :ref:`vasrc0`::ref:`i8x4`, :ref:`vasrc1`::ref:`i8x4`, :ref:`asrc2`::ref:`i32x16` :ref:`cbsz` :ref:`abid` :ref:`blgp` - v_mfma_i32_4x4x4i8 :ref:`adst`::ref:`i32x4`, :ref:`vasrc0`::ref:`i8x4`, :ref:`vasrc1`::ref:`i8x4`, :ref:`asrc2`::ref:`i32x4` :ref:`cbsz` :ref:`abid` :ref:`blgp` + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_accvgpr_read_b32 :ref:`vdst`, :ref:`vsrc` + v_accvgpr_write_b32 :ref:`vdst`, :ref:`src` + v_dot2_f32_f16 :ref:`vdst`, :ref:`src0`::ref:`f16x2`, :ref:`src1`::ref:`f16x2`, :ref:`src2`::ref:`f32` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_dot2_i32_i16 :ref:`vdst`, :ref:`src0`::ref:`i16x2`, :ref:`src1`::ref:`i16x2`, :ref:`src2`::ref:`i32` :ref:`clamp` + v_dot2_u32_u16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_dot4_i32_i8 :ref:`vdst`, :ref:`src0`::ref:`i8x4`, :ref:`src1`::ref:`i8x4`, :ref:`src2`::ref:`i32` :ref:`clamp` + v_dot4_u32_u8 :ref:`vdst`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_dot8_i32_i4 :ref:`vdst`, :ref:`src0`::ref:`i4x8`, :ref:`src1`::ref:`i4x8`, :ref:`src2`::ref:`i32` :ref:`clamp` + v_dot8_u32_u4 :ref:`vdst`, :ref:`src0`::ref:`u4x8`, :ref:`src1`::ref:`u4x8`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_fma_mix_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_fma_mixhi_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_fma_mixlo_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_mfma_f32_16x16x16f16 :ref:`vdst`::ref:`f32x4`, :ref:`vsrc0`::ref:`f16x4`, :ref:`vsrc1`::ref:`f16x4`, :ref:`vsrc2`::ref:`f32x4` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_f32_16x16x1f32 :ref:`vdst`::ref:`f32x16`, :ref:`vsrc0`::ref:`f32`, :ref:`vsrc1`::ref:`f32`, :ref:`vsrc2`::ref:`f32x16` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_f32_16x16x2bf16 :ref:`vdst`::ref:`f32x16`, :ref:`vsrc0`::ref:`bf16x2`, :ref:`vsrc1`::ref:`bf16x2`, :ref:`vsrc2`::ref:`f32x16` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_f32_16x16x4f16 :ref:`vdst`::ref:`f32x16`, :ref:`vsrc0`::ref:`f16x4`, :ref:`vsrc1`::ref:`f16x4`, :ref:`vsrc2`::ref:`f32x16` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_f32_16x16x4f32 :ref:`vdst`::ref:`f32x4`, :ref:`vsrc0`::ref:`f32`, :ref:`vsrc1`::ref:`f32`, :ref:`vsrc2`::ref:`f32x4` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_f32_16x16x8bf16 :ref:`vdst`::ref:`f32x4`, :ref:`vsrc0`::ref:`bf16x2`, :ref:`vsrc1`::ref:`bf16x2`, :ref:`vsrc2`::ref:`f32x4` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_f32_32x32x1f32 :ref:`vdst`::ref:`f32x32`, :ref:`vsrc0`::ref:`f32`, :ref:`vsrc1`::ref:`f32`, :ref:`vsrc2`::ref:`f32x32` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_f32_32x32x2bf16 :ref:`vdst`::ref:`f32x32`, :ref:`vsrc0`::ref:`bf16x2`, :ref:`vsrc1`::ref:`bf16x2`, :ref:`vsrc2`::ref:`f32x32` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_f32_32x32x2f32 :ref:`vdst`::ref:`f32x16`, :ref:`vsrc0`::ref:`f32`, :ref:`vsrc1`::ref:`f32`, :ref:`vsrc2`::ref:`f32x16` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_f32_32x32x4bf16 :ref:`vdst`::ref:`f32x16`, :ref:`vsrc0`::ref:`bf16x2`, :ref:`vsrc1`::ref:`bf16x2`, :ref:`vsrc2`::ref:`f32x16` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_f32_32x32x4f16 :ref:`vdst`::ref:`f32x32`, :ref:`vsrc0`::ref:`f16x4`, :ref:`vsrc1`::ref:`f16x4`, :ref:`vsrc2`::ref:`f32x32` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_f32_32x32x8f16 :ref:`vdst`::ref:`f32x16`, :ref:`vsrc0`::ref:`f16x4`, :ref:`vsrc1`::ref:`f16x4`, :ref:`vsrc2`::ref:`f32x16` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_f32_4x4x1f32 :ref:`vdst`::ref:`f32x4`, :ref:`vsrc0`::ref:`f32`, :ref:`vsrc1`::ref:`f32`, :ref:`vsrc2`::ref:`f32x4` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_f32_4x4x2bf16 :ref:`vdst`::ref:`f32x4`, :ref:`vsrc0`::ref:`bf16x2`, :ref:`vsrc1`::ref:`bf16x2`, :ref:`vsrc2`::ref:`f32x4` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_f32_4x4x4f16 :ref:`vdst`::ref:`f32x4`, :ref:`vsrc0`::ref:`f16x4`, :ref:`vsrc1`::ref:`f16x4`, :ref:`vsrc2`::ref:`f32x4` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_i32_16x16x16i8 :ref:`vdst`::ref:`i32x4`, :ref:`vsrc0`::ref:`i8x4`, :ref:`vsrc1`::ref:`i8x4`, :ref:`vsrc2`::ref:`i32x4` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_i32_16x16x4i8 :ref:`vdst`::ref:`i32x16`, :ref:`vsrc0`::ref:`i8x4`, :ref:`vsrc1`::ref:`i8x4`, :ref:`vsrc2`::ref:`i32x16` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_i32_32x32x4i8 :ref:`vdst`::ref:`i32x32`, :ref:`vsrc0`::ref:`i8x4`, :ref:`vsrc1`::ref:`i8x4`, :ref:`vsrc2`::ref:`i32x32` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_i32_32x32x8i8 :ref:`vdst`::ref:`i32x16`, :ref:`vsrc0`::ref:`i8x4`, :ref:`vsrc1`::ref:`i8x4`, :ref:`vsrc2`::ref:`i32x16` :ref:`cbsz` :ref:`abid` :ref:`blgp` + v_mfma_i32_4x4x4i8 :ref:`vdst`::ref:`i32x4`, :ref:`vsrc0`::ref:`i8x4`, :ref:`vsrc1`::ref:`i8x4`, :ref:`vsrc2`::ref:`i32x4` :ref:`cbsz` :ref:`abid` :ref:`blgp` .. |---| unicode:: U+02014 .. em dash - .. toctree:: :hidden: - AMDGPUAsmGFX9 - gfx908_addr_buf - gfx908_adst1024_0 - gfx908_adst128_0 - gfx908_adst32_0 - gfx908_adst512_0 - gfx908_asrc1024_0 - gfx908_asrc128_0 - gfx908_asrc32_0 - gfx908_asrc512_0 - gfx908_data_buf_atomic32 - gfx908_dst_flat_atomic32 - gfx908_offset_buf - gfx908_rsrc_buf - gfx908_saddr_flat_global - gfx908_src32_0 - gfx908_src32_1 - gfx908_src32_2 - gfx908_src32_3 - gfx908_src32_4 - gfx908_src32_5 - gfx908_vaddr_flat_global - gfx908_vasrc32_0 - gfx908_vasrc64_0 - gfx908_vdata32_0 - gfx908_vdst32_0 - gfx908_vsrc32_0 - gfx908_mad_type_dev - gfx908_mod_dpp_sdwa_abs_neg - gfx908_mod_sdwa_sext - gfx908_mod_vop3_abs_neg + gfx908_dst + gfx908_fx_operand + gfx908_m + gfx908_m_1 gfx908_opt - gfx908_ret - gfx908_type_dev + gfx908_saddr + gfx908_soffset + gfx908_src + gfx908_src_1 + gfx908_src_2 + gfx908_src_3 + gfx908_src_4 + gfx908_src_5 + gfx908_srsrc + gfx908_type_deviation + gfx908_vaddr + gfx908_vaddr_1 + gfx908_vdata + gfx908_vdata_1 + gfx908_vdst + gfx908_vdst_1 + gfx908_vdst_2 + gfx908_vdst_3 + gfx908_vdst_4 + gfx908_vdst_5 + gfx908_vsrc + gfx908_vsrc_1 + gfx908_vsrc_2 + gfx908_vsrc_3 + gfx908_vsrc_4 + gfx908_vsrc_5 + gfx908_vsrc_6 diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX90a.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX90a.rst index 14fb9a46b744..6c1ac12e6a39 100644 --- a/llvm/docs/AMDGPU/AMDGPUAsmGFX90a.rst +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX90a.rst @@ -38,130 +38,130 @@ DS **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - ds_add_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_add_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_and_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_append :ref:`vdst` :ref:`offset16` :ref:`gds` - ds_bpermute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` - ds_cmpst_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_f32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_f64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_cmpst_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_condxchg32_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_consume :ref:`vdst` :ref:`offset16` :ref:`gds` - ds_dec_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_dec_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_dec_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_dec_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_barrier :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_init :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_sema_br :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_gws_sema_p :ref:`offset16` :ref:`gds` - ds_gws_sema_release_all :ref:`offset16` :ref:`gds` - ds_gws_sema_v :ref:`offset16` :ref:`gds` - ds_inc_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_inc_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_inc_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_inc_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_max_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_min_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_mskor_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_mskor_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_mskor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_mskor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` + ds_add_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_append :ref:`vdst` :ref:`offset` :ref:`gds` + ds_bpermute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` + ds_cmpst_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_f32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_f64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_condxchg32_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_consume :ref:`vdst` :ref:`offset` :ref:`gds` + ds_dec_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_barrier :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_init :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_sema_br :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_sema_p :ref:`offset` :ref:`gds` + ds_gws_sema_release_all :ref:`offset` :ref:`gds` + ds_gws_sema_v :ref:`offset` :ref:`gds` + ds_inc_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_mskor_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` ds_nop - ds_or_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_or_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_permute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` - ds_read2_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read2_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read2st64_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read2st64_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_read_addtid_b32 :ref:`vdst` :ref:`offset16` :ref:`gds` - ds_read_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_i8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_i8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u16_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u16_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_read_u8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset16` :ref:`gds` - ds_rsub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_rsub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_rsub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_rsub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_sub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` + ds_or_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_permute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` + ds_read2_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2st64_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2st64_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read_addtid_b32 :ref:`vdst` :ref:`offset` :ref:`gds` + ds_read_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` ds_swizzle_b32 :ref:`vdst`, :ref:`vaddr` :ref:`pattern` :ref:`gds` - ds_wrap_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset16` :ref:`gds` - ds_write2_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write2_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write2st64_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write2st64_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_write_addtid_b32 :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b16_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b8_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_write_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_wrxchg2_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg2_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg2st64_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg2st64_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset8` :ref:`offset8` :ref:`gds` - ds_wrxchg_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_wrxchg_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` - ds_xor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset16` :ref:`gds` + ds_wrap_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_write2_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2st64_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2st64_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write_addtid_b32 :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b16_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b8_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_wrxchg2_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2st64_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2st64_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_wrxchg_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` FLAT ----------------------- @@ -754,212 +754,212 @@ VOP1 .. parsed-literal:: - **INSTRUCTION** **DST** **SRC** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_accvgpr_mov_b32 :ref:`vdst`, :ref:`vsrc` - v_bfrev_b32 :ref:`vdst`, :ref:`src` - v_bfrev_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_bfrev_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ceil_f16 :ref:`vdst`, :ref:`src` - v_ceil_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ceil_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ceil_f32 :ref:`vdst`, :ref:`src` - v_ceil_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ceil_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ceil_f64 :ref:`vdst`, :ref:`src` - v_ceil_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + **INSTRUCTION** **DST** **SRC** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + v_accvgpr_mov_b32 :ref:`vdst`, :ref:`vsrc` + v_bfrev_b32 :ref:`vdst`, :ref:`src` + v_bfrev_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_bfrev_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ceil_f16 :ref:`vdst`, :ref:`src` + v_ceil_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_ceil_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ceil_f32 :ref:`vdst`, :ref:`src` + v_ceil_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_ceil_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ceil_f64 :ref:`vdst`, :ref:`src` + v_ceil_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_clrexcp - v_cos_f16 :ref:`vdst`, :ref:`src` - v_cos_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cos_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cos_f32 :ref:`vdst`, :ref:`src` - v_cos_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cos_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f16_f32 :ref:`vdst`, :ref:`src` - v_cvt_f16_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f16_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f16_i16 :ref:`vdst`, :ref:`src` - v_cvt_f16_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f16_i16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f16_u16 :ref:`vdst`, :ref:`src` - v_cvt_f16_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f16_u16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_f16 :ref:`vdst`, :ref:`src` - v_cvt_f32_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_f64 :ref:`vdst`, :ref:`src` - v_cvt_f32_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_i32 :ref:`vdst`, :ref:`src` - v_cvt_f32_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_i32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_u32 :ref:`vdst`, :ref:`src` - v_cvt_f32_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_u32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_ubyte0 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte0_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_ubyte0_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_ubyte1 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte1_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_ubyte1_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_ubyte2 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte2_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_ubyte2_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_ubyte3 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte3_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_ubyte3_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f64_f32 :ref:`vdst`, :ref:`src` - v_cvt_f64_i32 :ref:`vdst`, :ref:`src` - v_cvt_f64_u32 :ref:`vdst`, :ref:`src` - v_cvt_flr_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_flr_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_flr_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_i16_f16 :ref:`vdst`, :ref:`src` - v_cvt_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_i32_f64 :ref:`vdst`, :ref:`src` - v_cvt_i32_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_norm_i16_f16 :ref:`vdst`, :ref:`src` - v_cvt_norm_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_norm_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_norm_u16_f16 :ref:`vdst`, :ref:`src` - v_cvt_norm_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_norm_u16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_off_f32_i4 :ref:`vdst`, :ref:`src` - v_cvt_off_f32_i4_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_off_f32_i4_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_rpi_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_rpi_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_rpi_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_u16_f16 :ref:`vdst`, :ref:`src` - v_cvt_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_u16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_u32_f32 :ref:`vdst`, :ref:`src` - v_cvt_u32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_u32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_u32_f64 :ref:`vdst`, :ref:`src` - v_cvt_u32_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_exp_f16 :ref:`vdst`, :ref:`src` - v_exp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_exp_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_exp_f32 :ref:`vdst`, :ref:`src` - v_exp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_exp_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_exp_legacy_f32 :ref:`vdst`, :ref:`src` - v_exp_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_exp_legacy_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ffbh_i32 :ref:`vdst`, :ref:`src` - v_ffbh_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ffbh_i32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ffbh_u32 :ref:`vdst`, :ref:`src` - v_ffbh_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ffbh_u32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ffbl_b32 :ref:`vdst`, :ref:`src` - v_ffbl_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ffbl_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_floor_f16 :ref:`vdst`, :ref:`src` - v_floor_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_floor_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_floor_f32 :ref:`vdst`, :ref:`src` - v_floor_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_floor_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_floor_f64 :ref:`vdst`, :ref:`src` - v_floor_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_fract_f16 :ref:`vdst`, :ref:`src` - v_fract_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_fract_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_fract_f32 :ref:`vdst`, :ref:`src` - v_fract_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_fract_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_fract_f64 :ref:`vdst`, :ref:`src` - v_fract_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_frexp_exp_i16_f16 :ref:`vdst`, :ref:`src` - v_frexp_exp_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_frexp_exp_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_frexp_exp_i32_f32 :ref:`vdst`, :ref:`src` - v_frexp_exp_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_frexp_exp_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_frexp_exp_i32_f64 :ref:`vdst`, :ref:`src` - v_frexp_exp_i32_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_frexp_mant_f16 :ref:`vdst`, :ref:`src` - v_frexp_mant_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_frexp_mant_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_frexp_mant_f32 :ref:`vdst`, :ref:`src` - v_frexp_mant_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_frexp_mant_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_frexp_mant_f64 :ref:`vdst`, :ref:`src` - v_frexp_mant_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_log_f16 :ref:`vdst`, :ref:`src` - v_log_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_log_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_log_f32 :ref:`vdst`, :ref:`src` - v_log_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_log_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_log_legacy_f32 :ref:`vdst`, :ref:`src` - v_log_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_log_legacy_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_mov_b32 :ref:`vdst`, :ref:`src` - v_mov_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mov_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cos_f16 :ref:`vdst`, :ref:`src` + v_cos_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cos_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cos_f32 :ref:`vdst`, :ref:`src` + v_cos_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cos_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f16_f32 :ref:`vdst`, :ref:`src` + v_cvt_f16_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f16_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f16_i16 :ref:`vdst`, :ref:`src` + v_cvt_f16_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f16_i16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f16_u16 :ref:`vdst`, :ref:`src` + v_cvt_f16_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f16_u16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_f16 :ref:`vdst`, :ref:`src` + v_cvt_f32_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f32_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_f64 :ref:`vdst`, :ref:`src` + v_cvt_f32_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f32_i32 :ref:`vdst`, :ref:`src` + v_cvt_f32_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f32_i32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_u32 :ref:`vdst`, :ref:`src` + v_cvt_f32_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f32_u32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte0 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte0_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f32_ubyte0_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte1 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte1_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f32_ubyte1_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte2 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte2_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f32_ubyte2_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte3 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte3_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f32_ubyte3_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f64_f32 :ref:`vdst`, :ref:`src` + v_cvt_f64_i32 :ref:`vdst`, :ref:`src` + v_cvt_f64_u32 :ref:`vdst`, :ref:`src` + v_cvt_flr_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_flr_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_flr_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_i16_f16 :ref:`vdst`, :ref:`src` + v_cvt_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_i32_f64 :ref:`vdst`, :ref:`src` + v_cvt_i32_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_norm_i16_f16 :ref:`vdst`, :ref:`src` + v_cvt_norm_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_norm_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_norm_u16_f16 :ref:`vdst`, :ref:`src` + v_cvt_norm_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_norm_u16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_off_f32_i4 :ref:`vdst`, :ref:`src` + v_cvt_off_f32_i4_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_off_f32_i4_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_rpi_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_rpi_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_rpi_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_u16_f16 :ref:`vdst`, :ref:`src` + v_cvt_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_u16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_u32_f32 :ref:`vdst`, :ref:`src` + v_cvt_u32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_u32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_u32_f64 :ref:`vdst`, :ref:`src` + v_cvt_u32_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_exp_f16 :ref:`vdst`, :ref:`src` + v_exp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_exp_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_exp_f32 :ref:`vdst`, :ref:`src` + v_exp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_exp_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_exp_legacy_f32 :ref:`vdst`, :ref:`src` + v_exp_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_exp_legacy_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ffbh_i32 :ref:`vdst`, :ref:`src` + v_ffbh_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_ffbh_i32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ffbh_u32 :ref:`vdst`, :ref:`src` + v_ffbh_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_ffbh_u32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ffbl_b32 :ref:`vdst`, :ref:`src` + v_ffbl_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_ffbl_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_floor_f16 :ref:`vdst`, :ref:`src` + v_floor_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_floor_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_floor_f32 :ref:`vdst`, :ref:`src` + v_floor_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_floor_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_floor_f64 :ref:`vdst`, :ref:`src` + v_floor_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_fract_f16 :ref:`vdst`, :ref:`src` + v_fract_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_fract_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_fract_f32 :ref:`vdst`, :ref:`src` + v_fract_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_fract_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_fract_f64 :ref:`vdst`, :ref:`src` + v_fract_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_frexp_exp_i16_f16 :ref:`vdst`, :ref:`src` + v_frexp_exp_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_frexp_exp_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_exp_i32_f32 :ref:`vdst`, :ref:`src` + v_frexp_exp_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_frexp_exp_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_exp_i32_f64 :ref:`vdst`, :ref:`src` + v_frexp_exp_i32_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_frexp_mant_f16 :ref:`vdst`, :ref:`src` + v_frexp_mant_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_frexp_mant_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_mant_f32 :ref:`vdst`, :ref:`src` + v_frexp_mant_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_frexp_mant_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_mant_f64 :ref:`vdst`, :ref:`src` + v_frexp_mant_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_log_f16 :ref:`vdst`, :ref:`src` + v_log_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_log_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_log_f32 :ref:`vdst`, :ref:`src` + v_log_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_log_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_log_legacy_f32 :ref:`vdst`, :ref:`src` + v_log_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_log_legacy_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_mov_b32 :ref:`vdst`, :ref:`src` + v_mov_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_mov_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_nop - v_not_b32 :ref:`vdst`, :ref:`src` - v_not_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_not_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rcp_f16 :ref:`vdst`, :ref:`src` - v_rcp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rcp_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rcp_f32 :ref:`vdst`, :ref:`src` - v_rcp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rcp_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rcp_f64 :ref:`vdst`, :ref:`src` - v_rcp_iflag_f32 :ref:`vdst`, :ref:`src` - v_rcp_iflag_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rcp_iflag_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_readfirstlane_b32 :ref:`sdst`, :ref:`vsrc` - v_rndne_f16 :ref:`vdst`, :ref:`src` - v_rndne_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rndne_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rndne_f32 :ref:`vdst`, :ref:`src` - v_rndne_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rndne_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rndne_f64 :ref:`vdst`, :ref:`src` - v_rsq_f16 :ref:`vdst`, :ref:`src` - v_rsq_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rsq_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rsq_f32 :ref:`vdst`, :ref:`src` - v_rsq_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rsq_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rsq_f64 :ref:`vdst`, :ref:`src` - v_sat_pk_u8_i16 :ref:`vdst`, :ref:`src` - v_sat_pk_u8_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sat_pk_u8_i16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_screen_partition_4se_b32 :ref:`vdst`, :ref:`src` - v_screen_partition_4se_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_screen_partition_4se_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sin_f16 :ref:`vdst`, :ref:`src` - v_sin_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sin_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sin_f32 :ref:`vdst`, :ref:`src` - v_sin_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sin_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sqrt_f16 :ref:`vdst`, :ref:`src` - v_sqrt_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sqrt_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sqrt_f32 :ref:`vdst`, :ref:`src` - v_sqrt_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sqrt_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sqrt_f64 :ref:`vdst`, :ref:`src` - v_swap_b32 :ref:`vdst`, :ref:`vsrc` - v_trunc_f16 :ref:`vdst`, :ref:`src` - v_trunc_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_trunc_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_trunc_f32 :ref:`vdst`, :ref:`src` - v_trunc_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_trunc_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_trunc_f64 :ref:`vdst`, :ref:`src` - v_trunc_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_not_b32 :ref:`vdst`, :ref:`src` + v_not_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_not_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rcp_f16 :ref:`vdst`, :ref:`src` + v_rcp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rcp_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rcp_f32 :ref:`vdst`, :ref:`src` + v_rcp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rcp_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rcp_f64 :ref:`vdst`, :ref:`src` + v_rcp_iflag_f32 :ref:`vdst`, :ref:`src` + v_rcp_iflag_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rcp_iflag_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_readfirstlane_b32 :ref:`sdst`, :ref:`vsrc` + v_rndne_f16 :ref:`vdst`, :ref:`src` + v_rndne_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rndne_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rndne_f32 :ref:`vdst`, :ref:`src` + v_rndne_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rndne_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rndne_f64 :ref:`vdst`, :ref:`src` + v_rsq_f16 :ref:`vdst`, :ref:`src` + v_rsq_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rsq_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rsq_f32 :ref:`vdst`, :ref:`src` + v_rsq_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rsq_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rsq_f64 :ref:`vdst`, :ref:`src` + v_sat_pk_u8_i16 :ref:`vdst`::ref:`u8x4`, :ref:`src` + v_sat_pk_u8_i16_dpp :ref:`vdst`::ref:`u8x4`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sat_pk_u8_i16_sdwa :ref:`vdst`::ref:`u8x4`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_screen_partition_4se_b32 :ref:`vdst`, :ref:`src` + v_screen_partition_4se_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_screen_partition_4se_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sin_f16 :ref:`vdst`, :ref:`src` + v_sin_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sin_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sin_f32 :ref:`vdst`, :ref:`src` + v_sin_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sin_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sqrt_f16 :ref:`vdst`, :ref:`src` + v_sqrt_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sqrt_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sqrt_f32 :ref:`vdst`, :ref:`src` + v_sqrt_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sqrt_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sqrt_f64 :ref:`vdst`, :ref:`src` + v_swap_b32 :ref:`vdst`, :ref:`vsrc` + v_trunc_f16 :ref:`vdst`, :ref:`src` + v_trunc_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_trunc_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_trunc_f32 :ref:`vdst`, :ref:`src` + v_trunc_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_trunc_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_trunc_f64 :ref:`vdst`, :ref:`src` + v_trunc_f64_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` VOP2 ----------------------- @@ -973,7 +973,7 @@ VOP2 v_add_co_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_add_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_add_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_add_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_add_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_add_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_add_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` @@ -1012,7 +1012,7 @@ VOP2 v_fmac_f64_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp64_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_ldexp_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`i16` v_ldexp_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`i16` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ldexp_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`i16` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_ldexp_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`i16` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_lshlrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`vsrc1` v_lshlrev_b16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u16`, :ref:`vsrc1` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_lshlrev_b16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`u16`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` @@ -1035,7 +1035,7 @@ VOP2 v_madmk_f32 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` v_max_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_max_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_max_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_max_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_max_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_max_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` @@ -1053,7 +1053,7 @@ VOP2 v_max_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_min_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_min_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_min_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_min_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_min_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_min_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` @@ -1071,7 +1071,7 @@ VOP2 v_min_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_mul_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_mul_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_mul_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_mul_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` @@ -1099,7 +1099,7 @@ VOP2 v_sub_co_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_sub_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_sub_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sub_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_sub_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_sub_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_sub_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_sub_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` @@ -1120,7 +1120,7 @@ VOP2 v_subrev_co_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_subrev_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_subrev_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_subrev_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_subrev_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_subrev_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp32_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` v_subrev_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` @@ -1142,439 +1142,439 @@ VOP3 .. parsed-literal:: - **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** + **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_add_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_add_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_add_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` - v_add_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_add_lshl_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_add_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_add_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_addc_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` - v_alignbit_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_alignbyte_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_and_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_and_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_ashrrev_i16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` - v_ashrrev_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_ashrrev_i64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_bcnt_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_bfe_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` - v_bfe_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_bfi_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_bfm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_bfrev_b32_e64 :ref:`vdst`, :ref:`src` - v_ceil_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_add3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_add_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_add_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` + v_add_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_add_lshl_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_add_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_add_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_addc_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_alignbit_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`b16` + v_alignbyte_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`b16` + v_and_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_and_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_ashrrev_i16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_ashrrev_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_ashrrev_i64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_bcnt_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_bfe_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` + v_bfe_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_bfi_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_bfm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_bfrev_b32_e64 :ref:`vdst`, :ref:`src` + v_ceil_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` v_clrexcp_e64 - v_cmp_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_f_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ge_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_gt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_le_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_t_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_f_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ge_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_gt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_le_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_t_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` - v_cos_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f16_i16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` - v_cvt_f16_u16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` - v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f32_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte0_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte1_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte2_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte3_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f64_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f64_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f64_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_flr_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_norm_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_norm_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_off_f32_i4_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_pk_i16_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_cvt_pk_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` - v_cvt_pkaccum_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` - v_cvt_pknorm_i16_f16 :ref:`vdst`::ref:`i16x2`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`op_sel` - v_cvt_pknorm_i16_f32 :ref:`vdst`::ref:`i16x2`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cvt_pknorm_u16_f16 :ref:`vdst`::ref:`u16x2`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`op_sel` - v_cvt_pknorm_u16_f32 :ref:`vdst`::ref:`u16x2`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_div_fixup_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fixup_legacy_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` - v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_scale_f32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_div_scale_f64 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_exp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_exp_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ffbh_i32_e64 :ref:`vdst`, :ref:`src` - v_ffbh_u32_e64 :ref:`vdst`, :ref:`src` - v_ffbl_b32_e64 :ref:`vdst`, :ref:`src` - v_floor_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_legacy_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` - v_fmac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_fmac_f64_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_fract_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_frexp_exp_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_mant_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ldexp_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i16` :ref:`clamp` - v_ldexp_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` - v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` - v_lerp_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` - v_log_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_log_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_lshl_add_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_lshl_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2` - v_lshlrev_b16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` - v_lshlrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_lshlrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_lshrrev_b16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` - v_lshrrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_lshrrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_mac_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_mac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_mad_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` - v_mad_i32_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`op_sel` :ref:`clamp` - v_mad_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`clamp` - v_mad_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i64` :ref:`clamp` - v_mad_legacy_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` - v_mad_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_legacy_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` - v_mad_legacy_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` - v_mad_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` - v_mad_u32_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`op_sel` :ref:`clamp` - v_mad_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_mad_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u64` :ref:`clamp` - v_max3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_max3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_max3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_max3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_max3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_max_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_i16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_max_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_max_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_max_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mbcnt_hi_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mbcnt_lo_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_med3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_med3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_med3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_med3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_med3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_min3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_min3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_min3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_i16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_min_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_min_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_min_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mov_b32_e64 :ref:`vdst`, :ref:`src` - v_mqsad_pk_u16_u8 :ref:`vdst`::ref:`b64`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b64` :ref:`clamp` - v_mqsad_u32_u8 :ref:`vdst`::ref:`b128`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`vsrc2`::ref:`b128` :ref:`clamp` - v_msad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` :ref:`clamp` - v_mul_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_hi_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_mul_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_lo_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_lo_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_cmp_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u32_e64 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:ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_t_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` + v_cos_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f16_i16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f16_u16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f32_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte0_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte1_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte2_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte3_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f64_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f64_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f64_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_flr_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_norm_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_norm_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_off_f32_i4_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_pk_i16_i32 :ref:`vdst`, :ref:`src0`::ref:`i32`, :ref:`src1`::ref:`i32` + v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1`::ref:`u32` + v_cvt_pk_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` + v_cvt_pkaccum_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32` + v_cvt_pknorm_i16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f16`, :ref:`src1`::ref:`m`::ref:`f16` :ref:`op_sel` + v_cvt_pknorm_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pknorm_u16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f16`, :ref:`src1`::ref:`m`::ref:`f16` :ref:`op_sel` + v_cvt_pknorm_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_div_fixup_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fixup_legacy_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_scale_f32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_div_scale_f64 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_exp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_exp_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ffbh_i32_e64 :ref:`vdst`, :ref:`src` + v_ffbh_u32_e64 :ref:`vdst`, :ref:`src` + v_ffbl_b32_e64 :ref:`vdst`, :ref:`src` + v_floor_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_legacy_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fmac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_fmac_f64_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_exp_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_mant_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ldexp_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i16` :ref:`clamp` :ref:`omod` + v_ldexp_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_lerp_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` + v_log_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_log_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_lshl_add_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_lshl_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2` + v_lshlrev_b16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_lshlrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshlrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshrrev_b16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_lshrrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshrrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_mac_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_mad_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` + v_mad_i32_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`op_sel` :ref:`clamp` + v_mad_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`clamp` + v_mad_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i64` :ref:`clamp` + v_mad_legacy_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_legacy_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` + v_mad_legacy_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` + v_mad_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` + v_mad_u32_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`op_sel` :ref:`clamp` + v_mad_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_mad_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u64` :ref:`clamp` + v_max3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_max3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_max3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_max3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_max3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_max_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_i16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mbcnt_hi_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mbcnt_lo_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_med3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_med3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_med3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_med3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_med3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_min3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_min3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_min3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_i16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mov_b32_e64 :ref:`vdst`, :ref:`src` + v_mqsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` :ref:`clamp` + v_mqsad_u32_u8 :ref:`vdst`::ref:`u32x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`vsrc2`::ref:`u32x4` :ref:`clamp` + v_msad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_mul_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_hi_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_mul_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_lo_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_lo_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` v_nop_e64 - v_not_b32_e64 :ref:`vdst`, :ref:`src` - v_or3_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_or_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_pack_b32_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`op_sel` - v_perm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_qsad_pk_u16_u8 :ref:`vdst`::ref:`b64`, :ref:`src0`::ref:`b64`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b64` :ref:`clamp` - v_rcp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_readlane_b32 :ref:`sdst`, :ref:`vsrc0`, :ref:`ssrc1` - v_rndne_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sad_hi_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_sad_u16 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_sad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` - v_sad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_sat_pk_u8_i16_e64 :ref:`vdst`, :ref:`src` - v_screen_partition_4se_b32_e64 :ref:`vdst`, :ref:`src` - v_sin_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sub_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_sub_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_sub_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` - v_sub_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_sub_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_sub_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_subb_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` - v_subbrev_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` - v_subrev_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_subrev_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_subrev_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_subrev_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod` - v_trunc_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_writelane_b32 :ref:`vdst`, :ref:`ssrc0`, :ref:`ssrc1` - v_xad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_xnor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_xor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_not_b32_e64 :ref:`vdst`, :ref:`src` + v_or3_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_or_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_pack_b32_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`op_sel` + v_perm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_qsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` :ref:`clamp` + v_rcp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_readlane_b32 :ref:`sdst`, :ref:`vsrc0`, :ref:`ssrc1` + v_rndne_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sad_hi_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sad_u16 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` + v_sad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sat_pk_u8_i16_e64 :ref:`vdst`::ref:`u8x4`, :ref:`src` + v_screen_partition_4se_b32_e64 :ref:`vdst`, :ref:`src` + v_sin_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_sub_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` + v_sub_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_sub_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_sub_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_subb_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_subbrev_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_subrev_co_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_subrev_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_subrev_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_subrev_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod` + v_trunc_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_writelane_b32 :ref:`vdst`, :ref:`ssrc0`, :ref:`ssrc1` + v_xad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_xnor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_xor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` VOP3P ----------------------- @@ -1623,12 +1623,12 @@ VOP3P v_mfma_i32_32x32x8i8 :ref:`vdst`::ref:`i32x16`, :ref:`vsrc0`::ref:`i8x4`, :ref:`vsrc1`::ref:`i8x4`, :ref:`src2`::ref:`i32x16` :ref:`cbsz` :ref:`abid` :ref:`blgp` v_mfma_i32_4x4x4i8 :ref:`vdst`::ref:`i32x4`, :ref:`vsrc0`::ref:`i8x4`, :ref:`vsrc1`::ref:`i8x4`, :ref:`src2`::ref:`i32x4` :ref:`cbsz` :ref:`abid` :ref:`blgp` v_pk_add_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` - v_pk_add_f32 :ref:`vdst`::ref:`f32x2`, :ref:`src0`::ref:`f32x2`, :ref:`src1`::ref:`f32x2` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` v_pk_add_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` v_pk_add_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` v_pk_ashrrev_i16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` v_pk_fma_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` - v_pk_fma_f32 :ref:`vdst`::ref:`f32x2`, :ref:`src0`::ref:`f32x2`, :ref:`src1`::ref:`f32x2`, :ref:`src2`::ref:`f32x2` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_fma_f32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` v_pk_lshlrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` v_pk_lshrrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` v_pk_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` @@ -1639,9 +1639,9 @@ VOP3P v_pk_min_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` v_pk_min_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` v_pk_min_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` - v_pk_mov_b32 :ref:`vdst`::ref:`b32x2`, :ref:`src0`::ref:`b32x2`, :ref:`src1`::ref:`b32x2` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_mov_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` v_pk_mul_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` - v_pk_mul_f32 :ref:`vdst`::ref:`f32x2`, :ref:`src0`::ref:`f32x2`, :ref:`src1`::ref:`f32x2` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` v_pk_mul_lo_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` v_pk_sub_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` v_pk_sub_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` diff --git a/llvm/docs/AMDGPU/gfx10_src32_2.rst b/llvm/docs/AMDGPU/gfx1011_src.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_src32_2.rst rename to llvm/docs/AMDGPU/gfx1011_src.rst index bb976167ef58..a6104a197ef1 100644 --- a/llvm/docs/AMDGPU/gfx10_src32_2.rst +++ b/llvm/docs/AMDGPU/gfx1011_src.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_src32_2: +.. _amdgpu_synid_gfx1011_src: src -=========================== +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_src32_4.rst b/llvm/docs/AMDGPU/gfx1011_src_1.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_src32_4.rst rename to llvm/docs/AMDGPU/gfx1011_src_1.rst index 127990f08be1..759d0313af2a 100644 --- a/llvm/docs/AMDGPU/gfx10_src32_4.rst +++ b/llvm/docs/AMDGPU/gfx1011_src_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_src32_4: +.. _amdgpu_synid_gfx1011_src_1: src -=========================== +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_src32_3.rst b/llvm/docs/AMDGPU/gfx1011_src_2.rst similarity index 81% rename from llvm/docs/AMDGPU/gfx10_src32_3.rst rename to llvm/docs/AMDGPU/gfx1011_src_2.rst index 43bb76b5ac8d..d648ca357444 100644 --- a/llvm/docs/AMDGPU/gfx10_src32_3.rst +++ b/llvm/docs/AMDGPU/gfx1011_src_2.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid10_src32_3: +.. _amdgpu_synid_gfx1011_src_2: src -=========================== +=== Instruction input. *Size:* 1 dword. -*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`iconst`, :ref:`literal` +*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`iconst`, :ref:`ival`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx10_src32_1.rst b/llvm/docs/AMDGPU/gfx1011_src_3.rst similarity index 77% rename from llvm/docs/AMDGPU/gfx10_src32_1.rst rename to llvm/docs/AMDGPU/gfx1011_src_3.rst index f786f406695d..b259810ca4a4 100644 --- a/llvm/docs/AMDGPU/gfx10_src32_1.rst +++ b/llvm/docs/AMDGPU/gfx1011_src_3.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid10_src32_1: +.. _amdgpu_synid_gfx1011_src_3: src -=========================== +=== Instruction input. *Size:* 1 dword. -*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst` +*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst`, :ref:`ival`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx1011_type_dev.rst b/llvm/docs/AMDGPU/gfx1011_type_dev.rst deleted file mode 100644 index c7ddb82757e4..000000000000 --- a/llvm/docs/AMDGPU/gfx1011_type_dev.rst +++ /dev/null @@ -1,13 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid1011_type_dev: - -Type deviation -=========================== - -*Type* of this operand differs from *type* :ref:`implied by the opcode`. This tag specifies actual operand *type*. diff --git a/llvm/docs/AMDGPU/gfx10_type_dev.rst b/llvm/docs/AMDGPU/gfx1011_type_deviation.rst similarity index 69% rename from llvm/docs/AMDGPU/gfx10_type_dev.rst rename to llvm/docs/AMDGPU/gfx1011_type_deviation.rst index dd3d14faaafd..70598228237a 100644 --- a/llvm/docs/AMDGPU/gfx10_type_dev.rst +++ b/llvm/docs/AMDGPU/gfx1011_type_deviation.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid10_type_dev: +.. _amdgpu_synid_gfx1011_type_deviation: -Type deviation -=========================== +Type Deviation +============== -*Type* of this operand differs from *type* :ref:`implied by the opcode`. This tag specifies actual operand *type*. +*Type* of this operand differs from *type* :ref:`implied by the opcode`. This tag specifies actual operand *type*. diff --git a/llvm/docs/AMDGPU/gfx7_vdst32_0.rst b/llvm/docs/AMDGPU/gfx1011_vdst.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx7_vdst32_0.rst rename to llvm/docs/AMDGPU/gfx1011_vdst.rst index e93620355e6d..eb16b8d944f8 100644 --- a/llvm/docs/AMDGPU/gfx7_vdst32_0.rst +++ b/llvm/docs/AMDGPU/gfx1011_vdst.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_vdst32_0: +.. _amdgpu_synid_gfx1011_vdst: vdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx1011_vdst32_0.rst b/llvm/docs/AMDGPU/gfx1011_vdst32_0.rst deleted file mode 100644 index 115b8527fb68..000000000000 --- a/llvm/docs/AMDGPU/gfx1011_vdst32_0.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid1011_vdst32_0: - -vdst -=========================== - -Instruction output. - -*Size:* 1 dword. - -*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vsrc32_0.rst b/llvm/docs/AMDGPU/gfx1011_vsrc.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx8_vsrc32_0.rst rename to llvm/docs/AMDGPU/gfx1011_vsrc.rst index 524f36a0a893..7ebc1359b074 100644 --- a/llvm/docs/AMDGPU/gfx8_vsrc32_0.rst +++ b/llvm/docs/AMDGPU/gfx1011_vsrc.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_vsrc32_0: +.. _amdgpu_synid_gfx1011_vsrc: vsrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx1011_vsrc32_0.rst b/llvm/docs/AMDGPU/gfx1011_vsrc32_0.rst deleted file mode 100644 index be63c6549493..000000000000 --- a/llvm/docs/AMDGPU/gfx1011_vsrc32_0.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid1011_vsrc32_0: - -vsrc -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx10_attr.rst b/llvm/docs/AMDGPU/gfx10_attr.rst index c3091bbad7af..7ea3a3de61ae 100644 --- a/llvm/docs/AMDGPU/gfx10_attr.rst +++ b/llvm/docs/AMDGPU/gfx10_attr.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_attr: +.. _amdgpu_synid_gfx10_attr: attr -=========================== +==== Interpolation attribute and channel: diff --git a/llvm/docs/AMDGPU/gfx7_ret.rst b/llvm/docs/AMDGPU/gfx10_dst.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx7_ret.rst rename to llvm/docs/AMDGPU/gfx10_dst.rst index 899a200c38f6..9b9a81c0ab48 100644 --- a/llvm/docs/AMDGPU/gfx7_ret.rst +++ b/llvm/docs/AMDGPU/gfx10_dst.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid7_ret: +.. _amdgpu_synid_gfx10_dst: dst -=========================== +=== This is an input operand. It may optionally serve as a destination if :ref:`glc` is specified. diff --git a/llvm/docs/AMDGPU/gfx10_mad_type_dev.rst b/llvm/docs/AMDGPU/gfx10_fx_operand.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx10_mad_type_dev.rst rename to llvm/docs/AMDGPU/gfx10_fx_operand.rst index 6bffb83d6471..1f83eb2423be 100644 --- a/llvm/docs/AMDGPU/gfx10_mad_type_dev.rst +++ b/llvm/docs/AMDGPU/gfx10_fx_operand.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_mad_type_dev: +.. _amdgpu_synid_gfx10_fx_operand: -fx -=========================== +FX Operand +========== This is an *f32* or *f16* operand depending on instruction modifiers: diff --git a/llvm/docs/AMDGPU/gfx10_hwreg.rst b/llvm/docs/AMDGPU/gfx10_hwreg.rst index 5a114aede062..65ad41d66770 100644 --- a/llvm/docs/AMDGPU/gfx10_hwreg.rst +++ b/llvm/docs/AMDGPU/gfx10_hwreg.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_hwreg: +.. _amdgpu_synid_gfx10_hwreg: hwreg -=========================== +===== Bits of a hardware register being accessed. diff --git a/llvm/docs/AMDGPU/gfx7_simm16.rst b/llvm/docs/AMDGPU/gfx10_imm16.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx7_simm16.rst rename to llvm/docs/AMDGPU/gfx10_imm16.rst index d6890d429c11..22d73ae5ecce 100644 --- a/llvm/docs/AMDGPU/gfx7_simm16.rst +++ b/llvm/docs/AMDGPU/gfx10_imm16.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid7_simm16: +.. _amdgpu_synid_gfx10_imm16: imm16 -=========================== +===== An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range -32768..65535. diff --git a/llvm/docs/AMDGPU/gfx8_uimm16.rst b/llvm/docs/AMDGPU/gfx10_imm16_1.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx8_uimm16.rst rename to llvm/docs/AMDGPU/gfx10_imm16_1.rst index 591d01503120..ee2380386d3e 100644 --- a/llvm/docs/AMDGPU/gfx8_uimm16.rst +++ b/llvm/docs/AMDGPU/gfx10_imm16_1.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid8_uimm16: +.. _amdgpu_synid_gfx10_imm16_1: imm16 -=========================== +===== An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range 0..65535. diff --git a/llvm/docs/AMDGPU/gfx8_bimm16.rst b/llvm/docs/AMDGPU/gfx10_imm16_2.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx8_bimm16.rst rename to llvm/docs/AMDGPU/gfx10_imm16_2.rst index 83cac003e488..2500954a77ed 100644 --- a/llvm/docs/AMDGPU/gfx8_bimm16.rst +++ b/llvm/docs/AMDGPU/gfx10_imm16_2.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid8_bimm16: +.. _amdgpu_synid_gfx10_imm16_2: imm16 -=========================== +===== A 16-bit :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range -32768..65535. diff --git a/llvm/docs/AMDGPU/gfx10_label.rst b/llvm/docs/AMDGPU/gfx10_label.rst index cf1a8ea598f9..f5dddfd4036d 100644 --- a/llvm/docs/AMDGPU/gfx10_label.rst +++ b/llvm/docs/AMDGPU/gfx10_label.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_label: +.. _amdgpu_synid_gfx10_label: label -=========================== +===== A branch target which is a 16-bit signed integer treated as a PC-relative dword offset. diff --git a/llvm/docs/AMDGPU/gfx7_mod.rst b/llvm/docs/AMDGPU/gfx10_m.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx7_mod.rst rename to llvm/docs/AMDGPU/gfx10_m.rst index 0b03299b254b..8d4480bcf589 100644 --- a/llvm/docs/AMDGPU/gfx7_mod.rst +++ b/llvm/docs/AMDGPU/gfx10_m.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid7_mod: +.. _amdgpu_synid_gfx10_m: m -=========================== += This operand may be used with floating point operand modifiers :ref:`abs` and :ref:`neg`. diff --git a/llvm/docs/AMDGPU/gfx8_mod_sdwa_sext.rst b/llvm/docs/AMDGPU/gfx10_m_1.rst similarity index 85% rename from llvm/docs/AMDGPU/gfx8_mod_sdwa_sext.rst rename to llvm/docs/AMDGPU/gfx10_m_1.rst index 64141c5104f1..b3f9d2f22e93 100644 --- a/llvm/docs/AMDGPU/gfx8_mod_sdwa_sext.rst +++ b/llvm/docs/AMDGPU/gfx10_m_1.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid8_mod_sdwa_sext: +.. _amdgpu_synid_gfx10_m_1: m -=========================== += This operand may be used with integer operand modifier :ref:`sext`. diff --git a/llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst b/llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst deleted file mode 100644 index 05bcc0330840..000000000000 --- a/llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst +++ /dev/null @@ -1,13 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid10_mod_dpp_sdwa_abs_neg: - -m -=========================== - -This operand may be used with floating point operand modifiers :ref:`abs` and :ref:`neg`. diff --git a/llvm/docs/AMDGPU/gfx10_msg.rst b/llvm/docs/AMDGPU/gfx10_msg.rst index c0774d85a62e..2ebd4f00cdf8 100644 --- a/llvm/docs/AMDGPU/gfx10_msg.rst +++ b/llvm/docs/AMDGPU/gfx10_msg.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_msg: +.. _amdgpu_synid_gfx10_msg: msg -=========================== +=== A 16-bit message code. The bits of this operand have the following meaning: @@ -99,4 +99,3 @@ Examples: stream = 1 s_sendmsg sendmsg(msg, op, stream) s_sendmsg sendmsg(2, GS_OP_CUT) - diff --git a/llvm/docs/AMDGPU/gfx10_opt.rst b/llvm/docs/AMDGPU/gfx10_opt.rst index 16acc93a0414..b4a372a02f7e 100644 --- a/llvm/docs/AMDGPU/gfx10_opt.rst +++ b/llvm/docs/AMDGPU/gfx10_opt.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid10_opt: +.. _amdgpu_synid_gfx10_opt: opt -=========================== +=== This is an optional operand. It must be used if and only if :ref:`glc` is specified. diff --git a/llvm/docs/AMDGPU/gfx10_param.rst b/llvm/docs/AMDGPU/gfx10_param.rst index 0e59db7e3edf..c308fe277185 100644 --- a/llvm/docs/AMDGPU/gfx10_param.rst +++ b/llvm/docs/AMDGPU/gfx10_param.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_param: +.. _amdgpu_synid_gfx10_param: param -=========================== +===== Interpolation parameter to read: diff --git a/llvm/docs/AMDGPU/gfx8_perm_smem.rst b/llvm/docs/AMDGPU/gfx10_probe.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx8_perm_smem.rst rename to llvm/docs/AMDGPU/gfx10_probe.rst index b18920bd1142..cb9c879dfa7c 100644 --- a/llvm/docs/AMDGPU/gfx8_perm_smem.rst +++ b/llvm/docs/AMDGPU/gfx10_probe.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_perm_smem: +.. _amdgpu_synid_gfx10_probe: -imm3 -=========================== +probe +===== A bit mask which indicates request permissions. diff --git a/llvm/docs/AMDGPU/gfx10_saddr_flat_global.rst b/llvm/docs/AMDGPU/gfx10_saddr.rst similarity index 64% rename from llvm/docs/AMDGPU/gfx10_saddr_flat_global.rst rename to llvm/docs/AMDGPU/gfx10_saddr.rst index 2362d0c020ef..27d947ccfe02 100644 --- a/llvm/docs/AMDGPU/gfx10_saddr_flat_global.rst +++ b/llvm/docs/AMDGPU/gfx10_saddr.rst @@ -5,15 +5,15 @@ * * ************************************************** -.. _amdgpu_synid10_saddr_flat_global: +.. _amdgpu_synid_gfx10_saddr: saddr -=========================== +===== An optional 64-bit flat global address. Must be specified as :ref:`off` if not used. -See :ref:`vaddr` for description of available addressing modes. +See :ref:`vaddr` for description of available addressing modes. *Size:* 2 dwords. -*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`off` +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`off` diff --git a/llvm/docs/AMDGPU/gfx10_saddr_flat_scratch.rst b/llvm/docs/AMDGPU/gfx10_saddr_1.rst similarity index 62% rename from llvm/docs/AMDGPU/gfx10_saddr_flat_scratch.rst rename to llvm/docs/AMDGPU/gfx10_saddr_1.rst index 8fea5d304288..ba860500d372 100644 --- a/llvm/docs/AMDGPU/gfx10_saddr_flat_scratch.rst +++ b/llvm/docs/AMDGPU/gfx10_saddr_1.rst @@ -5,15 +5,15 @@ * * ************************************************** -.. _amdgpu_synid10_saddr_flat_scratch: +.. _amdgpu_synid_gfx10_saddr_1: saddr -=========================== +===== An optional 32-bit flat scratch offset. Must be specified as :ref:`off` if not used. -Either this operand or :ref:`vaddr` must be set to :ref:`off`. +Either this operand or :ref:`vaddr` must be set to :ref:`off`. *Size:* 1 dword. -*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`null`, :ref:`off` +*Operands:* :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`off` diff --git a/llvm/docs/AMDGPU/gfx10_base_smem_addr.rst b/llvm/docs/AMDGPU/gfx10_sbase.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx10_base_smem_addr.rst rename to llvm/docs/AMDGPU/gfx10_sbase.rst index 9d5211432f9f..be764564eca4 100644 --- a/llvm/docs/AMDGPU/gfx10_base_smem_addr.rst +++ b/llvm/docs/AMDGPU/gfx10_sbase.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_base_smem_addr: +.. _amdgpu_synid_gfx10_sbase: sbase -=========================== +===== A 64-bit base address for scalar memory operations. diff --git a/llvm/docs/AMDGPU/gfx7_base_smem_buf.rst b/llvm/docs/AMDGPU/gfx10_sbase_1.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx7_base_smem_buf.rst rename to llvm/docs/AMDGPU/gfx10_sbase_1.rst index 416cac715c71..ea58778a4363 100644 --- a/llvm/docs/AMDGPU/gfx7_base_smem_buf.rst +++ b/llvm/docs/AMDGPU/gfx10_sbase_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_base_smem_buf: +.. _amdgpu_synid_gfx10_sbase_1: sbase -=========================== +===== A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride. diff --git a/llvm/docs/AMDGPU/gfx10_base_smem_scratch.rst b/llvm/docs/AMDGPU/gfx10_sbase_2.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_base_smem_scratch.rst rename to llvm/docs/AMDGPU/gfx10_sbase_2.rst index 2b7e8b4cd4b1..14a9a4bc0496 100644 --- a/llvm/docs/AMDGPU/gfx10_base_smem_scratch.rst +++ b/llvm/docs/AMDGPU/gfx10_sbase_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_base_smem_scratch: +.. _amdgpu_synid_gfx10_sbase_2: sbase -=========================== +===== This operand is ignored by H/W and :ref:`flat_scratch` is supplied instead. diff --git a/llvm/docs/AMDGPU/gfx10_data_smem_atomic32.rst b/llvm/docs/AMDGPU/gfx10_sdata.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_data_smem_atomic32.rst rename to llvm/docs/AMDGPU/gfx10_sdata.rst index 5e8f7ca30204..3537824b06c7 100644 --- a/llvm/docs/AMDGPU/gfx10_data_smem_atomic32.rst +++ b/llvm/docs/AMDGPU/gfx10_sdata.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_data_smem_atomic32: +.. _amdgpu_synid_gfx10_sdata: sdata -=========================== +===== Input data for an atomic instruction. diff --git a/llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst b/llvm/docs/AMDGPU/gfx10_sdata_1.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst rename to llvm/docs/AMDGPU/gfx10_sdata_1.rst index 4cd5a05b41a5..96dc05038656 100644 --- a/llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst +++ b/llvm/docs/AMDGPU/gfx10_sdata_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_data_smem_atomic64: +.. _amdgpu_synid_gfx10_sdata_1: sdata -=========================== +===== Input data for an atomic instruction. diff --git a/llvm/docs/AMDGPU/gfx10_data_smem_atomic128.rst b/llvm/docs/AMDGPU/gfx10_sdata_2.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_data_smem_atomic128.rst rename to llvm/docs/AMDGPU/gfx10_sdata_2.rst index c59c4888fabd..22090af1cd38 100644 --- a/llvm/docs/AMDGPU/gfx10_data_smem_atomic128.rst +++ b/llvm/docs/AMDGPU/gfx10_sdata_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_data_smem_atomic128: +.. _amdgpu_synid_gfx10_sdata_2: sdata -=========================== +===== Input data for an atomic instruction. diff --git a/llvm/docs/AMDGPU/gfx10_sdata32_0.rst b/llvm/docs/AMDGPU/gfx10_sdata_3.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_sdata32_0.rst rename to llvm/docs/AMDGPU/gfx10_sdata_3.rst index 10e10caf626b..38eedc59b338 100644 --- a/llvm/docs/AMDGPU/gfx10_sdata32_0.rst +++ b/llvm/docs/AMDGPU/gfx10_sdata_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_sdata32_0: +.. _amdgpu_synid_gfx10_sdata_3: sdata -=========================== +===== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_sdata64_0.rst b/llvm/docs/AMDGPU/gfx10_sdata_4.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_sdata64_0.rst rename to llvm/docs/AMDGPU/gfx10_sdata_4.rst index f03938a3c8aa..07fb5ff687a8 100644 --- a/llvm/docs/AMDGPU/gfx10_sdata64_0.rst +++ b/llvm/docs/AMDGPU/gfx10_sdata_4.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_sdata64_0: +.. _amdgpu_synid_gfx10_sdata_4: sdata -=========================== +===== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx8_sdata128_0.rst b/llvm/docs/AMDGPU/gfx10_sdata_5.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx8_sdata128_0.rst rename to llvm/docs/AMDGPU/gfx10_sdata_5.rst index a52703c3545a..153153a2e068 100644 --- a/llvm/docs/AMDGPU/gfx8_sdata128_0.rst +++ b/llvm/docs/AMDGPU/gfx10_sdata_5.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_sdata128_0: +.. _amdgpu_synid_gfx10_sdata_5: sdata -=========================== +===== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_wsdst.rst b/llvm/docs/AMDGPU/gfx10_sdst.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx10_wsdst.rst rename to llvm/docs/AMDGPU/gfx10_sdst.rst index 1e39990f8903..18327a8646d1 100644 --- a/llvm/docs/AMDGPU/gfx10_wsdst.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_wsdst: +.. _amdgpu_synid_gfx10_sdst: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx10_sdst32_0.rst b/llvm/docs/AMDGPU/gfx10_sdst_1.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_sdst32_0.rst rename to llvm/docs/AMDGPU/gfx10_sdst_1.rst index 1000d83ffc2e..4fab64c9a16e 100644 --- a/llvm/docs/AMDGPU/gfx10_sdst32_0.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_sdst32_0: +.. _amdgpu_synid_gfx10_sdst_1: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx10_sdst512_0.rst b/llvm/docs/AMDGPU/gfx10_sdst_2.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx10_sdst512_0.rst rename to llvm/docs/AMDGPU/gfx10_sdst_2.rst index f72a2d5e0280..657e8e92581c 100644 --- a/llvm/docs/AMDGPU/gfx10_sdst512_0.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_sdst512_0: +.. _amdgpu_synid_gfx10_sdst_2: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx10_sdst64_0.rst b/llvm/docs/AMDGPU/gfx10_sdst_3.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_sdst64_0.rst rename to llvm/docs/AMDGPU/gfx10_sdst_3.rst index 75797f2a4332..ba5378bd1100 100644 --- a/llvm/docs/AMDGPU/gfx10_sdst64_0.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_sdst64_0: +.. _amdgpu_synid_gfx10_sdst_3: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx8_sdst128_0.rst b/llvm/docs/AMDGPU/gfx10_sdst_4.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx8_sdst128_0.rst rename to llvm/docs/AMDGPU/gfx10_sdst_4.rst index 277e3db02c41..8f3d8da00d04 100644 --- a/llvm/docs/AMDGPU/gfx8_sdst128_0.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst_4.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_sdst128_0: +.. _amdgpu_synid_gfx10_sdst_4: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx8_sdst256_0.rst b/llvm/docs/AMDGPU/gfx10_sdst_5.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx8_sdst256_0.rst rename to llvm/docs/AMDGPU/gfx10_sdst_5.rst index 2e54b9b1462c..042ab9bd88b9 100644 --- a/llvm/docs/AMDGPU/gfx8_sdst256_0.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst_5.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_sdst256_0: +.. _amdgpu_synid_gfx10_sdst_5: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx10_sdst32_1.rst b/llvm/docs/AMDGPU/gfx10_sdst_6.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_sdst32_1.rst rename to llvm/docs/AMDGPU/gfx10_sdst_6.rst index ddfb348c3de8..80f18caf85d3 100644 --- a/llvm/docs/AMDGPU/gfx10_sdst32_1.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst_6.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_sdst32_1: +.. _amdgpu_synid_gfx10_sdst_6: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx10_sdst64_1.rst b/llvm/docs/AMDGPU/gfx10_sdst_7.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx10_sdst64_1.rst rename to llvm/docs/AMDGPU/gfx10_sdst_7.rst index be8b6a06cec1..09ad3be1b829 100644 --- a/llvm/docs/AMDGPU/gfx10_sdst64_1.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst_7.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_sdst64_1: +.. _amdgpu_synid_gfx10_sdst_7: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx10_sdst32_2.rst b/llvm/docs/AMDGPU/gfx10_sdst_8.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_sdst32_2.rst rename to llvm/docs/AMDGPU/gfx10_sdst_8.rst index 41a078ba4238..572446119cd8 100644 --- a/llvm/docs/AMDGPU/gfx10_sdst32_2.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst_8.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_sdst32_2: +.. _amdgpu_synid_gfx10_sdst_8: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx8_bimm32.rst b/llvm/docs/AMDGPU/gfx10_simm32.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx8_bimm32.rst rename to llvm/docs/AMDGPU/gfx10_simm32.rst index ab5c53a6540a..44f1f517349e 100644 --- a/llvm/docs/AMDGPU/gfx8_bimm32.rst +++ b/llvm/docs/AMDGPU/gfx10_simm32.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid8_bimm32: +.. _amdgpu_synid_gfx10_simm32: -imm32 -=========================== +simm32 +====== An :ref:`integer_number` or an :ref:`absolute_expression`. The value is truncated to 32 bits. diff --git a/llvm/docs/AMDGPU/gfx8_fimm16.rst b/llvm/docs/AMDGPU/gfx10_simm32_1.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx8_fimm16.rst rename to llvm/docs/AMDGPU/gfx10_simm32_1.rst index 2050af2e2874..54090bfedc8f 100644 --- a/llvm/docs/AMDGPU/gfx8_fimm16.rst +++ b/llvm/docs/AMDGPU/gfx10_simm32_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_fimm16: +.. _amdgpu_synid_gfx10_simm32_1: -imm32 -=========================== +simm32 +====== A :ref:`floating-point_number`, an :ref:`integer_number`, or an :ref:`absolute_expression`. The value is converted to *f16* as described :ref:`here`. diff --git a/llvm/docs/AMDGPU/gfx8_fimm32.rst b/llvm/docs/AMDGPU/gfx10_simm32_2.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx8_fimm32.rst rename to llvm/docs/AMDGPU/gfx10_simm32_2.rst index 49796b47ed08..24d3011fd606 100644 --- a/llvm/docs/AMDGPU/gfx8_fimm32.rst +++ b/llvm/docs/AMDGPU/gfx10_simm32_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_fimm32: +.. _amdgpu_synid_gfx10_simm32_2: -imm32 -=========================== +simm32 +====== A :ref:`floating-point_number`, an :ref:`integer_number`, or an :ref:`absolute_expression`. The value is converted to *f32* as described :ref:`here`. diff --git a/llvm/docs/AMDGPU/gfx10_offset_buf.rst b/llvm/docs/AMDGPU/gfx10_soffset.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_offset_buf.rst rename to llvm/docs/AMDGPU/gfx10_soffset.rst index 99598fdd1516..0154df93ec84 100644 --- a/llvm/docs/AMDGPU/gfx10_offset_buf.rst +++ b/llvm/docs/AMDGPU/gfx10_soffset.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_offset_buf: +.. _amdgpu_synid_gfx10_soffset: soffset -=========================== +======= An unsigned byte offset. diff --git a/llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst b/llvm/docs/AMDGPU/gfx10_soffset_1.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst rename to llvm/docs/AMDGPU/gfx10_soffset_1.rst index 30763e7f9bbb..b73e114d17d4 100644 --- a/llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst +++ b/llvm/docs/AMDGPU/gfx10_soffset_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_offset_smem_plain: +.. _amdgpu_synid_gfx10_soffset_1: soffset -=========================== +======= An offset added to the base address to get memory address. diff --git a/llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst b/llvm/docs/AMDGPU/gfx10_soffset_2.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst rename to llvm/docs/AMDGPU/gfx10_soffset_2.rst index b7acd418e89d..772d887bf217 100644 --- a/llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst +++ b/llvm/docs/AMDGPU/gfx10_soffset_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_offset_smem_buf: +.. _amdgpu_synid_gfx10_soffset_2: soffset -=========================== +======= An unsigned 20-bit offset added to the base address to get memory address. diff --git a/llvm/docs/AMDGPU/gfx10_src32_0.rst b/llvm/docs/AMDGPU/gfx10_src.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_src32_0.rst rename to llvm/docs/AMDGPU/gfx10_src.rst index f4ae944c9601..f83c11822c02 100644 --- a/llvm/docs/AMDGPU/gfx10_src32_0.rst +++ b/llvm/docs/AMDGPU/gfx10_src.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_src32_0: +.. _amdgpu_synid_gfx10_src: src -=========================== +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_src32_5.rst b/llvm/docs/AMDGPU/gfx10_src_1.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx10_src32_5.rst rename to llvm/docs/AMDGPU/gfx10_src_1.rst index b856aa975fa1..67fc1c59cf50 100644 --- a/llvm/docs/AMDGPU/gfx10_src32_5.rst +++ b/llvm/docs/AMDGPU/gfx10_src_1.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid10_src32_5: +.. _amdgpu_synid_gfx10_src_1: src -=========================== +=== Instruction input. *Size:* 1 dword. -*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst`, :ref:`literal` +*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst`, :ref:`ival` diff --git a/llvm/docs/AMDGPU/gfx1011_src32_0.rst b/llvm/docs/AMDGPU/gfx10_src_2.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx1011_src32_0.rst rename to llvm/docs/AMDGPU/gfx10_src_2.rst index 8d82f4171f6d..9bd53ddb5412 100644 --- a/llvm/docs/AMDGPU/gfx1011_src32_0.rst +++ b/llvm/docs/AMDGPU/gfx10_src_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid1011_src32_0: +.. _amdgpu_synid_gfx10_src_2: src -=========================== +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_src64_0.rst b/llvm/docs/AMDGPU/gfx10_src_3.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_src64_0.rst rename to llvm/docs/AMDGPU/gfx10_src_3.rst index f88ccf2a68c9..a581d7b4c96c 100644 --- a/llvm/docs/AMDGPU/gfx10_src64_0.rst +++ b/llvm/docs/AMDGPU/gfx10_src_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_src64_0: +.. _amdgpu_synid_gfx10_src_3: src -=========================== +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx1011_src32_2.rst b/llvm/docs/AMDGPU/gfx10_src_4.rst similarity index 81% rename from llvm/docs/AMDGPU/gfx1011_src32_2.rst rename to llvm/docs/AMDGPU/gfx10_src_4.rst index 6c62701709a1..6bbb235dcf5c 100644 --- a/llvm/docs/AMDGPU/gfx1011_src32_2.rst +++ b/llvm/docs/AMDGPU/gfx10_src_4.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid1011_src32_2: +.. _amdgpu_synid_gfx10_src_4: src -=========================== +=== Instruction input. *Size:* 1 dword. -*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`iconst`, :ref:`literal` +*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`iconst`, :ref:`ival`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx7_vsrc32_1.rst b/llvm/docs/AMDGPU/gfx10_src_5.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx7_vsrc32_1.rst rename to llvm/docs/AMDGPU/gfx10_src_5.rst index 063216a5e040..44a447193cef 100644 --- a/llvm/docs/AMDGPU/gfx7_vsrc32_1.rst +++ b/llvm/docs/AMDGPU/gfx10_src_5.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_vsrc32_1: +.. _amdgpu_synid_gfx10_src_5: -vsrc -=========================== +src +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx1011_src32_1.rst b/llvm/docs/AMDGPU/gfx10_src_6.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx1011_src32_1.rst rename to llvm/docs/AMDGPU/gfx10_src_6.rst index b923912d041c..b1b49b168de7 100644 --- a/llvm/docs/AMDGPU/gfx1011_src32_1.rst +++ b/llvm/docs/AMDGPU/gfx10_src_6.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid1011_src32_1: +.. _amdgpu_synid_gfx10_src_6: src -=========================== +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_src32_6.rst b/llvm/docs/AMDGPU/gfx10_src_7.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_src32_6.rst rename to llvm/docs/AMDGPU/gfx10_src_7.rst index 3db381aa1f40..dffdab171432 100644 --- a/llvm/docs/AMDGPU/gfx10_src32_6.rst +++ b/llvm/docs/AMDGPU/gfx10_src_7.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_src32_6: +.. _amdgpu_synid_gfx10_src_7: src -=========================== +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx1011_src32_3.rst b/llvm/docs/AMDGPU/gfx10_src_8.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx1011_src32_3.rst rename to llvm/docs/AMDGPU/gfx10_src_8.rst index 00ffe2317566..25297cfe91bd 100644 --- a/llvm/docs/AMDGPU/gfx1011_src32_3.rst +++ b/llvm/docs/AMDGPU/gfx10_src_8.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid1011_src32_3: +.. _amdgpu_synid_gfx10_src_8: src -=========================== +=== Instruction input. *Size:* 1 dword. -*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst`, :ref:`literal` +*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst`, :ref:`ival`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx8_rsrc_mimg.rst b/llvm/docs/AMDGPU/gfx10_srsrc.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx8_rsrc_mimg.rst rename to llvm/docs/AMDGPU/gfx10_srsrc.rst index 3ca255928983..704c2b216512 100644 --- a/llvm/docs/AMDGPU/gfx8_rsrc_mimg.rst +++ b/llvm/docs/AMDGPU/gfx10_srsrc.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_rsrc_mimg: +.. _amdgpu_synid_gfx10_srsrc: srsrc -=========================== +===== Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format. diff --git a/llvm/docs/AMDGPU/gfx8_rsrc_buf.rst b/llvm/docs/AMDGPU/gfx10_srsrc_1.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx8_rsrc_buf.rst rename to llvm/docs/AMDGPU/gfx10_srsrc_1.rst index ecdb0a0d9dcf..11546818280d 100644 --- a/llvm/docs/AMDGPU/gfx8_rsrc_buf.rst +++ b/llvm/docs/AMDGPU/gfx10_srsrc_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_rsrc_buf: +.. _amdgpu_synid_gfx10_srsrc_1: srsrc -=========================== +===== Buffer resource constant which defines the address and characteristics of the buffer in memory. diff --git a/llvm/docs/AMDGPU/gfx8_samp_mimg.rst b/llvm/docs/AMDGPU/gfx10_ssamp.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx8_samp_mimg.rst rename to llvm/docs/AMDGPU/gfx10_ssamp.rst index c4b27125768d..0bde3b7c3225 100644 --- a/llvm/docs/AMDGPU/gfx8_samp_mimg.rst +++ b/llvm/docs/AMDGPU/gfx10_ssamp.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_samp_mimg: +.. _amdgpu_synid_gfx10_ssamp: ssamp -=========================== +===== Sampler constant used to specify filtering options applied to the image data after it is read. diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_0.rst b/llvm/docs/AMDGPU/gfx10_ssrc.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_ssrc32_0.rst rename to llvm/docs/AMDGPU/gfx10_ssrc.rst index e444898cdc15..cdcb9e6b3692 100644 --- a/llvm/docs/AMDGPU/gfx10_ssrc32_0.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_ssrc32_0: +.. _amdgpu_synid_gfx10_ssrc: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_ssrc64_0.rst b/llvm/docs/AMDGPU/gfx10_ssrc_1.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_ssrc64_0.rst rename to llvm/docs/AMDGPU/gfx10_ssrc_1.rst index 7e351f44a4ca..96545ffc5767 100644 --- a/llvm/docs/AMDGPU/gfx10_ssrc64_0.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_ssrc64_0: +.. _amdgpu_synid_gfx10_ssrc_1: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_1.rst b/llvm/docs/AMDGPU/gfx10_ssrc_2.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_ssrc32_1.rst rename to llvm/docs/AMDGPU/gfx10_ssrc_2.rst index 4fdbe1c099eb..ee31917115f8 100644 --- a/llvm/docs/AMDGPU/gfx10_ssrc32_1.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_ssrc32_1: +.. _amdgpu_synid_gfx10_ssrc_2: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_ssrc64_1.rst b/llvm/docs/AMDGPU/gfx10_ssrc_3.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_ssrc64_1.rst rename to llvm/docs/AMDGPU/gfx10_ssrc_3.rst index 45116b00c187..aa4ff88d059a 100644 --- a/llvm/docs/AMDGPU/gfx10_ssrc64_1.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_ssrc64_1: +.. _amdgpu_synid_gfx10_ssrc_3: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_2.rst b/llvm/docs/AMDGPU/gfx10_ssrc_4.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_ssrc32_2.rst rename to llvm/docs/AMDGPU/gfx10_ssrc_4.rst index 1b46e77a43c6..f4aef373258b 100644 --- a/llvm/docs/AMDGPU/gfx10_ssrc32_2.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc_4.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_ssrc32_2: +.. _amdgpu_synid_gfx10_ssrc_4: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_wssrc.rst b/llvm/docs/AMDGPU/gfx10_ssrc_5.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx10_wssrc.rst rename to llvm/docs/AMDGPU/gfx10_ssrc_5.rst index 35fdb02a0eac..e36c48f38e96 100644 --- a/llvm/docs/AMDGPU/gfx10_wssrc.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc_5.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_wssrc: +.. _amdgpu_synid_gfx10_ssrc_5: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_3.rst b/llvm/docs/AMDGPU/gfx10_ssrc_6.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_ssrc32_3.rst rename to llvm/docs/AMDGPU/gfx10_ssrc_6.rst index ec6b1152dfa1..15972cf70274 100644 --- a/llvm/docs/AMDGPU/gfx10_ssrc32_3.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc_6.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_ssrc32_3: +.. _amdgpu_synid_gfx10_ssrc_6: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_4.rst b/llvm/docs/AMDGPU/gfx10_ssrc_7.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx10_ssrc32_4.rst rename to llvm/docs/AMDGPU/gfx10_ssrc_7.rst index bba8d5aeaa18..3507e8373b08 100644 --- a/llvm/docs/AMDGPU/gfx10_ssrc32_4.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc_7.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_ssrc32_4: +.. _amdgpu_synid_gfx10_ssrc_7: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_5.rst b/llvm/docs/AMDGPU/gfx10_ssrc_8.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_ssrc32_5.rst rename to llvm/docs/AMDGPU/gfx10_ssrc_8.rst index a0b1bbf0463f..48a7e71b64ef 100644 --- a/llvm/docs/AMDGPU/gfx10_ssrc32_5.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc_8.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_ssrc32_5: +.. _amdgpu_synid_gfx10_ssrc_8: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_tgt.rst b/llvm/docs/AMDGPU/gfx10_tgt.rst index f562c72962dd..342466a9863f 100644 --- a/llvm/docs/AMDGPU/gfx10_tgt.rst +++ b/llvm/docs/AMDGPU/gfx10_tgt.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_tgt: +.. _amdgpu_synid_gfx10_tgt: tgt -=========================== +=== An export target: diff --git a/llvm/docs/AMDGPU/gfx7_type_dev.rst b/llvm/docs/AMDGPU/gfx10_type_deviation.rst similarity index 69% rename from llvm/docs/AMDGPU/gfx7_type_dev.rst rename to llvm/docs/AMDGPU/gfx10_type_deviation.rst index faef5f4ee3ac..e0e417deb3af 100644 --- a/llvm/docs/AMDGPU/gfx7_type_dev.rst +++ b/llvm/docs/AMDGPU/gfx10_type_deviation.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid7_type_dev: +.. _amdgpu_synid_gfx10_type_deviation: -Type deviation -=========================== +Type Deviation +============== -*Type* of this operand differs from *type* :ref:`implied by the opcode`. This tag specifies actual operand *type*. +*Type* of this operand differs from *type* :ref:`implied by the opcode`. This tag specifies actual operand *type*. diff --git a/llvm/docs/AMDGPU/gfx7_addr_ds.rst b/llvm/docs/AMDGPU/gfx10_vaddr.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx7_addr_ds.rst rename to llvm/docs/AMDGPU/gfx10_vaddr.rst index c9cab7d45ec8..e87fd388d692 100644 --- a/llvm/docs/AMDGPU/gfx7_addr_ds.rst +++ b/llvm/docs/AMDGPU/gfx10_vaddr.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_addr_ds: +.. _amdgpu_synid_gfx10_vaddr: vaddr -=========================== +===== An offset from the start of GDS/LDS memory. diff --git a/llvm/docs/AMDGPU/gfx7_addr_flat.rst b/llvm/docs/AMDGPU/gfx10_vaddr_1.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx7_addr_flat.rst rename to llvm/docs/AMDGPU/gfx10_vaddr_1.rst index 93deea6d7a2f..aca79412fd58 100644 --- a/llvm/docs/AMDGPU/gfx7_addr_flat.rst +++ b/llvm/docs/AMDGPU/gfx10_vaddr_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_addr_flat: +.. _amdgpu_synid_gfx10_vaddr_1: vaddr -=========================== +===== A 64-bit flat address. diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_2.rst b/llvm/docs/AMDGPU/gfx10_vaddr_2.rst new file mode 100644 index 000000000000..1229618b509c --- /dev/null +++ b/llvm/docs/AMDGPU/gfx10_vaddr_2.rst @@ -0,0 +1,20 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx10_vaddr_2: + +vaddr +===== + +A 64-bit flat global address or a 32-bit offset depending on addressing mode: + +* Address = :ref:`vaddr` + :ref:`offset12s`. :ref:`vaddr` is a 64-bit address. This mode is indicated by :ref:`saddr` set to :ref:`off`. +* Address = :ref:`saddr` + :ref:`vaddr` + :ref:`offset12s`. :ref:`vaddr` is a 32-bit offset. This mode is used when :ref:`saddr` is not :ref:`off`. + +*Size:* 1 or 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_flat_scratch.rst b/llvm/docs/AMDGPU/gfx10_vaddr_3.rst similarity index 72% rename from llvm/docs/AMDGPU/gfx10_vaddr_flat_scratch.rst rename to llvm/docs/AMDGPU/gfx10_vaddr_3.rst index cc6d1af64eed..c866483f5697 100644 --- a/llvm/docs/AMDGPU/gfx10_vaddr_flat_scratch.rst +++ b/llvm/docs/AMDGPU/gfx10_vaddr_3.rst @@ -5,14 +5,14 @@ * * ************************************************** -.. _amdgpu_synid10_vaddr_flat_scratch: +.. _amdgpu_synid_gfx10_vaddr_3: vaddr -=========================== +===== An optional 32-bit flat scratch offset. Must be specified as :ref:`off` if not used. -Either this operand or :ref:`saddr` must be set to :ref:`off`. +Either this operand or :ref:`saddr` must be set to :ref:`off`. *Size:* 1 dword. diff --git a/llvm/docs/AMDGPU/gfx10_addr_mimg.rst b/llvm/docs/AMDGPU/gfx10_vaddr_4.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx10_addr_mimg.rst rename to llvm/docs/AMDGPU/gfx10_vaddr_4.rst index 7555e2836ee0..c7ac072fb1c9 100644 --- a/llvm/docs/AMDGPU/gfx10_addr_mimg.rst +++ b/llvm/docs/AMDGPU/gfx10_vaddr_4.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_addr_mimg: +.. _amdgpu_synid_gfx10_vaddr_4: vaddr -=========================== +===== Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image. @@ -19,5 +19,4 @@ This operand may be specified using either :ref:`standard VGPR syntax`, the size is 1-13 dwords. * If specified using :ref:`standard VGPR syntax`, the size is 1, 2, 3, 4, 8 or 16 dwords. Note that assembler currently supports a limited range of register sequences. - *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_addr_buf.rst b/llvm/docs/AMDGPU/gfx10_vaddr_5.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx8_addr_buf.rst rename to llvm/docs/AMDGPU/gfx10_vaddr_5.rst index 74aa275c1997..c5c8f6492fa0 100644 --- a/llvm/docs/AMDGPU/gfx8_addr_buf.rst +++ b/llvm/docs/AMDGPU/gfx10_vaddr_5.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_addr_buf: +.. _amdgpu_synid_gfx10_vaddr_5: vaddr -=========================== +===== This is an optional operand which may specify offset and/or index. diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst b/llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst deleted file mode 100644 index 06713f931960..000000000000 --- a/llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst +++ /dev/null @@ -1,20 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid10_vaddr_flat_global: - -vaddr -=========================== - -A 64-bit flat global address or a 32-bit offset depending on addressing mode: - -* Address = :ref:`vaddr` + :ref:`offset12s`. :ref:`vaddr` is a 64-bit address. This mode is indicated by :ref:`saddr` set to :ref:`off`. -* Address = :ref:`saddr` + :ref:`vaddr` + :ref:`offset12s`. :ref:`vaddr` is a 32-bit offset. This mode is used when :ref:`saddr` is not :ref:`off`. - -*Size:* 1 or 2 dwords. - -*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx10_vcc_32.rst b/llvm/docs/AMDGPU/gfx10_vcc.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx10_vcc_32.rst rename to llvm/docs/AMDGPU/gfx10_vcc.rst index 1525dab0fd5d..1d77db33ed1d 100644 --- a/llvm/docs/AMDGPU/gfx10_vcc_32.rst +++ b/llvm/docs/AMDGPU/gfx10_vcc.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_vcc_32: +.. _amdgpu_synid_gfx10_vcc: vcc -=========================== +=== Vector condition code. This operand depends on wavefront size: diff --git a/llvm/docs/AMDGPU/gfx8_vdata32_0.rst b/llvm/docs/AMDGPU/gfx10_vdata.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx8_vdata32_0.rst rename to llvm/docs/AMDGPU/gfx10_vdata.rst index b89d65b1c793..38048c66d8ad 100644 --- a/llvm/docs/AMDGPU/gfx8_vdata32_0.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_vdata32_0: +.. _amdgpu_synid_gfx10_vdata: vdata -=========================== +===== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_vdata0.rst b/llvm/docs/AMDGPU/gfx10_vdata0.rst new file mode 100644 index 000000000000..f660fa6296ef --- /dev/null +++ b/llvm/docs/AMDGPU/gfx10_vdata0.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx10_vdata0: + +vdata0 +====== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx10_vdata0_1.rst b/llvm/docs/AMDGPU/gfx10_vdata0_1.rst new file mode 100644 index 000000000000..10741bc5f8ed --- /dev/null +++ b/llvm/docs/AMDGPU/gfx10_vdata0_1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx10_vdata0_1: + +vdata0 +====== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx10_vdata1.rst b/llvm/docs/AMDGPU/gfx10_vdata1.rst new file mode 100644 index 000000000000..a775bccfb35b --- /dev/null +++ b/llvm/docs/AMDGPU/gfx10_vdata1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx10_vdata1: + +vdata1 +====== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx10_vdata1_1.rst b/llvm/docs/AMDGPU/gfx10_vdata1_1.rst new file mode 100644 index 000000000000..1834fce9d807 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx10_vdata1_1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx10_vdata1_1: + +vdata1 +====== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx7_vdata64_0.rst b/llvm/docs/AMDGPU/gfx10_vdata_1.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx7_vdata64_0.rst rename to llvm/docs/AMDGPU/gfx10_vdata_1.rst index fceea9fd4b18..2190149b49db 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata64_0.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_vdata64_0: +.. _amdgpu_synid_gfx10_vdata_1: vdata -=========================== +===== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx8_data_buf_atomic128.rst b/llvm/docs/AMDGPU/gfx10_vdata_10.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx8_data_buf_atomic128.rst rename to llvm/docs/AMDGPU/gfx10_vdata_10.rst index 40b6d3a236e8..31de91bc006f 100644 --- a/llvm/docs/AMDGPU/gfx8_data_buf_atomic128.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_10.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_data_buf_atomic128: +.. _amdgpu_synid_gfx10_vdata_10: vdata -=========================== +===== Input data for an atomic instruction. diff --git a/llvm/docs/AMDGPU/gfx8_vdata128_0.rst b/llvm/docs/AMDGPU/gfx10_vdata_2.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx8_vdata128_0.rst rename to llvm/docs/AMDGPU/gfx10_vdata_2.rst index bf7e3db732b1..3cf264bea247 100644 --- a/llvm/docs/AMDGPU/gfx8_vdata128_0.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_vdata128_0: +.. _amdgpu_synid_gfx10_vdata_2: vdata -=========================== +===== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_vdata96_0.rst b/llvm/docs/AMDGPU/gfx10_vdata_3.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx7_vdata96_0.rst rename to llvm/docs/AMDGPU/gfx10_vdata_3.rst index b9fe5996e535..9b710c01f170 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata96_0.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_vdata96_0: +.. _amdgpu_synid_gfx10_vdata_3: vdata -=========================== +===== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx8_data_mimg_atomic_reg.rst b/llvm/docs/AMDGPU/gfx10_vdata_4.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx8_data_mimg_atomic_reg.rst rename to llvm/docs/AMDGPU/gfx10_vdata_4.rst index 35bcdc379a10..4d922aaf524f 100644 --- a/llvm/docs/AMDGPU/gfx8_data_mimg_atomic_reg.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_4.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_data_mimg_atomic_reg: +.. _amdgpu_synid_gfx10_vdata_4: vdata -=========================== +===== Input data for an atomic instruction. diff --git a/llvm/docs/AMDGPU/gfx8_data_mimg_atomic_cmp.rst b/llvm/docs/AMDGPU/gfx10_vdata_5.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx8_data_mimg_atomic_cmp.rst rename to llvm/docs/AMDGPU/gfx10_vdata_5.rst index 237b91cadfee..f23bb6b6ab29 100644 --- a/llvm/docs/AMDGPU/gfx8_data_mimg_atomic_cmp.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_5.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_data_mimg_atomic_cmp: +.. _amdgpu_synid_gfx10_vdata_5: vdata -=========================== +===== Input data for an atomic instruction. @@ -23,5 +23,4 @@ Optionally may serve as an output data: Note: the surface data format is indicated in the image resource constant but not in the instruction. - *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx10_data_mimg_store_d16.rst b/llvm/docs/AMDGPU/gfx10_vdata_6.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_data_mimg_store_d16.rst rename to llvm/docs/AMDGPU/gfx10_vdata_6.rst index 142b3060422e..af43d4506924 100644 --- a/llvm/docs/AMDGPU/gfx10_data_mimg_store_d16.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_6.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_data_mimg_store_d16: +.. _amdgpu_synid_gfx10_vdata_6: vdata -=========================== +===== Image data to store by an *image_store* instruction. @@ -17,5 +17,4 @@ Image data to store by an *image_store* instruction. * :ref:`dmask` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16`. * :ref:`d16` specifies that data in registers are packed; each value occupies 16 bits. - *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx7_data_mimg_store.rst b/llvm/docs/AMDGPU/gfx10_vdata_7.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx7_data_mimg_store.rst rename to llvm/docs/AMDGPU/gfx10_vdata_7.rst index 1858547a7c0c..e157fb2b98e6 100644 --- a/llvm/docs/AMDGPU/gfx7_data_mimg_store.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_7.rst @@ -5,14 +5,13 @@ * * ************************************************** -.. _amdgpu_synid7_data_mimg_store: +.. _amdgpu_synid_gfx10_vdata_7: vdata -=========================== +===== Image data to store by an *image_store* instruction. *Size:* depends on :ref:`dmask` which may specify from 1 to 4 data elements. Each data element occupies 1 dword. - *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx7_data_buf_atomic32.rst b/llvm/docs/AMDGPU/gfx10_vdata_8.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx7_data_buf_atomic32.rst rename to llvm/docs/AMDGPU/gfx10_vdata_8.rst index df4a6e42ad45..83cefb82b62f 100644 --- a/llvm/docs/AMDGPU/gfx7_data_buf_atomic32.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_8.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_data_buf_atomic32: +.. _amdgpu_synid_gfx10_vdata_8: vdata -=========================== +===== Input data for an atomic instruction. diff --git a/llvm/docs/AMDGPU/gfx8_data_buf_atomic64.rst b/llvm/docs/AMDGPU/gfx10_vdata_9.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx8_data_buf_atomic64.rst rename to llvm/docs/AMDGPU/gfx10_vdata_9.rst index 107998e37d93..0f0be76806d6 100644 --- a/llvm/docs/AMDGPU/gfx8_data_buf_atomic64.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_9.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_data_buf_atomic64: +.. _amdgpu_synid_gfx10_vdata_9: vdata -=========================== +===== Input data for an atomic instruction. diff --git a/llvm/docs/AMDGPU/gfx8_vdst32_0.rst b/llvm/docs/AMDGPU/gfx10_vdst.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx8_vdst32_0.rst rename to llvm/docs/AMDGPU/gfx10_vdst.rst index 781fcb6ec35b..d541d96ba30f 100644 --- a/llvm/docs/AMDGPU/gfx8_vdst32_0.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_vdst32_0: +.. _amdgpu_synid_gfx10_vdst: vdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx8_vdst64_0.rst b/llvm/docs/AMDGPU/gfx10_vdst_1.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx8_vdst64_0.rst rename to llvm/docs/AMDGPU/gfx10_vdst_1.rst index af2dfe9bf38c..45ab7f51b9bc 100644 --- a/llvm/docs/AMDGPU/gfx8_vdst64_0.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_vdst64_0: +.. _amdgpu_synid_gfx10_vdst_1: vdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx7_dst_buf_64.rst b/llvm/docs/AMDGPU/gfx10_vdst_10.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx7_dst_buf_64.rst rename to llvm/docs/AMDGPU/gfx10_vdst_10.rst index de62a568bf5f..063c5e300452 100644 --- a/llvm/docs/AMDGPU/gfx7_dst_buf_64.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_10.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_dst_buf_64: +.. _amdgpu_synid_gfx10_vdst_10: vdst -=========================== +==== Instruction output: data read from a memory buffer. diff --git a/llvm/docs/AMDGPU/gfx8_dst_buf_96.rst b/llvm/docs/AMDGPU/gfx10_vdst_11.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx8_dst_buf_96.rst rename to llvm/docs/AMDGPU/gfx10_vdst_11.rst index 0012c1a88d30..4b63e79402c6 100644 --- a/llvm/docs/AMDGPU/gfx8_dst_buf_96.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_11.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_dst_buf_96: +.. _amdgpu_synid_gfx10_vdst_11: vdst -=========================== +==== Instruction output: data read from a memory buffer. diff --git a/llvm/docs/AMDGPU/gfx7_dst_buf_128.rst b/llvm/docs/AMDGPU/gfx10_vdst_12.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx7_dst_buf_128.rst rename to llvm/docs/AMDGPU/gfx10_vdst_12.rst index 701616ed3201..95948c1b2adf 100644 --- a/llvm/docs/AMDGPU/gfx7_dst_buf_128.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_12.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_dst_buf_128: +.. _amdgpu_synid_gfx10_vdst_12: vdst -=========================== +==== Instruction output: data read from a memory buffer. diff --git a/llvm/docs/AMDGPU/gfx8_dst_buf_lds.rst b/llvm/docs/AMDGPU/gfx10_vdst_13.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx8_dst_buf_lds.rst rename to llvm/docs/AMDGPU/gfx10_vdst_13.rst index b1cb1458dfac..49230f4231ce 100644 --- a/llvm/docs/AMDGPU/gfx8_dst_buf_lds.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_13.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_dst_buf_lds: +.. _amdgpu_synid_gfx10_vdst_13: vdst -=========================== +==== Instruction output: data read from a memory buffer. diff --git a/llvm/docs/AMDGPU/gfx8_vdst128_0.rst b/llvm/docs/AMDGPU/gfx10_vdst_2.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx8_vdst128_0.rst rename to llvm/docs/AMDGPU/gfx10_vdst_2.rst index 1eccc9523092..31ead59c2c72 100644 --- a/llvm/docs/AMDGPU/gfx8_vdst128_0.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_vdst128_0: +.. _amdgpu_synid_gfx10_vdst_2: vdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx7_vdst96_0.rst b/llvm/docs/AMDGPU/gfx10_vdst_3.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx7_vdst96_0.rst rename to llvm/docs/AMDGPU/gfx10_vdst_3.rst index 3c5bf880ce99..c910a331c03d 100644 --- a/llvm/docs/AMDGPU/gfx7_vdst96_0.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_vdst96_0: +.. _amdgpu_synid_gfx10_vdst_3: vdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx8_dst_flat_atomic32.rst b/llvm/docs/AMDGPU/gfx10_vdst_4.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx8_dst_flat_atomic32.rst rename to llvm/docs/AMDGPU/gfx10_vdst_4.rst index a8ae4646ae98..9f906f683248 100644 --- a/llvm/docs/AMDGPU/gfx8_dst_flat_atomic32.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_4.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_dst_flat_atomic32: +.. _amdgpu_synid_gfx10_vdst_4: vdst -=========================== +==== Data returned by a 32-bit atomic flat instruction. diff --git a/llvm/docs/AMDGPU/gfx7_dst_flat_atomic64.rst b/llvm/docs/AMDGPU/gfx10_vdst_5.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx7_dst_flat_atomic64.rst rename to llvm/docs/AMDGPU/gfx10_vdst_5.rst index cb1fddd93187..3aca2c1edc85 100644 --- a/llvm/docs/AMDGPU/gfx7_dst_flat_atomic64.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_5.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_dst_flat_atomic64: +.. _amdgpu_synid_gfx10_vdst_5: vdst -=========================== +==== Data returned by a 64-bit atomic flat instruction. diff --git a/llvm/docs/AMDGPU/gfx10_dst_mimg_gather4.rst b/llvm/docs/AMDGPU/gfx10_vdst_6.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_dst_mimg_gather4.rst rename to llvm/docs/AMDGPU/gfx10_vdst_6.rst index 90b859353880..c0ac63b7d514 100644 --- a/llvm/docs/AMDGPU/gfx10_dst_mimg_gather4.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_6.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_dst_mimg_gather4: +.. _amdgpu_synid_gfx10_vdst_6: vdst -=========================== +==== Image data to load by an *image_gather4* instruction. diff --git a/llvm/docs/AMDGPU/gfx7_dst_mimg_regular.rst b/llvm/docs/AMDGPU/gfx10_vdst_7.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx7_dst_mimg_regular.rst rename to llvm/docs/AMDGPU/gfx10_vdst_7.rst index aa165b81e621..425edaed52e7 100644 --- a/llvm/docs/AMDGPU/gfx7_dst_mimg_regular.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_7.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_dst_mimg_regular: +.. _amdgpu_synid_gfx10_vdst_7: vdst -=========================== +==== Image data to load by an image instruction. diff --git a/llvm/docs/AMDGPU/gfx10_dst_mimg_regular_d16.rst b/llvm/docs/AMDGPU/gfx10_vdst_8.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_dst_mimg_regular_d16.rst rename to llvm/docs/AMDGPU/gfx10_vdst_8.rst index 9217574c9c42..1790e061d945 100644 --- a/llvm/docs/AMDGPU/gfx10_dst_mimg_regular_d16.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_8.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_dst_mimg_regular_d16: +.. _amdgpu_synid_gfx10_vdst_8: vdst -=========================== +==== Image data to load by an image instruction. @@ -18,5 +18,4 @@ Image data to load by an image instruction. * :ref:`d16` specifies that data elements in registers are packed; each value occupies 16 bits. * :ref:`tfe` adds 1 dword if specified. - *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx7_dst_buf_32.rst b/llvm/docs/AMDGPU/gfx10_vdst_9.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx7_dst_buf_32.rst rename to llvm/docs/AMDGPU/gfx10_vdst_9.rst index 101941195d5d..3d3cde2c2d6e 100644 --- a/llvm/docs/AMDGPU/gfx7_dst_buf_32.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_9.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_dst_buf_32: +.. _amdgpu_synid_gfx10_vdst_9: vdst -=========================== +==== Instruction output: data read from a memory buffer. diff --git a/llvm/docs/AMDGPU/gfx7_vsrc32_0.rst b/llvm/docs/AMDGPU/gfx10_vsrc.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx7_vsrc32_0.rst rename to llvm/docs/AMDGPU/gfx10_vsrc.rst index 93b12b00a1c7..48af0a29a717 100644 --- a/llvm/docs/AMDGPU/gfx7_vsrc32_0.rst +++ b/llvm/docs/AMDGPU/gfx10_vsrc.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_vsrc32_0: +.. _amdgpu_synid_gfx10_vsrc: vsrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx8_src_exp.rst b/llvm/docs/AMDGPU/gfx10_vsrc_1.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx8_src_exp.rst rename to llvm/docs/AMDGPU/gfx10_vsrc_1.rst index 10449b4e36e8..8e6a7ba370c4 100644 --- a/llvm/docs/AMDGPU/gfx8_src_exp.rst +++ b/llvm/docs/AMDGPU/gfx10_vsrc_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_src_exp: +.. _amdgpu_synid_gfx10_vsrc_1: vsrc -=========================== +==== Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off` if not used. diff --git a/llvm/docs/AMDGPU/gfx7_vsrc128_0.rst b/llvm/docs/AMDGPU/gfx10_vsrc_2.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx7_vsrc128_0.rst rename to llvm/docs/AMDGPU/gfx10_vsrc_2.rst index 975237916bb6..67ef71bdeb7e 100644 --- a/llvm/docs/AMDGPU/gfx7_vsrc128_0.rst +++ b/llvm/docs/AMDGPU/gfx10_vsrc_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_vsrc128_0: +.. _amdgpu_synid_gfx10_vsrc_2: vsrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx8_vsrc64_0.rst b/llvm/docs/AMDGPU/gfx10_vsrc_3.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx8_vsrc64_0.rst rename to llvm/docs/AMDGPU/gfx10_vsrc_3.rst index 7c2c39ff7530..5ea851bf1fe1 100644 --- a/llvm/docs/AMDGPU/gfx8_vsrc64_0.rst +++ b/llvm/docs/AMDGPU/gfx10_vsrc_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_vsrc64_0: +.. _amdgpu_synid_gfx10_vsrc_3: vsrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_waitcnt.rst b/llvm/docs/AMDGPU/gfx10_waitcnt.rst index 1a7126400dd5..405d94ab93df 100644 --- a/llvm/docs/AMDGPU/gfx10_waitcnt.rst +++ b/llvm/docs/AMDGPU/gfx10_waitcnt.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_waitcnt: +.. _amdgpu_synid_gfx10_waitcnt: waitcnt -=========================== +======= Counts of outstanding instructions to wait for. diff --git a/llvm/docs/AMDGPU/gfx7_attr.rst b/llvm/docs/AMDGPU/gfx7_attr.rst index 2257f4e1f320..e4a7c80d485e 100644 --- a/llvm/docs/AMDGPU/gfx7_attr.rst +++ b/llvm/docs/AMDGPU/gfx7_attr.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_attr: +.. _amdgpu_synid_gfx7_attr: attr -=========================== +==== Interpolation attribute and channel: diff --git a/llvm/docs/AMDGPU/gfx8_ret.rst b/llvm/docs/AMDGPU/gfx7_dst.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx8_ret.rst rename to llvm/docs/AMDGPU/gfx7_dst.rst index b4b89d8e6477..54ca5f6f6c3e 100644 --- a/llvm/docs/AMDGPU/gfx8_ret.rst +++ b/llvm/docs/AMDGPU/gfx7_dst.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid8_ret: +.. _amdgpu_synid_gfx7_dst: dst -=========================== +=== This is an input operand. It may optionally serve as a destination if :ref:`glc` is specified. diff --git a/llvm/docs/AMDGPU/gfx7_hwreg.rst b/llvm/docs/AMDGPU/gfx7_hwreg.rst index 6f7d71e519df..06e65cbf73b8 100644 --- a/llvm/docs/AMDGPU/gfx7_hwreg.rst +++ b/llvm/docs/AMDGPU/gfx7_hwreg.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_hwreg: +.. _amdgpu_synid_gfx7_hwreg: hwreg -=========================== +===== Bits of a hardware register being accessed. diff --git a/llvm/docs/AMDGPU/gfx8_simm16.rst b/llvm/docs/AMDGPU/gfx7_imm16.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx8_simm16.rst rename to llvm/docs/AMDGPU/gfx7_imm16.rst index 4155272ebfe8..93f34412616e 100644 --- a/llvm/docs/AMDGPU/gfx8_simm16.rst +++ b/llvm/docs/AMDGPU/gfx7_imm16.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid8_simm16: +.. _amdgpu_synid_gfx7_imm16: imm16 -=========================== +===== An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range -32768..65535. diff --git a/llvm/docs/AMDGPU/gfx7_uimm16.rst b/llvm/docs/AMDGPU/gfx7_imm16_1.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx7_uimm16.rst rename to llvm/docs/AMDGPU/gfx7_imm16_1.rst index a49ddeb554c2..03eab3747795 100644 --- a/llvm/docs/AMDGPU/gfx7_uimm16.rst +++ b/llvm/docs/AMDGPU/gfx7_imm16_1.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid7_uimm16: +.. _amdgpu_synid_gfx7_imm16_1: imm16 -=========================== +===== An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range 0..65535. diff --git a/llvm/docs/AMDGPU/gfx7_bimm16.rst b/llvm/docs/AMDGPU/gfx7_imm16_2.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx7_bimm16.rst rename to llvm/docs/AMDGPU/gfx7_imm16_2.rst index 9b0fb57db376..6f69f65d826c 100644 --- a/llvm/docs/AMDGPU/gfx7_bimm16.rst +++ b/llvm/docs/AMDGPU/gfx7_imm16_2.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid7_bimm16: +.. _amdgpu_synid_gfx7_imm16_2: imm16 -=========================== +===== A 16-bit :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range -32768..65535. diff --git a/llvm/docs/AMDGPU/gfx7_label.rst b/llvm/docs/AMDGPU/gfx7_label.rst index 6c1a685c3ea9..3804a54ee5d8 100644 --- a/llvm/docs/AMDGPU/gfx7_label.rst +++ b/llvm/docs/AMDGPU/gfx7_label.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_label: +.. _amdgpu_synid_gfx7_label: label -=========================== +===== A branch target which is a 16-bit signed integer treated as a PC-relative dword offset. diff --git a/llvm/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst b/llvm/docs/AMDGPU/gfx7_m.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst rename to llvm/docs/AMDGPU/gfx7_m.rst index a3a4c6043833..293fa5a42e97 100644 --- a/llvm/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst +++ b/llvm/docs/AMDGPU/gfx7_m.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid8_mod_vop3_abs_neg: +.. _amdgpu_synid_gfx7_m: m -=========================== += This operand may be used with floating point operand modifiers :ref:`abs` and :ref:`neg`. diff --git a/llvm/docs/AMDGPU/gfx7_msg.rst b/llvm/docs/AMDGPU/gfx7_msg.rst index 72a895ef5b36..7f73a24a6e80 100644 --- a/llvm/docs/AMDGPU/gfx7_msg.rst +++ b/llvm/docs/AMDGPU/gfx7_msg.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_msg: +.. _amdgpu_synid_gfx7_msg: msg -=========================== +=== A 16-bit message code. The bits of this operand have the following meaning: @@ -91,4 +91,3 @@ Examples: stream = 1 s_sendmsg sendmsg(msg, op, stream) s_sendmsg sendmsg(2, GS_OP_CUT) - diff --git a/llvm/docs/AMDGPU/gfx7_opt.rst b/llvm/docs/AMDGPU/gfx7_opt.rst index d7e59463464b..68fa73531f12 100644 --- a/llvm/docs/AMDGPU/gfx7_opt.rst +++ b/llvm/docs/AMDGPU/gfx7_opt.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid7_opt: +.. _amdgpu_synid_gfx7_opt: opt -=========================== +=== This is an optional operand. It must be used if and only if :ref:`glc` is specified. diff --git a/llvm/docs/AMDGPU/gfx7_param.rst b/llvm/docs/AMDGPU/gfx7_param.rst index e3f9dd23a93a..48dc30e80f1d 100644 --- a/llvm/docs/AMDGPU/gfx7_param.rst +++ b/llvm/docs/AMDGPU/gfx7_param.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_param: +.. _amdgpu_synid_gfx7_param: param -=========================== +===== Interpolation parameter to read: diff --git a/llvm/docs/AMDGPU/gfx8_base_smem_buf.rst b/llvm/docs/AMDGPU/gfx7_sbase.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx8_base_smem_buf.rst rename to llvm/docs/AMDGPU/gfx7_sbase.rst index fb243d0f262f..d945b6755ac1 100644 --- a/llvm/docs/AMDGPU/gfx8_base_smem_buf.rst +++ b/llvm/docs/AMDGPU/gfx7_sbase.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_base_smem_buf: +.. _amdgpu_synid_gfx7_sbase: sbase -=========================== +===== A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride. diff --git a/llvm/docs/AMDGPU/gfx7_base_smem_addr.rst b/llvm/docs/AMDGPU/gfx7_sbase_1.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx7_base_smem_addr.rst rename to llvm/docs/AMDGPU/gfx7_sbase_1.rst index 9cc3cc71fdf7..4b40f0063244 100644 --- a/llvm/docs/AMDGPU/gfx7_base_smem_addr.rst +++ b/llvm/docs/AMDGPU/gfx7_sbase_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_base_smem_addr: +.. _amdgpu_synid_gfx7_sbase_1: sbase -=========================== +===== A 64-bit base address for scalar memory operations. diff --git a/llvm/docs/AMDGPU/gfx7_sdst32_0.rst b/llvm/docs/AMDGPU/gfx7_sdst.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx7_sdst32_0.rst rename to llvm/docs/AMDGPU/gfx7_sdst.rst index 183d89f9e906..088ff959b18e 100644 --- a/llvm/docs/AMDGPU/gfx7_sdst32_0.rst +++ b/llvm/docs/AMDGPU/gfx7_sdst.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_sdst32_0: +.. _amdgpu_synid_gfx7_sdst: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx7_sdst512_0.rst b/llvm/docs/AMDGPU/gfx7_sdst_1.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx7_sdst512_0.rst rename to llvm/docs/AMDGPU/gfx7_sdst_1.rst index d8c64b1e395c..82b0454680fb 100644 --- a/llvm/docs/AMDGPU/gfx7_sdst512_0.rst +++ b/llvm/docs/AMDGPU/gfx7_sdst_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_sdst512_0: +.. _amdgpu_synid_gfx7_sdst_1: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx7_sdst64_0.rst b/llvm/docs/AMDGPU/gfx7_sdst_2.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx7_sdst64_0.rst rename to llvm/docs/AMDGPU/gfx7_sdst_2.rst index af608801b390..cdf6029e77ba 100644 --- a/llvm/docs/AMDGPU/gfx7_sdst64_0.rst +++ b/llvm/docs/AMDGPU/gfx7_sdst_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_sdst64_0: +.. _amdgpu_synid_gfx7_sdst_2: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx7_sdst128_0.rst b/llvm/docs/AMDGPU/gfx7_sdst_3.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx7_sdst128_0.rst rename to llvm/docs/AMDGPU/gfx7_sdst_3.rst index 735a30cefd62..e621ec41a75b 100644 --- a/llvm/docs/AMDGPU/gfx7_sdst128_0.rst +++ b/llvm/docs/AMDGPU/gfx7_sdst_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_sdst128_0: +.. _amdgpu_synid_gfx7_sdst_3: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx7_sdst256_0.rst b/llvm/docs/AMDGPU/gfx7_sdst_4.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx7_sdst256_0.rst rename to llvm/docs/AMDGPU/gfx7_sdst_4.rst index c4e6f9fcf662..ab37adfa92f4 100644 --- a/llvm/docs/AMDGPU/gfx7_sdst256_0.rst +++ b/llvm/docs/AMDGPU/gfx7_sdst_4.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_sdst256_0: +.. _amdgpu_synid_gfx7_sdst_4: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx7_sdst32_1.rst b/llvm/docs/AMDGPU/gfx7_sdst_5.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx7_sdst32_1.rst rename to llvm/docs/AMDGPU/gfx7_sdst_5.rst index 2e49e20f9d5c..afa7d4322420 100644 --- a/llvm/docs/AMDGPU/gfx7_sdst32_1.rst +++ b/llvm/docs/AMDGPU/gfx7_sdst_5.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_sdst32_1: +.. _amdgpu_synid_gfx7_sdst_5: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx7_sdst64_1.rst b/llvm/docs/AMDGPU/gfx7_sdst_6.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx7_sdst64_1.rst rename to llvm/docs/AMDGPU/gfx7_sdst_6.rst index 207df73932ca..5fe3d5950b8c 100644 --- a/llvm/docs/AMDGPU/gfx7_sdst64_1.rst +++ b/llvm/docs/AMDGPU/gfx7_sdst_6.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_sdst64_1: +.. _amdgpu_synid_gfx7_sdst_6: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx7_sdst32_2.rst b/llvm/docs/AMDGPU/gfx7_sdst_7.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx7_sdst32_2.rst rename to llvm/docs/AMDGPU/gfx7_sdst_7.rst index 8212e5d7a612..20455beaccc5 100644 --- a/llvm/docs/AMDGPU/gfx7_sdst32_2.rst +++ b/llvm/docs/AMDGPU/gfx7_sdst_7.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_sdst32_2: +.. _amdgpu_synid_gfx7_sdst_7: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx7_bimm32.rst b/llvm/docs/AMDGPU/gfx7_simm32.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx7_bimm32.rst rename to llvm/docs/AMDGPU/gfx7_simm32.rst index c4ffef8bcdec..885d77fa0bbb 100644 --- a/llvm/docs/AMDGPU/gfx7_bimm32.rst +++ b/llvm/docs/AMDGPU/gfx7_simm32.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid7_bimm32: +.. _amdgpu_synid_gfx7_simm32: -imm32 -=========================== +simm32 +====== An :ref:`integer_number` or an :ref:`absolute_expression`. The value is truncated to 32 bits. diff --git a/llvm/docs/AMDGPU/gfx7_fimm32.rst b/llvm/docs/AMDGPU/gfx7_simm32_1.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx7_fimm32.rst rename to llvm/docs/AMDGPU/gfx7_simm32_1.rst index b086074604c6..bf25074104c9 100644 --- a/llvm/docs/AMDGPU/gfx7_fimm32.rst +++ b/llvm/docs/AMDGPU/gfx7_simm32_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_fimm32: +.. _amdgpu_synid_gfx7_simm32_1: -imm32 -=========================== +simm32 +====== A :ref:`floating-point_number`, an :ref:`integer_number`, or an :ref:`absolute_expression`. The value is converted to *f32* as described :ref:`here`. diff --git a/llvm/docs/AMDGPU/gfx7_offset_buf.rst b/llvm/docs/AMDGPU/gfx7_soffset.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx7_offset_buf.rst rename to llvm/docs/AMDGPU/gfx7_soffset.rst index b78affa6db67..b8c24a5b5be8 100644 --- a/llvm/docs/AMDGPU/gfx7_offset_buf.rst +++ b/llvm/docs/AMDGPU/gfx7_soffset.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_offset_buf: +.. _amdgpu_synid_gfx7_soffset: soffset -=========================== +======= An unsigned byte offset. diff --git a/llvm/docs/AMDGPU/gfx7_offset_smem.rst b/llvm/docs/AMDGPU/gfx7_soffset_1.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx7_offset_smem.rst rename to llvm/docs/AMDGPU/gfx7_soffset_1.rst index 85ed5f186737..6899bb0b8003 100644 --- a/llvm/docs/AMDGPU/gfx7_offset_smem.rst +++ b/llvm/docs/AMDGPU/gfx7_soffset_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_offset_smem: +.. _amdgpu_synid_gfx7_soffset_1: soffset -=========================== +======= An unsigned offset added to the base address to get memory address. diff --git a/llvm/docs/AMDGPU/gfx7_src32_0.rst b/llvm/docs/AMDGPU/gfx7_src.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_src32_0.rst rename to llvm/docs/AMDGPU/gfx7_src.rst index 6a9c977a3a10..eccbf6b712df 100644 --- a/llvm/docs/AMDGPU/gfx7_src32_0.rst +++ b/llvm/docs/AMDGPU/gfx7_src.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_src32_0: +.. _amdgpu_synid_gfx7_src: src -=========================== +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_src64_2.rst b/llvm/docs/AMDGPU/gfx7_src64_2.rst deleted file mode 100644 index 4a50df7046d9..000000000000 --- a/llvm/docs/AMDGPU/gfx7_src64_2.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid7_src64_2: - -src -=========================== - -Instruction input. - -*Size:* 2 dwords. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`vcc`, :ref:`trap`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst` diff --git a/llvm/docs/AMDGPU/gfx7_src64_0.rst b/llvm/docs/AMDGPU/gfx7_src_1.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx7_src64_0.rst rename to llvm/docs/AMDGPU/gfx7_src_1.rst index 9088418da5b7..dfe7971f0cb4 100644 --- a/llvm/docs/AMDGPU/gfx7_src64_0.rst +++ b/llvm/docs/AMDGPU/gfx7_src_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_src64_0: +.. _amdgpu_synid_gfx7_src_1: src -=========================== +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_src32_6.rst b/llvm/docs/AMDGPU/gfx7_src_10.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx7_src32_6.rst rename to llvm/docs/AMDGPU/gfx7_src_10.rst index 8c49d5954d0d..4d02fd9f66a6 100644 --- a/llvm/docs/AMDGPU/gfx7_src32_6.rst +++ b/llvm/docs/AMDGPU/gfx7_src_10.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_src32_6: +.. _amdgpu_synid_gfx7_src_10: src -=========================== +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_src_2.rst b/llvm/docs/AMDGPU/gfx7_src_2.rst new file mode 100644 index 000000000000..58cdec53bcbe --- /dev/null +++ b/llvm/docs/AMDGPU/gfx7_src_2.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx7_src_2: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`iconst`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx8_vsrc32_1.rst b/llvm/docs/AMDGPU/gfx7_src_3.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx8_vsrc32_1.rst rename to llvm/docs/AMDGPU/gfx7_src_3.rst index 5ed15a15226d..6d1593c64b97 100644 --- a/llvm/docs/AMDGPU/gfx8_vsrc32_1.rst +++ b/llvm/docs/AMDGPU/gfx7_src_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_vsrc32_1: +.. _amdgpu_synid_gfx7_src_3: -vsrc -=========================== +src +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_src32_2.rst b/llvm/docs/AMDGPU/gfx7_src_4.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx7_src32_2.rst rename to llvm/docs/AMDGPU/gfx7_src_4.rst index 2fdb6462cc40..9dc4da37aa07 100644 --- a/llvm/docs/AMDGPU/gfx7_src32_2.rst +++ b/llvm/docs/AMDGPU/gfx7_src_4.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_src32_2: +.. _amdgpu_synid_gfx7_src_4: src -=========================== +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_src32_3.rst b/llvm/docs/AMDGPU/gfx7_src_5.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_src32_3.rst rename to llvm/docs/AMDGPU/gfx7_src_5.rst index 19bbde9c7853..2b0160614911 100644 --- a/llvm/docs/AMDGPU/gfx7_src32_3.rst +++ b/llvm/docs/AMDGPU/gfx7_src_5.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_src32_3: +.. _amdgpu_synid_gfx7_src_5: src -=========================== +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_src32_4.rst b/llvm/docs/AMDGPU/gfx7_src_6.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx7_src32_4.rst rename to llvm/docs/AMDGPU/gfx7_src_6.rst index 7b0c3a89c1a8..8c81e4c27cfa 100644 --- a/llvm/docs/AMDGPU/gfx7_src32_4.rst +++ b/llvm/docs/AMDGPU/gfx7_src_6.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_src32_4: +.. _amdgpu_synid_gfx7_src_6: src -=========================== +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_src64_1.rst b/llvm/docs/AMDGPU/gfx7_src_7.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx7_src64_1.rst rename to llvm/docs/AMDGPU/gfx7_src_7.rst index feb657c1f5dd..2087805a2e2e 100644 --- a/llvm/docs/AMDGPU/gfx7_src64_1.rst +++ b/llvm/docs/AMDGPU/gfx7_src_7.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_src64_1: +.. _amdgpu_synid_gfx7_src_7: src -=========================== +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_src32_5.rst b/llvm/docs/AMDGPU/gfx7_src_8.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx7_src32_5.rst rename to llvm/docs/AMDGPU/gfx7_src_8.rst index bcfbaeb013d0..20cc4ab92a4a 100644 --- a/llvm/docs/AMDGPU/gfx7_src32_5.rst +++ b/llvm/docs/AMDGPU/gfx7_src_8.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_src32_5: +.. _amdgpu_synid_gfx7_src_8: src -=========================== +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_src32_1.rst b/llvm/docs/AMDGPU/gfx7_src_9.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_src32_1.rst rename to llvm/docs/AMDGPU/gfx7_src_9.rst index 990d22973c02..d47c69e94f34 100644 --- a/llvm/docs/AMDGPU/gfx7_src32_1.rst +++ b/llvm/docs/AMDGPU/gfx7_src_9.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_src32_1: +.. _amdgpu_synid_gfx7_src_9: src -=========================== +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_rsrc_mimg.rst b/llvm/docs/AMDGPU/gfx7_srsrc.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx7_rsrc_mimg.rst rename to llvm/docs/AMDGPU/gfx7_srsrc.rst index b0e40fe09cc6..6579e0343f22 100644 --- a/llvm/docs/AMDGPU/gfx7_rsrc_mimg.rst +++ b/llvm/docs/AMDGPU/gfx7_srsrc.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_rsrc_mimg: +.. _amdgpu_synid_gfx7_srsrc: srsrc -=========================== +===== Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format. diff --git a/llvm/docs/AMDGPU/gfx7_rsrc_buf.rst b/llvm/docs/AMDGPU/gfx7_srsrc_1.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx7_rsrc_buf.rst rename to llvm/docs/AMDGPU/gfx7_srsrc_1.rst index 7ebcebc68efe..6a365c3b6f65 100644 --- a/llvm/docs/AMDGPU/gfx7_rsrc_buf.rst +++ b/llvm/docs/AMDGPU/gfx7_srsrc_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_rsrc_buf: +.. _amdgpu_synid_gfx7_srsrc_1: srsrc -=========================== +===== Buffer resource constant which defines the address and characteristics of the buffer in memory. diff --git a/llvm/docs/AMDGPU/gfx7_samp_mimg.rst b/llvm/docs/AMDGPU/gfx7_ssamp.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx7_samp_mimg.rst rename to llvm/docs/AMDGPU/gfx7_ssamp.rst index 738cad415fef..59ce8ee1c9c8 100644 --- a/llvm/docs/AMDGPU/gfx7_samp_mimg.rst +++ b/llvm/docs/AMDGPU/gfx7_ssamp.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_samp_mimg: +.. _amdgpu_synid_gfx7_ssamp: ssamp -=========================== +===== Sampler constant used to specify filtering options applied to the image data after it is read. diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_0.rst b/llvm/docs/AMDGPU/gfx7_ssrc.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx7_ssrc32_0.rst rename to llvm/docs/AMDGPU/gfx7_ssrc.rst index 589d9ccd9781..d06a69b5ab91 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc32_0.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_ssrc32_0: +.. _amdgpu_synid_gfx7_ssrc: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_ssrc64_0.rst b/llvm/docs/AMDGPU/gfx7_ssrc_1.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx7_ssrc64_0.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_1.rst index 49add61fc94b..51e92de67671 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc64_0.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_ssrc64_0: +.. _amdgpu_synid_gfx7_ssrc_1: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_6.rst b/llvm/docs/AMDGPU/gfx7_ssrc_10.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_ssrc32_6.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_10.rst index 32bc30585907..cbd9ad6494cf 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc32_6.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_10.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_ssrc32_6: +.. _amdgpu_synid_gfx7_ssrc_10: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_1.rst b/llvm/docs/AMDGPU/gfx7_ssrc_2.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_ssrc32_1.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_2.rst index 4f04b0bc2256..c0e6cb9b952b 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc32_1.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_ssrc32_1: +.. _amdgpu_synid_gfx7_ssrc_2: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_2.rst b/llvm/docs/AMDGPU/gfx7_ssrc_3.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx7_ssrc32_2.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_3.rst index c7ff032f8800..5ac692aadc81 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc32_2.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_ssrc32_2: +.. _amdgpu_synid_gfx7_ssrc_3: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_ssrc64_1.rst b/llvm/docs/AMDGPU/gfx7_ssrc_4.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx7_ssrc64_1.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_4.rst index 42dc8c569061..65ffe4ea7285 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc64_1.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_4.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_ssrc64_1: +.. _amdgpu_synid_gfx7_ssrc_4: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_3.rst b/llvm/docs/AMDGPU/gfx7_ssrc_5.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx7_ssrc32_3.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_5.rst index 2ec4af2f6d55..09a9a3516d84 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc32_3.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_5.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_ssrc32_3: +.. _amdgpu_synid_gfx7_ssrc_5: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_ssrc64_2.rst b/llvm/docs/AMDGPU/gfx7_ssrc_6.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_ssrc64_2.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_6.rst index 525593055465..48371b757b7a 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc64_2.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_6.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_ssrc64_2: +.. _amdgpu_synid_gfx7_ssrc_6: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_ssrc64_3.rst b/llvm/docs/AMDGPU/gfx7_ssrc_7.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx7_ssrc64_3.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_7.rst index 173f550d4ec9..5070fae33bbe 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc64_3.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_7.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_ssrc64_3: +.. _amdgpu_synid_gfx7_ssrc_7: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_4.rst b/llvm/docs/AMDGPU/gfx7_ssrc_8.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx7_ssrc32_4.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_8.rst index e07ffe5a9ec2..ff277d502ed7 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc32_4.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_8.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_ssrc32_4: +.. _amdgpu_synid_gfx7_ssrc_8: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_5.rst b/llvm/docs/AMDGPU/gfx7_ssrc_9.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx7_ssrc32_5.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_9.rst index 71402a7d000e..5c3d3454a39e 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc32_5.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_9.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_ssrc32_5: +.. _amdgpu_synid_gfx7_ssrc_9: ssrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_tgt.rst b/llvm/docs/AMDGPU/gfx7_tgt.rst index 8413ad1a6f3e..2aaf928a1fb9 100644 --- a/llvm/docs/AMDGPU/gfx7_tgt.rst +++ b/llvm/docs/AMDGPU/gfx7_tgt.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_tgt: +.. _amdgpu_synid_gfx7_tgt: tgt -=========================== +=== An export target: diff --git a/llvm/docs/AMDGPU/gfx8_type_dev.rst b/llvm/docs/AMDGPU/gfx7_type_deviation.rst similarity index 69% rename from llvm/docs/AMDGPU/gfx8_type_dev.rst rename to llvm/docs/AMDGPU/gfx7_type_deviation.rst index cf8f7f7f00e3..876d13df7e4b 100644 --- a/llvm/docs/AMDGPU/gfx8_type_dev.rst +++ b/llvm/docs/AMDGPU/gfx7_type_deviation.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid8_type_dev: +.. _amdgpu_synid_gfx7_type_deviation: -Type deviation -=========================== +Type Deviation +============== -*Type* of this operand differs from *type* :ref:`implied by the opcode`. This tag specifies actual operand *type*. +*Type* of this operand differs from *type* :ref:`implied by the opcode`. This tag specifies actual operand *type*. diff --git a/llvm/docs/AMDGPU/gfx8_addr_ds.rst b/llvm/docs/AMDGPU/gfx7_vaddr.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx8_addr_ds.rst rename to llvm/docs/AMDGPU/gfx7_vaddr.rst index 7115ff0cf043..849fdc6be3f2 100644 --- a/llvm/docs/AMDGPU/gfx8_addr_ds.rst +++ b/llvm/docs/AMDGPU/gfx7_vaddr.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_addr_ds: +.. _amdgpu_synid_gfx7_vaddr: vaddr -=========================== +===== An offset from the start of GDS/LDS memory. diff --git a/llvm/docs/AMDGPU/gfx8_addr_flat.rst b/llvm/docs/AMDGPU/gfx7_vaddr_1.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx8_addr_flat.rst rename to llvm/docs/AMDGPU/gfx7_vaddr_1.rst index 53dfcc3e8950..6cae555658e4 100644 --- a/llvm/docs/AMDGPU/gfx8_addr_flat.rst +++ b/llvm/docs/AMDGPU/gfx7_vaddr_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_addr_flat: +.. _amdgpu_synid_gfx7_vaddr_1: vaddr -=========================== +===== A 64-bit flat address. diff --git a/llvm/docs/AMDGPU/gfx7_addr_mimg.rst b/llvm/docs/AMDGPU/gfx7_vaddr_2.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_addr_mimg.rst rename to llvm/docs/AMDGPU/gfx7_vaddr_2.rst index 76eb4846f1ae..e537a86cecdd 100644 --- a/llvm/docs/AMDGPU/gfx7_addr_mimg.rst +++ b/llvm/docs/AMDGPU/gfx7_vaddr_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_addr_mimg: +.. _amdgpu_synid_gfx7_vaddr_2: vaddr -=========================== +===== Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image. diff --git a/llvm/docs/AMDGPU/gfx7_addr_buf.rst b/llvm/docs/AMDGPU/gfx7_vaddr_3.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx7_addr_buf.rst rename to llvm/docs/AMDGPU/gfx7_vaddr_3.rst index 22dc7d353385..f2721b69139f 100644 --- a/llvm/docs/AMDGPU/gfx7_addr_buf.rst +++ b/llvm/docs/AMDGPU/gfx7_vaddr_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_addr_buf: +.. _amdgpu_synid_gfx7_vaddr_3: vaddr -=========================== +===== This is an optional operand which may specify a 64-bit address, offset and/or index. diff --git a/llvm/docs/AMDGPU/gfx7_vcc_64.rst b/llvm/docs/AMDGPU/gfx7_vcc.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx7_vcc_64.rst rename to llvm/docs/AMDGPU/gfx7_vcc.rst index b1285e0e8b8d..9f873e1f49bf 100644 --- a/llvm/docs/AMDGPU/gfx7_vcc_64.rst +++ b/llvm/docs/AMDGPU/gfx7_vcc.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_vcc_64: +.. _amdgpu_synid_gfx7_vcc: vcc -=========================== +=== Vector condition code. diff --git a/llvm/docs/AMDGPU/gfx7_vdata32_0.rst b/llvm/docs/AMDGPU/gfx7_vdata.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx7_vdata32_0.rst rename to llvm/docs/AMDGPU/gfx7_vdata.rst index 1615abb4f6c3..617ee2a75cef 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata32_0.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_vdata32_0: +.. _amdgpu_synid_gfx7_vdata: vdata -=========================== +===== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_vdata0.rst b/llvm/docs/AMDGPU/gfx7_vdata0.rst new file mode 100644 index 000000000000..42d41a7ad5c7 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx7_vdata0.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx7_vdata0: + +vdata0 +====== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx7_vdata0_1.rst b/llvm/docs/AMDGPU/gfx7_vdata0_1.rst new file mode 100644 index 000000000000..3f4320bb3ef4 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx7_vdata0_1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx7_vdata0_1: + +vdata0 +====== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx7_vdata1.rst b/llvm/docs/AMDGPU/gfx7_vdata1.rst new file mode 100644 index 000000000000..19feb6123cd9 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx7_vdata1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx7_vdata1: + +vdata1 +====== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx7_vdata1_1.rst b/llvm/docs/AMDGPU/gfx7_vdata1_1.rst new file mode 100644 index 000000000000..b0c8a73626e0 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx7_vdata1_1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx7_vdata1_1: + +vdata1 +====== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdata64_0.rst b/llvm/docs/AMDGPU/gfx7_vdata_1.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx8_vdata64_0.rst rename to llvm/docs/AMDGPU/gfx7_vdata_1.rst index 438054456060..dd16f9c54c1d 100644 --- a/llvm/docs/AMDGPU/gfx8_vdata64_0.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_vdata64_0: +.. _amdgpu_synid_gfx7_vdata_1: vdata -=========================== +===== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_vdata128_0.rst b/llvm/docs/AMDGPU/gfx7_vdata_2.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx7_vdata128_0.rst rename to llvm/docs/AMDGPU/gfx7_vdata_2.rst index 5ed2b823bf74..922d7f5f96cc 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata128_0.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_vdata128_0: +.. _amdgpu_synid_gfx7_vdata_2: vdata -=========================== +===== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx8_vdata96_0.rst b/llvm/docs/AMDGPU/gfx7_vdata_3.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx8_vdata96_0.rst rename to llvm/docs/AMDGPU/gfx7_vdata_3.rst index b8ad22d1f24a..2126739309bb 100644 --- a/llvm/docs/AMDGPU/gfx8_vdata96_0.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_vdata96_0: +.. _amdgpu_synid_gfx7_vdata_3: vdata -=========================== +===== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_data_mimg_atomic_reg.rst b/llvm/docs/AMDGPU/gfx7_vdata_4.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_data_mimg_atomic_reg.rst rename to llvm/docs/AMDGPU/gfx7_vdata_4.rst index 30785e47ff98..99cb0406dd40 100644 --- a/llvm/docs/AMDGPU/gfx7_data_mimg_atomic_reg.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_4.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_data_mimg_atomic_reg: +.. _amdgpu_synid_gfx7_vdata_4: vdata -=========================== +===== Input data for an atomic instruction. diff --git a/llvm/docs/AMDGPU/gfx7_data_mimg_atomic_cmp.rst b/llvm/docs/AMDGPU/gfx7_vdata_5.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_data_mimg_atomic_cmp.rst rename to llvm/docs/AMDGPU/gfx7_vdata_5.rst index 0328519d17b6..e5288b96ef5d 100644 --- a/llvm/docs/AMDGPU/gfx7_data_mimg_atomic_cmp.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_5.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_data_mimg_atomic_cmp: +.. _amdgpu_synid_gfx7_vdata_5: vdata -=========================== +===== Input data for an atomic instruction. @@ -23,5 +23,4 @@ Optionally may serve as an output data: Note: the surface data format is indicated in the image resource constant but not in the instruction. - *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_data_mimg_store.rst b/llvm/docs/AMDGPU/gfx7_vdata_6.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx8_data_mimg_store.rst rename to llvm/docs/AMDGPU/gfx7_vdata_6.rst index 65a1a49f67e5..33837702f178 100644 --- a/llvm/docs/AMDGPU/gfx8_data_mimg_store.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_6.rst @@ -5,14 +5,13 @@ * * ************************************************** -.. _amdgpu_synid8_data_mimg_store: +.. _amdgpu_synid_gfx7_vdata_6: vdata -=========================== +===== Image data to store by an *image_store* instruction. *Size:* depends on :ref:`dmask` which may specify from 1 to 4 data elements. Each data element occupies 1 dword. - *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_data_buf_atomic32.rst b/llvm/docs/AMDGPU/gfx7_vdata_7.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx8_data_buf_atomic32.rst rename to llvm/docs/AMDGPU/gfx7_vdata_7.rst index 51121820d740..ef156bca7125 100644 --- a/llvm/docs/AMDGPU/gfx8_data_buf_atomic32.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_7.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_data_buf_atomic32: +.. _amdgpu_synid_gfx7_vdata_7: vdata -=========================== +===== Input data for an atomic instruction. diff --git a/llvm/docs/AMDGPU/gfx7_data_buf_atomic64.rst b/llvm/docs/AMDGPU/gfx7_vdata_8.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx7_data_buf_atomic64.rst rename to llvm/docs/AMDGPU/gfx7_vdata_8.rst index 4892e41631f4..b555bf5782a5 100644 --- a/llvm/docs/AMDGPU/gfx7_data_buf_atomic64.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_8.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_data_buf_atomic64: +.. _amdgpu_synid_gfx7_vdata_8: vdata -=========================== +===== Input data for an atomic instruction. diff --git a/llvm/docs/AMDGPU/gfx7_data_buf_atomic128.rst b/llvm/docs/AMDGPU/gfx7_vdata_9.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx7_data_buf_atomic128.rst rename to llvm/docs/AMDGPU/gfx7_vdata_9.rst index 33ff26c6c594..aa395f203097 100644 --- a/llvm/docs/AMDGPU/gfx7_data_buf_atomic128.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_9.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_data_buf_atomic128: +.. _amdgpu_synid_gfx7_vdata_9: vdata -=========================== +===== Input data for an atomic instruction. diff --git a/llvm/docs/AMDGPU/gfx10_vdst32_0.rst b/llvm/docs/AMDGPU/gfx7_vdst.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx10_vdst32_0.rst rename to llvm/docs/AMDGPU/gfx7_vdst.rst index d04548ec1eae..ec98a49afe0f 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst32_0.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_vdst32_0: +.. _amdgpu_synid_gfx7_vdst: vdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx7_vdst64_0.rst b/llvm/docs/AMDGPU/gfx7_vdst_1.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx7_vdst64_0.rst rename to llvm/docs/AMDGPU/gfx7_vdst_1.rst index 4cacaa0d63f1..4a3b1c7c0241 100644 --- a/llvm/docs/AMDGPU/gfx7_vdst64_0.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_vdst64_0: +.. _amdgpu_synid_gfx7_vdst_1: vdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx7_dst_buf_96.rst b/llvm/docs/AMDGPU/gfx7_vdst_10.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx7_dst_buf_96.rst rename to llvm/docs/AMDGPU/gfx7_vdst_10.rst index 1abfcc07aecf..320d0d0c9849 100644 --- a/llvm/docs/AMDGPU/gfx7_dst_buf_96.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_10.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_dst_buf_96: +.. _amdgpu_synid_gfx7_vdst_10: vdst -=========================== +==== Instruction output: data read from a memory buffer. diff --git a/llvm/docs/AMDGPU/gfx8_dst_buf_128.rst b/llvm/docs/AMDGPU/gfx7_vdst_11.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx8_dst_buf_128.rst rename to llvm/docs/AMDGPU/gfx7_vdst_11.rst index d076c7025f63..3f40c25958ac 100644 --- a/llvm/docs/AMDGPU/gfx8_dst_buf_128.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_11.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_dst_buf_128: +.. _amdgpu_synid_gfx7_vdst_11: vdst -=========================== +==== Instruction output: data read from a memory buffer. diff --git a/llvm/docs/AMDGPU/gfx7_dst_buf_lds.rst b/llvm/docs/AMDGPU/gfx7_vdst_12.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx7_dst_buf_lds.rst rename to llvm/docs/AMDGPU/gfx7_vdst_12.rst index 435f6bb874b4..2f8473800f50 100644 --- a/llvm/docs/AMDGPU/gfx7_dst_buf_lds.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_12.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_dst_buf_lds: +.. _amdgpu_synid_gfx7_vdst_12: vdst -=========================== +==== Instruction output: data read from a memory buffer. diff --git a/llvm/docs/AMDGPU/gfx7_vdst128_0.rst b/llvm/docs/AMDGPU/gfx7_vdst_2.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx7_vdst128_0.rst rename to llvm/docs/AMDGPU/gfx7_vdst_2.rst index c18652e88419..8a4206129c81 100644 --- a/llvm/docs/AMDGPU/gfx7_vdst128_0.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_vdst128_0: +.. _amdgpu_synid_gfx7_vdst_2: vdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx8_vdst96_0.rst b/llvm/docs/AMDGPU/gfx7_vdst_3.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx8_vdst96_0.rst rename to llvm/docs/AMDGPU/gfx7_vdst_3.rst index 4895b6579002..65810a36797d 100644 --- a/llvm/docs/AMDGPU/gfx8_vdst96_0.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_vdst96_0: +.. _amdgpu_synid_gfx7_vdst_3: vdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx7_dst_flat_atomic32.rst b/llvm/docs/AMDGPU/gfx7_vdst_4.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx7_dst_flat_atomic32.rst rename to llvm/docs/AMDGPU/gfx7_vdst_4.rst index 4a85656ca86d..4aebd9230eec 100644 --- a/llvm/docs/AMDGPU/gfx7_dst_flat_atomic32.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_4.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_dst_flat_atomic32: +.. _amdgpu_synid_gfx7_vdst_4: vdst -=========================== +==== Data returned by a 32-bit atomic flat instruction. diff --git a/llvm/docs/AMDGPU/gfx8_dst_flat_atomic64.rst b/llvm/docs/AMDGPU/gfx7_vdst_5.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx8_dst_flat_atomic64.rst rename to llvm/docs/AMDGPU/gfx7_vdst_5.rst index 5b46e88f5610..b57b2f7ba2d9 100644 --- a/llvm/docs/AMDGPU/gfx8_dst_flat_atomic64.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_5.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_dst_flat_atomic64: +.. _amdgpu_synid_gfx7_vdst_5: vdst -=========================== +==== Data returned by a 64-bit atomic flat instruction. diff --git a/llvm/docs/AMDGPU/gfx7_dst_mimg_gather4.rst b/llvm/docs/AMDGPU/gfx7_vdst_6.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx7_dst_mimg_gather4.rst rename to llvm/docs/AMDGPU/gfx7_vdst_6.rst index 17fcff5246a3..2fa85a24e39d 100644 --- a/llvm/docs/AMDGPU/gfx7_dst_mimg_gather4.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_6.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_dst_mimg_gather4: +.. _amdgpu_synid_gfx7_vdst_6: vdst -=========================== +==== Image data to load by an *image_gather4* instruction. diff --git a/llvm/docs/AMDGPU/gfx8_dst_mimg_regular.rst b/llvm/docs/AMDGPU/gfx7_vdst_7.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx8_dst_mimg_regular.rst rename to llvm/docs/AMDGPU/gfx7_vdst_7.rst index be1037a5ce5a..7d36d7701812 100644 --- a/llvm/docs/AMDGPU/gfx8_dst_mimg_regular.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_7.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_dst_mimg_regular: +.. _amdgpu_synid_gfx7_vdst_7: vdst -=========================== +==== Image data to load by an image instruction. diff --git a/llvm/docs/AMDGPU/gfx8_dst_buf_32.rst b/llvm/docs/AMDGPU/gfx7_vdst_8.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx8_dst_buf_32.rst rename to llvm/docs/AMDGPU/gfx7_vdst_8.rst index e747530d9956..b3361d99ffd7 100644 --- a/llvm/docs/AMDGPU/gfx8_dst_buf_32.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_8.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_dst_buf_32: +.. _amdgpu_synid_gfx7_vdst_8: vdst -=========================== +==== Instruction output: data read from a memory buffer. diff --git a/llvm/docs/AMDGPU/gfx8_dst_buf_64.rst b/llvm/docs/AMDGPU/gfx7_vdst_9.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx8_dst_buf_64.rst rename to llvm/docs/AMDGPU/gfx7_vdst_9.rst index f5da65bf5737..6e036fce65f4 100644 --- a/llvm/docs/AMDGPU/gfx8_dst_buf_64.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_9.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_dst_buf_64: +.. _amdgpu_synid_gfx7_vdst_9: vdst -=========================== +==== Instruction output: data read from a memory buffer. diff --git a/llvm/docs/AMDGPU/gfx7_src_exp.rst b/llvm/docs/AMDGPU/gfx7_vsrc.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx7_src_exp.rst rename to llvm/docs/AMDGPU/gfx7_vsrc.rst index 32f71a88b645..98e79945379f 100644 --- a/llvm/docs/AMDGPU/gfx7_src_exp.rst +++ b/llvm/docs/AMDGPU/gfx7_vsrc.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_src_exp: +.. _amdgpu_synid_gfx7_vsrc: vsrc -=========================== +==== Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off` if not used. diff --git a/llvm/docs/AMDGPU/gfx10_vsrc32_0.rst b/llvm/docs/AMDGPU/gfx7_vsrc_1.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx10_vsrc32_0.rst rename to llvm/docs/AMDGPU/gfx7_vsrc_1.rst index 95cecb42825c..f8ed78a4ccb4 100644 --- a/llvm/docs/AMDGPU/gfx10_vsrc32_0.rst +++ b/llvm/docs/AMDGPU/gfx7_vsrc_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_vsrc32_0: +.. _amdgpu_synid_gfx7_vsrc_1: vsrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx8_vsrc128_0.rst b/llvm/docs/AMDGPU/gfx7_vsrc_2.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx8_vsrc128_0.rst rename to llvm/docs/AMDGPU/gfx7_vsrc_2.rst index 25b1794d85f3..77887d65f102 100644 --- a/llvm/docs/AMDGPU/gfx8_vsrc128_0.rst +++ b/llvm/docs/AMDGPU/gfx7_vsrc_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_vsrc128_0: +.. _amdgpu_synid_gfx7_vsrc_2: vsrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_vsrc64_0.rst b/llvm/docs/AMDGPU/gfx7_vsrc_3.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx7_vsrc64_0.rst rename to llvm/docs/AMDGPU/gfx7_vsrc_3.rst index d8c9d45ddb5f..8a4533e4cd27 100644 --- a/llvm/docs/AMDGPU/gfx7_vsrc64_0.rst +++ b/llvm/docs/AMDGPU/gfx7_vsrc_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_vsrc64_0: +.. _amdgpu_synid_gfx7_vsrc_3: vsrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx7_waitcnt.rst b/llvm/docs/AMDGPU/gfx7_waitcnt.rst index b70c8c32deb3..3913770b2b84 100644 --- a/llvm/docs/AMDGPU/gfx7_waitcnt.rst +++ b/llvm/docs/AMDGPU/gfx7_waitcnt.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid7_waitcnt: +.. _amdgpu_synid_gfx7_waitcnt: waitcnt -=========================== +======= Counts of outstanding instructions to wait for. diff --git a/llvm/docs/AMDGPU/gfx8_attr.rst b/llvm/docs/AMDGPU/gfx8_attr.rst index eec2a2de4b3b..55de815f3fcc 100644 --- a/llvm/docs/AMDGPU/gfx8_attr.rst +++ b/llvm/docs/AMDGPU/gfx8_attr.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_attr: +.. _amdgpu_synid_gfx8_attr: attr -=========================== +==== Interpolation attribute and channel: diff --git a/llvm/docs/AMDGPU/gfx10_ret.rst b/llvm/docs/AMDGPU/gfx8_dst.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_ret.rst rename to llvm/docs/AMDGPU/gfx8_dst.rst index 0809f6ca913c..c291d88a3fc5 100644 --- a/llvm/docs/AMDGPU/gfx10_ret.rst +++ b/llvm/docs/AMDGPU/gfx8_dst.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid10_ret: +.. _amdgpu_synid_gfx8_dst: dst -=========================== +=== This is an input operand. It may optionally serve as a destination if :ref:`glc` is specified. diff --git a/llvm/docs/AMDGPU/gfx8_hwreg.rst b/llvm/docs/AMDGPU/gfx8_hwreg.rst index 36e5c588a238..c81af693497b 100644 --- a/llvm/docs/AMDGPU/gfx8_hwreg.rst +++ b/llvm/docs/AMDGPU/gfx8_hwreg.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_hwreg: +.. _amdgpu_synid_gfx8_hwreg: hwreg -=========================== +===== Bits of a hardware register being accessed. diff --git a/llvm/docs/AMDGPU/gfx8_imask.rst b/llvm/docs/AMDGPU/gfx8_imask.rst index 1b0a066faca5..7ee1d16e111a 100644 --- a/llvm/docs/AMDGPU/gfx8_imask.rst +++ b/llvm/docs/AMDGPU/gfx8_imask.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_imask: +.. _amdgpu_synid_gfx8_imask: imask -=========================== +===== This operand is a mask which controls indexing mode for operands of subsequent instructions. Bits 0, 1 and 2 control indexing of *src0*, *src1* and *src2*, while bit 3 controls indexing of *dst*. diff --git a/llvm/docs/AMDGPU/gfx10_simm16.rst b/llvm/docs/AMDGPU/gfx8_imm16.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx10_simm16.rst rename to llvm/docs/AMDGPU/gfx8_imm16.rst index e88003ffaf05..587faae4afaf 100644 --- a/llvm/docs/AMDGPU/gfx10_simm16.rst +++ b/llvm/docs/AMDGPU/gfx8_imm16.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid10_simm16: +.. _amdgpu_synid_gfx8_imm16: imm16 -=========================== +===== An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range -32768..65535. diff --git a/llvm/docs/AMDGPU/gfx10_uimm16.rst b/llvm/docs/AMDGPU/gfx8_imm16_1.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx10_uimm16.rst rename to llvm/docs/AMDGPU/gfx8_imm16_1.rst index 2814a4b836df..b3b62af003c1 100644 --- a/llvm/docs/AMDGPU/gfx10_uimm16.rst +++ b/llvm/docs/AMDGPU/gfx8_imm16_1.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid10_uimm16: +.. _amdgpu_synid_gfx8_imm16_1: imm16 -=========================== +===== An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range 0..65535. diff --git a/llvm/docs/AMDGPU/gfx10_bimm16.rst b/llvm/docs/AMDGPU/gfx8_imm16_2.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx10_bimm16.rst rename to llvm/docs/AMDGPU/gfx8_imm16_2.rst index b871ef27f96c..591bc08e6a79 100644 --- a/llvm/docs/AMDGPU/gfx10_bimm16.rst +++ b/llvm/docs/AMDGPU/gfx8_imm16_2.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid10_bimm16: +.. _amdgpu_synid_gfx8_imm16_2: imm16 -=========================== +===== A 16-bit :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range -32768..65535. diff --git a/llvm/docs/AMDGPU/gfx8_label.rst b/llvm/docs/AMDGPU/gfx8_label.rst index d81fe9f0e2a0..a3d3597021f7 100644 --- a/llvm/docs/AMDGPU/gfx8_label.rst +++ b/llvm/docs/AMDGPU/gfx8_label.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_label: +.. _amdgpu_synid_gfx8_label: label -=========================== +===== A branch target which is a 16-bit signed integer treated as a PC-relative dword offset. diff --git a/llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst b/llvm/docs/AMDGPU/gfx8_m.rst similarity index 85% rename from llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst rename to llvm/docs/AMDGPU/gfx8_m.rst index 15671007c102..43a066b3be7d 100644 --- a/llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst +++ b/llvm/docs/AMDGPU/gfx8_m.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid10_mod_sdwa_sext: +.. _amdgpu_synid_gfx8_m: m -=========================== += This operand may be used with integer operand modifier :ref:`sext`. diff --git a/llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst b/llvm/docs/AMDGPU/gfx8_m_1.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst rename to llvm/docs/AMDGPU/gfx8_m_1.rst index 50c29b66594d..be08cac1f30f 100644 --- a/llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst +++ b/llvm/docs/AMDGPU/gfx8_m_1.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid10_mod_vop3_abs_neg: +.. _amdgpu_synid_gfx8_m_1: m -=========================== += This operand may be used with floating point operand modifiers :ref:`abs` and :ref:`neg`. diff --git a/llvm/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst b/llvm/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst deleted file mode 100644 index 09790e48bc1b..000000000000 --- a/llvm/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst +++ /dev/null @@ -1,13 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_mod_dpp_sdwa_abs_neg: - -m -=========================== - -This operand may be used with floating point operand modifiers :ref:`abs` and :ref:`neg`. diff --git a/llvm/docs/AMDGPU/gfx8_msg.rst b/llvm/docs/AMDGPU/gfx8_msg.rst index f32033dd944c..ac27622dd577 100644 --- a/llvm/docs/AMDGPU/gfx8_msg.rst +++ b/llvm/docs/AMDGPU/gfx8_msg.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_msg: +.. _amdgpu_synid_gfx8_msg: msg -=========================== +=== A 16-bit message code. The bits of this operand have the following meaning: @@ -92,4 +92,3 @@ Examples: stream = 1 s_sendmsg sendmsg(msg, op, stream) s_sendmsg sendmsg(2, GS_OP_CUT) - diff --git a/llvm/docs/AMDGPU/gfx8_opt.rst b/llvm/docs/AMDGPU/gfx8_opt.rst index f9352288d073..2786b136d0a5 100644 --- a/llvm/docs/AMDGPU/gfx8_opt.rst +++ b/llvm/docs/AMDGPU/gfx8_opt.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid8_opt: +.. _amdgpu_synid_gfx8_opt: opt -=========================== +=== This is an optional operand. It must be used if and only if :ref:`glc` is specified. diff --git a/llvm/docs/AMDGPU/gfx8_param.rst b/llvm/docs/AMDGPU/gfx8_param.rst index 90d7eada07d2..59539fa7710f 100644 --- a/llvm/docs/AMDGPU/gfx8_param.rst +++ b/llvm/docs/AMDGPU/gfx8_param.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_param: +.. _amdgpu_synid_gfx8_param: param -=========================== +===== Interpolation parameter to read: diff --git a/llvm/docs/AMDGPU/gfx10_perm_smem.rst b/llvm/docs/AMDGPU/gfx8_probe.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx10_perm_smem.rst rename to llvm/docs/AMDGPU/gfx8_probe.rst index d6b3d07024d5..72c624daf73c 100644 --- a/llvm/docs/AMDGPU/gfx10_perm_smem.rst +++ b/llvm/docs/AMDGPU/gfx8_probe.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_perm_smem: +.. _amdgpu_synid_gfx8_probe: -imm3 -=========================== +probe +===== A bit mask which indicates request permissions. diff --git a/llvm/docs/AMDGPU/gfx8_base_smem_addr.rst b/llvm/docs/AMDGPU/gfx8_sbase.rst similarity index 70% rename from llvm/docs/AMDGPU/gfx8_base_smem_addr.rst rename to llvm/docs/AMDGPU/gfx8_sbase.rst index 81ef25586d6e..d6b8c680df74 100644 --- a/llvm/docs/AMDGPU/gfx8_base_smem_addr.rst +++ b/llvm/docs/AMDGPU/gfx8_sbase.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid8_base_smem_addr: +.. _amdgpu_synid_gfx8_sbase: sbase -=========================== +===== A 64-bit base address for scalar memory operations. *Size:* 2 dwords. -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap` +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap` diff --git a/llvm/docs/AMDGPU/gfx10_base_smem_buf.rst b/llvm/docs/AMDGPU/gfx8_sbase_1.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_base_smem_buf.rst rename to llvm/docs/AMDGPU/gfx8_sbase_1.rst index 00e987d7bb46..ab238e443f1e 100644 --- a/llvm/docs/AMDGPU/gfx10_base_smem_buf.rst +++ b/llvm/docs/AMDGPU/gfx8_sbase_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_base_smem_buf: +.. _amdgpu_synid_gfx8_sbase_1: sbase -=========================== +===== A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride. diff --git a/llvm/docs/AMDGPU/gfx8_sdata32_0.rst b/llvm/docs/AMDGPU/gfx8_sdata.rst similarity index 69% rename from llvm/docs/AMDGPU/gfx8_sdata32_0.rst rename to llvm/docs/AMDGPU/gfx8_sdata.rst index 9ccd7bd8c713..95925242a86a 100644 --- a/llvm/docs/AMDGPU/gfx8_sdata32_0.rst +++ b/llvm/docs/AMDGPU/gfx8_sdata.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid8_sdata32_0: +.. _amdgpu_synid_gfx8_sdata: sdata -=========================== +===== Instruction input. *Size:* 1 dword. -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap` +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap` diff --git a/llvm/docs/AMDGPU/gfx8_sdata64_0.rst b/llvm/docs/AMDGPU/gfx8_sdata_1.rst similarity index 69% rename from llvm/docs/AMDGPU/gfx8_sdata64_0.rst rename to llvm/docs/AMDGPU/gfx8_sdata_1.rst index 8718449228c7..5155ae6029fb 100644 --- a/llvm/docs/AMDGPU/gfx8_sdata64_0.rst +++ b/llvm/docs/AMDGPU/gfx8_sdata_1.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid8_sdata64_0: +.. _amdgpu_synid_gfx8_sdata_1: sdata -=========================== +===== Instruction input. *Size:* 2 dwords. -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap` +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap` diff --git a/llvm/docs/AMDGPU/gfx10_sdata128_0.rst b/llvm/docs/AMDGPU/gfx8_sdata_2.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx10_sdata128_0.rst rename to llvm/docs/AMDGPU/gfx8_sdata_2.rst index 19d6e5bc2eef..31e4fbf852ef 100644 --- a/llvm/docs/AMDGPU/gfx10_sdata128_0.rst +++ b/llvm/docs/AMDGPU/gfx8_sdata_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_sdata128_0: +.. _amdgpu_synid_gfx8_sdata_2: sdata -=========================== +===== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx8_sdst32_0.rst b/llvm/docs/AMDGPU/gfx8_sdst.rst similarity index 69% rename from llvm/docs/AMDGPU/gfx8_sdst32_0.rst rename to llvm/docs/AMDGPU/gfx8_sdst.rst index 44e6cdc8f7f5..8a3d805343f0 100644 --- a/llvm/docs/AMDGPU/gfx8_sdst32_0.rst +++ b/llvm/docs/AMDGPU/gfx8_sdst.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid8_sdst32_0: +.. _amdgpu_synid_gfx8_sdst: sdst -=========================== +==== Instruction output. *Size:* 1 dword. -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap` +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap` diff --git a/llvm/docs/AMDGPU/gfx8_sdst32_1.rst b/llvm/docs/AMDGPU/gfx8_sdst32_1.rst deleted file mode 100644 index 7156225fa3c4..000000000000 --- a/llvm/docs/AMDGPU/gfx8_sdst32_1.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_sdst32_1: - -sdst -=========================== - -Instruction output. - -*Size:* 1 dword. - -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec` diff --git a/llvm/docs/AMDGPU/gfx8_sdst512_0.rst b/llvm/docs/AMDGPU/gfx8_sdst_1.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx8_sdst512_0.rst rename to llvm/docs/AMDGPU/gfx8_sdst_1.rst index 95b82a7d0249..3a874930c235 100644 --- a/llvm/docs/AMDGPU/gfx8_sdst512_0.rst +++ b/llvm/docs/AMDGPU/gfx8_sdst_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_sdst512_0: +.. _amdgpu_synid_gfx8_sdst_1: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx8_sdst64_0.rst b/llvm/docs/AMDGPU/gfx8_sdst_2.rst similarity index 69% rename from llvm/docs/AMDGPU/gfx8_sdst64_0.rst rename to llvm/docs/AMDGPU/gfx8_sdst_2.rst index 9195778a5e82..7cf48d57adca 100644 --- a/llvm/docs/AMDGPU/gfx8_sdst64_0.rst +++ b/llvm/docs/AMDGPU/gfx8_sdst_2.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid8_sdst64_0: +.. _amdgpu_synid_gfx8_sdst_2: sdst -=========================== +==== Instruction output. *Size:* 2 dwords. -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap` +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap` diff --git a/llvm/docs/AMDGPU/gfx10_sdst128_0.rst b/llvm/docs/AMDGPU/gfx8_sdst_3.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx10_sdst128_0.rst rename to llvm/docs/AMDGPU/gfx8_sdst_3.rst index e1bfc693c0ea..2ea72e09fa80 100644 --- a/llvm/docs/AMDGPU/gfx10_sdst128_0.rst +++ b/llvm/docs/AMDGPU/gfx8_sdst_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_sdst128_0: +.. _amdgpu_synid_gfx8_sdst_3: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx10_sdst256_0.rst b/llvm/docs/AMDGPU/gfx8_sdst_4.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx10_sdst256_0.rst rename to llvm/docs/AMDGPU/gfx8_sdst_4.rst index c352bffeebb7..c89b7376176c 100644 --- a/llvm/docs/AMDGPU/gfx10_sdst256_0.rst +++ b/llvm/docs/AMDGPU/gfx8_sdst_4.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_sdst256_0: +.. _amdgpu_synid_gfx8_sdst_4: sdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx8_sdst_5.rst b/llvm/docs/AMDGPU/gfx8_sdst_5.rst new file mode 100644 index 000000000000..afed75ef9ed9 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_sdst_5.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_sdst_5: + +sdst +==== + +Instruction output. + +*Size:* 1 dword. + +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec` diff --git a/llvm/docs/AMDGPU/gfx8_sdst64_1.rst b/llvm/docs/AMDGPU/gfx8_sdst_6.rst similarity index 65% rename from llvm/docs/AMDGPU/gfx8_sdst64_1.rst rename to llvm/docs/AMDGPU/gfx8_sdst_6.rst index 165e0c0175f9..a9649d857264 100644 --- a/llvm/docs/AMDGPU/gfx8_sdst64_1.rst +++ b/llvm/docs/AMDGPU/gfx8_sdst_6.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid8_sdst64_1: +.. _amdgpu_synid_gfx8_sdst_6: sdst -=========================== +==== Instruction output. *Size:* 2 dwords. -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`exec` +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`exec` diff --git a/llvm/docs/AMDGPU/gfx8_sdst32_2.rst b/llvm/docs/AMDGPU/gfx8_sdst_7.rst similarity index 73% rename from llvm/docs/AMDGPU/gfx8_sdst32_2.rst rename to llvm/docs/AMDGPU/gfx8_sdst_7.rst index af446d3e54ce..dc58839db90c 100644 --- a/llvm/docs/AMDGPU/gfx8_sdst32_2.rst +++ b/llvm/docs/AMDGPU/gfx8_sdst_7.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid8_sdst32_2: +.. _amdgpu_synid_gfx8_sdst_7: sdst -=========================== +==== Instruction output. *Size:* 1 dword. -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`trap` +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`trap` diff --git a/llvm/docs/AMDGPU/gfx10_bimm32.rst b/llvm/docs/AMDGPU/gfx8_simm32.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx10_bimm32.rst rename to llvm/docs/AMDGPU/gfx8_simm32.rst index ebcc691ee258..e748b0d7d100 100644 --- a/llvm/docs/AMDGPU/gfx10_bimm32.rst +++ b/llvm/docs/AMDGPU/gfx8_simm32.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid10_bimm32: +.. _amdgpu_synid_gfx8_simm32: -imm32 -=========================== +simm32 +====== An :ref:`integer_number` or an :ref:`absolute_expression`. The value is truncated to 32 bits. diff --git a/llvm/docs/AMDGPU/gfx10_fimm16.rst b/llvm/docs/AMDGPU/gfx8_simm32_1.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_fimm16.rst rename to llvm/docs/AMDGPU/gfx8_simm32_1.rst index 9ac39c617908..4114ba283fcc 100644 --- a/llvm/docs/AMDGPU/gfx10_fimm16.rst +++ b/llvm/docs/AMDGPU/gfx8_simm32_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_fimm16: +.. _amdgpu_synid_gfx8_simm32_1: -imm32 -=========================== +simm32 +====== A :ref:`floating-point_number`, an :ref:`integer_number`, or an :ref:`absolute_expression`. The value is converted to *f16* as described :ref:`here`. diff --git a/llvm/docs/AMDGPU/gfx10_fimm32.rst b/llvm/docs/AMDGPU/gfx8_simm32_2.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_fimm32.rst rename to llvm/docs/AMDGPU/gfx8_simm32_2.rst index 7b181912e38f..5b88c7ee4a73 100644 --- a/llvm/docs/AMDGPU/gfx10_fimm32.rst +++ b/llvm/docs/AMDGPU/gfx8_simm32_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_fimm32: +.. _amdgpu_synid_gfx8_simm32_2: -imm32 -=========================== +simm32 +====== A :ref:`floating-point_number`, an :ref:`integer_number`, or an :ref:`absolute_expression`. The value is converted to *f32* as described :ref:`here`. diff --git a/llvm/docs/AMDGPU/gfx8_offset_buf.rst b/llvm/docs/AMDGPU/gfx8_soffset.rst similarity index 51% rename from llvm/docs/AMDGPU/gfx8_offset_buf.rst rename to llvm/docs/AMDGPU/gfx8_soffset.rst index 7b72bb64a3e9..6a75e3427d03 100644 --- a/llvm/docs/AMDGPU/gfx8_offset_buf.rst +++ b/llvm/docs/AMDGPU/gfx8_soffset.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid8_offset_buf: +.. _amdgpu_synid_gfx8_soffset: soffset -=========================== +======= An unsigned byte offset. *Size:* 1 dword. -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx8_offset_smem_load.rst b/llvm/docs/AMDGPU/gfx8_soffset_1.rst similarity index 64% rename from llvm/docs/AMDGPU/gfx8_offset_smem_load.rst rename to llvm/docs/AMDGPU/gfx8_soffset_1.rst index 5c30a87f569c..2b470445a28f 100644 --- a/llvm/docs/AMDGPU/gfx8_offset_smem_load.rst +++ b/llvm/docs/AMDGPU/gfx8_soffset_1.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid8_offset_smem_load: +.. _amdgpu_synid_gfx8_soffset_1: soffset -=========================== +======= An unsigned byte offset added to the base address to get memory address. *Size:* 1 dword. -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`uimm20` +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`uimm20` diff --git a/llvm/docs/AMDGPU/gfx8_offset_smem_store.rst b/llvm/docs/AMDGPU/gfx8_soffset_2.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx8_offset_smem_store.rst rename to llvm/docs/AMDGPU/gfx8_soffset_2.rst index 9ff90f98b354..e9d6c654b82d 100644 --- a/llvm/docs/AMDGPU/gfx8_offset_smem_store.rst +++ b/llvm/docs/AMDGPU/gfx8_soffset_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_offset_smem_store: +.. _amdgpu_synid_gfx8_soffset_2: soffset -=========================== +======= An unsigned byte offset added to the base address to get memory address. diff --git a/llvm/docs/AMDGPU/gfx8_src.rst b/llvm/docs/AMDGPU/gfx8_src.rst new file mode 100644 index 000000000000..15439b6dce53 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_src.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_src: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx8_src32_0.rst b/llvm/docs/AMDGPU/gfx8_src32_0.rst deleted file mode 100644 index 2e4d42b35f29..000000000000 --- a/llvm/docs/AMDGPU/gfx8_src32_0.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_src32_0: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx8_src32_1.rst b/llvm/docs/AMDGPU/gfx8_src32_1.rst deleted file mode 100644 index bd06181f7d3e..000000000000 --- a/llvm/docs/AMDGPU/gfx8_src32_1.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_src32_1: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`iconst`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx8_src32_2.rst b/llvm/docs/AMDGPU/gfx8_src32_2.rst deleted file mode 100644 index 3d8c63b19e3a..000000000000 --- a/llvm/docs/AMDGPU/gfx8_src32_2.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_src32_2: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx8_src32_3.rst b/llvm/docs/AMDGPU/gfx8_src32_3.rst deleted file mode 100644 index 19071fa8fde2..000000000000 --- a/llvm/docs/AMDGPU/gfx8_src32_3.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_src32_3: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx8_src32_4.rst b/llvm/docs/AMDGPU/gfx8_src32_4.rst deleted file mode 100644 index 0b71eec0f2c3..000000000000 --- a/llvm/docs/AMDGPU/gfx8_src32_4.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_src32_4: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx8_src32_5.rst b/llvm/docs/AMDGPU/gfx8_src32_5.rst deleted file mode 100644 index f37bd89321da..000000000000 --- a/llvm/docs/AMDGPU/gfx8_src32_5.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_src32_5: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx8_src32_6.rst b/llvm/docs/AMDGPU/gfx8_src32_6.rst deleted file mode 100644 index 2fe88a33a463..000000000000 --- a/llvm/docs/AMDGPU/gfx8_src32_6.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_src32_6: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`iconst` diff --git a/llvm/docs/AMDGPU/gfx8_src32_7.rst b/llvm/docs/AMDGPU/gfx8_src32_7.rst deleted file mode 100644 index c6b2cacd0b26..000000000000 --- a/llvm/docs/AMDGPU/gfx8_src32_7.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_src32_7: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst` diff --git a/llvm/docs/AMDGPU/gfx8_src64_0.rst b/llvm/docs/AMDGPU/gfx8_src64_0.rst deleted file mode 100644 index d62c37e3b60a..000000000000 --- a/llvm/docs/AMDGPU/gfx8_src64_0.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_src64_0: - -src -=========================== - -Instruction input. - -*Size:* 2 dwords. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx8_src64_1.rst b/llvm/docs/AMDGPU/gfx8_src64_1.rst deleted file mode 100644 index cd5ab8b1b75d..000000000000 --- a/llvm/docs/AMDGPU/gfx8_src64_1.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_src64_1: - -src -=========================== - -Instruction input. - -*Size:* 2 dwords. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx8_src_1.rst b/llvm/docs/AMDGPU/gfx8_src_1.rst new file mode 100644 index 000000000000..275735c5439f --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_src_1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_src_1: + +src +=== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx8_src_10.rst b/llvm/docs/AMDGPU/gfx8_src_10.rst new file mode 100644 index 000000000000..5d8df883c9c6 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_src_10.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_src_10: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst` diff --git a/llvm/docs/AMDGPU/gfx8_src_2.rst b/llvm/docs/AMDGPU/gfx8_src_2.rst new file mode 100644 index 000000000000..128faaa3730a --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_src_2.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_src_2: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`iconst`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx10_vsrc32_1.rst b/llvm/docs/AMDGPU/gfx8_src_3.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx10_vsrc32_1.rst rename to llvm/docs/AMDGPU/gfx8_src_3.rst index fd8c6bd28bda..3b1f63b0314a 100644 --- a/llvm/docs/AMDGPU/gfx10_vsrc32_1.rst +++ b/llvm/docs/AMDGPU/gfx8_src_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_vsrc32_1: +.. _amdgpu_synid_gfx8_src_3: -vsrc -=========================== +src +=== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx8_src_4.rst b/llvm/docs/AMDGPU/gfx8_src_4.rst new file mode 100644 index 000000000000..be6235551256 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_src_4.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_src_4: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx8_ssrc64_0.rst b/llvm/docs/AMDGPU/gfx8_src_5.rst similarity index 61% rename from llvm/docs/AMDGPU/gfx8_ssrc64_0.rst rename to llvm/docs/AMDGPU/gfx8_src_5.rst index 6c7efe5d5308..ec7d46c14973 100644 --- a/llvm/docs/AMDGPU/gfx8_ssrc64_0.rst +++ b/llvm/docs/AMDGPU/gfx8_src_5.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid8_ssrc64_0: +.. _amdgpu_synid_gfx8_src_5: -ssrc -=========================== +src +=== Instruction input. -*Size:* 2 dwords. +*Size:* 1 dword. -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant`, :ref:`literal` +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx8_src_6.rst b/llvm/docs/AMDGPU/gfx8_src_6.rst new file mode 100644 index 000000000000..bd52d5ab8afb --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_src_6.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_src_6: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx8_ssrc64_2.rst b/llvm/docs/AMDGPU/gfx8_src_7.rst similarity index 59% rename from llvm/docs/AMDGPU/gfx8_ssrc64_2.rst rename to llvm/docs/AMDGPU/gfx8_src_7.rst index 3252202ce988..366eace4e101 100644 --- a/llvm/docs/AMDGPU/gfx8_ssrc64_2.rst +++ b/llvm/docs/AMDGPU/gfx8_src_7.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid8_ssrc64_2: +.. _amdgpu_synid_gfx8_src_7: -ssrc -=========================== +src +=== Instruction input. -*Size:* 2 dwords. +*Size:* 1 dword. -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx8_src_8.rst b/llvm/docs/AMDGPU/gfx8_src_8.rst new file mode 100644 index 000000000000..75f2dcec72cc --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_src_8.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_src_8: + +src +=== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx8_src_9.rst b/llvm/docs/AMDGPU/gfx8_src_9.rst new file mode 100644 index 000000000000..4b5b1eca3faa --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_src_9.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_src_9: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`iconst` diff --git a/llvm/docs/AMDGPU/gfx10_rsrc_mimg.rst b/llvm/docs/AMDGPU/gfx8_srsrc.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_rsrc_mimg.rst rename to llvm/docs/AMDGPU/gfx8_srsrc.rst index af830b0a2c8d..11ce8a4e3953 100644 --- a/llvm/docs/AMDGPU/gfx10_rsrc_mimg.rst +++ b/llvm/docs/AMDGPU/gfx8_srsrc.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_rsrc_mimg: +.. _amdgpu_synid_gfx8_srsrc: srsrc -=========================== +===== Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format. diff --git a/llvm/docs/AMDGPU/gfx10_rsrc_buf.rst b/llvm/docs/AMDGPU/gfx8_srsrc_1.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx10_rsrc_buf.rst rename to llvm/docs/AMDGPU/gfx8_srsrc_1.rst index a3f454b40191..0fdb39e58dcf 100644 --- a/llvm/docs/AMDGPU/gfx10_rsrc_buf.rst +++ b/llvm/docs/AMDGPU/gfx8_srsrc_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_rsrc_buf: +.. _amdgpu_synid_gfx8_srsrc_1: srsrc -=========================== +===== Buffer resource constant which defines the address and characteristics of the buffer in memory. diff --git a/llvm/docs/AMDGPU/gfx10_samp_mimg.rst b/llvm/docs/AMDGPU/gfx8_ssamp.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx10_samp_mimg.rst rename to llvm/docs/AMDGPU/gfx8_ssamp.rst index 5f2aed088f11..79489dcc2be9 100644 --- a/llvm/docs/AMDGPU/gfx10_samp_mimg.rst +++ b/llvm/docs/AMDGPU/gfx8_ssamp.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_samp_mimg: +.. _amdgpu_synid_gfx8_ssamp: ssamp -=========================== +===== Sampler constant used to specify filtering options applied to the image data after it is read. diff --git a/llvm/docs/AMDGPU/gfx8_ssrc.rst b/llvm/docs/AMDGPU/gfx8_ssrc.rst new file mode 100644 index 000000000000..9449afeed91f --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_ssrc.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_ssrc: + +ssrc +==== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx8_ssrc32_0.rst b/llvm/docs/AMDGPU/gfx8_ssrc32_0.rst deleted file mode 100644 index 1f7d9fbdb23e..000000000000 --- a/llvm/docs/AMDGPU/gfx8_ssrc32_0.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_ssrc32_0: - -ssrc -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx8_ssrc32_2.rst b/llvm/docs/AMDGPU/gfx8_ssrc32_2.rst deleted file mode 100644 index 9b893e962a0a..000000000000 --- a/llvm/docs/AMDGPU/gfx8_ssrc32_2.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_ssrc32_2: - -ssrc -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec` diff --git a/llvm/docs/AMDGPU/gfx8_ssrc32_3.rst b/llvm/docs/AMDGPU/gfx8_ssrc32_3.rst deleted file mode 100644 index 131765fee506..000000000000 --- a/llvm/docs/AMDGPU/gfx8_ssrc32_3.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_ssrc32_3: - -ssrc -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`iconst` diff --git a/llvm/docs/AMDGPU/gfx8_ssrc32_4.rst b/llvm/docs/AMDGPU/gfx8_ssrc32_4.rst deleted file mode 100644 index eb5e2247fe04..000000000000 --- a/llvm/docs/AMDGPU/gfx8_ssrc32_4.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_ssrc32_4: - -ssrc -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx8_ssrc64_3.rst b/llvm/docs/AMDGPU/gfx8_ssrc64_3.rst deleted file mode 100644 index 9ab5436572d1..000000000000 --- a/llvm/docs/AMDGPU/gfx8_ssrc64_3.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid8_ssrc64_3: - -ssrc -=========================== - -Instruction input. - -*Size:* 2 dwords. - -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap`, :ref:`exec` diff --git a/llvm/docs/AMDGPU/gfx8_ssrc_1.rst b/llvm/docs/AMDGPU/gfx8_ssrc_1.rst new file mode 100644 index 000000000000..266e963e7b9b --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_ssrc_1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_ssrc_1: + +ssrc +==== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx8_ssrc32_1.rst b/llvm/docs/AMDGPU/gfx8_ssrc_2.rst similarity index 69% rename from llvm/docs/AMDGPU/gfx8_ssrc32_1.rst rename to llvm/docs/AMDGPU/gfx8_ssrc_2.rst index 203d9c5397fc..38aca6f1860f 100644 --- a/llvm/docs/AMDGPU/gfx8_ssrc32_1.rst +++ b/llvm/docs/AMDGPU/gfx8_ssrc_2.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid8_ssrc32_1: +.. _amdgpu_synid_gfx8_ssrc_2: ssrc -=========================== +==== Instruction input. *Size:* 1 dword. -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap` +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap` diff --git a/llvm/docs/AMDGPU/gfx8_ssrc64_1.rst b/llvm/docs/AMDGPU/gfx8_ssrc_3.rst similarity index 69% rename from llvm/docs/AMDGPU/gfx8_ssrc64_1.rst rename to llvm/docs/AMDGPU/gfx8_ssrc_3.rst index c4fddf4ace2b..f4700b14da50 100644 --- a/llvm/docs/AMDGPU/gfx8_ssrc64_1.rst +++ b/llvm/docs/AMDGPU/gfx8_ssrc_3.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid8_ssrc64_1: +.. _amdgpu_synid_gfx8_ssrc_3: ssrc -=========================== +==== Instruction input. *Size:* 2 dwords. -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`trap` +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap` diff --git a/llvm/docs/AMDGPU/gfx8_ssrc_4.rst b/llvm/docs/AMDGPU/gfx8_ssrc_4.rst new file mode 100644 index 000000000000..2e771c2f161f --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_ssrc_4.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_ssrc_4: + +ssrc +==== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx8_ssrc_5.rst b/llvm/docs/AMDGPU/gfx8_ssrc_5.rst new file mode 100644 index 000000000000..859852d20f44 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_ssrc_5.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_ssrc_5: + +ssrc +==== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`exec` diff --git a/llvm/docs/AMDGPU/gfx8_ssrc_6.rst b/llvm/docs/AMDGPU/gfx8_ssrc_6.rst new file mode 100644 index 000000000000..1f6d5473b9de --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_ssrc_6.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_ssrc_6: + +ssrc +==== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec` diff --git a/llvm/docs/AMDGPU/gfx8_ssrc_7.rst b/llvm/docs/AMDGPU/gfx8_ssrc_7.rst new file mode 100644 index 000000000000..1f09600aaa07 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_ssrc_7.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_ssrc_7: + +ssrc +==== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`iconst` diff --git a/llvm/docs/AMDGPU/gfx8_ssrc_8.rst b/llvm/docs/AMDGPU/gfx8_ssrc_8.rst new file mode 100644 index 000000000000..e6f8500c1d18 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_ssrc_8.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_ssrc_8: + +ssrc +==== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`trap`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx8_tgt.rst b/llvm/docs/AMDGPU/gfx8_tgt.rst index 3949028470ac..431d4fa6dc45 100644 --- a/llvm/docs/AMDGPU/gfx8_tgt.rst +++ b/llvm/docs/AMDGPU/gfx8_tgt.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_tgt: +.. _amdgpu_synid_gfx8_tgt: tgt -=========================== +=== An export target: diff --git a/llvm/docs/AMDGPU/gfx906_type_dev.rst b/llvm/docs/AMDGPU/gfx8_type_deviation.rst similarity index 69% rename from llvm/docs/AMDGPU/gfx906_type_dev.rst rename to llvm/docs/AMDGPU/gfx8_type_deviation.rst index 624d96c8beef..c9de90bbe9d3 100644 --- a/llvm/docs/AMDGPU/gfx906_type_dev.rst +++ b/llvm/docs/AMDGPU/gfx8_type_deviation.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid906_type_dev: +.. _amdgpu_synid_gfx8_type_deviation: -Type deviation -=========================== +Type Deviation +============== -*Type* of this operand differs from *type* :ref:`implied by the opcode`. This tag specifies actual operand *type*. +*Type* of this operand differs from *type* :ref:`implied by the opcode`. This tag specifies actual operand *type*. diff --git a/llvm/docs/AMDGPU/gfx10_addr_ds.rst b/llvm/docs/AMDGPU/gfx8_vaddr.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx10_addr_ds.rst rename to llvm/docs/AMDGPU/gfx8_vaddr.rst index b31862f2ec75..4df48f46351a 100644 --- a/llvm/docs/AMDGPU/gfx10_addr_ds.rst +++ b/llvm/docs/AMDGPU/gfx8_vaddr.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_addr_ds: +.. _amdgpu_synid_gfx8_vaddr: vaddr -=========================== +===== An offset from the start of GDS/LDS memory. diff --git a/llvm/docs/AMDGPU/gfx10_addr_flat.rst b/llvm/docs/AMDGPU/gfx8_vaddr_1.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx10_addr_flat.rst rename to llvm/docs/AMDGPU/gfx8_vaddr_1.rst index cd780ca0cbe1..279fe729473e 100644 --- a/llvm/docs/AMDGPU/gfx10_addr_flat.rst +++ b/llvm/docs/AMDGPU/gfx8_vaddr_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_addr_flat: +.. _amdgpu_synid_gfx8_vaddr_1: vaddr -=========================== +===== A 64-bit flat address. diff --git a/llvm/docs/AMDGPU/gfx8_addr_mimg.rst b/llvm/docs/AMDGPU/gfx8_vaddr_2.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx8_addr_mimg.rst rename to llvm/docs/AMDGPU/gfx8_vaddr_2.rst index f1052badacda..5bcd1b04ad59 100644 --- a/llvm/docs/AMDGPU/gfx8_addr_mimg.rst +++ b/llvm/docs/AMDGPU/gfx8_vaddr_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_addr_mimg: +.. _amdgpu_synid_gfx8_vaddr_2: vaddr -=========================== +===== Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image. diff --git a/llvm/docs/AMDGPU/gfx10_addr_buf.rst b/llvm/docs/AMDGPU/gfx8_vaddr_3.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx10_addr_buf.rst rename to llvm/docs/AMDGPU/gfx8_vaddr_3.rst index bd57e9e2fcdb..b40dac12c8c9 100644 --- a/llvm/docs/AMDGPU/gfx10_addr_buf.rst +++ b/llvm/docs/AMDGPU/gfx8_vaddr_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_addr_buf: +.. _amdgpu_synid_gfx8_vaddr_3: vaddr -=========================== +===== This is an optional operand which may specify offset and/or index. diff --git a/llvm/docs/AMDGPU/gfx8_vcc_64.rst b/llvm/docs/AMDGPU/gfx8_vcc.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx8_vcc_64.rst rename to llvm/docs/AMDGPU/gfx8_vcc.rst index e31df0e51c2e..14711dd23490 100644 --- a/llvm/docs/AMDGPU/gfx8_vcc_64.rst +++ b/llvm/docs/AMDGPU/gfx8_vcc.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_vcc_64: +.. _amdgpu_synid_gfx8_vcc: vcc -=========================== +=== Vector condition code. diff --git a/llvm/docs/AMDGPU/gfx10_vdata32_0.rst b/llvm/docs/AMDGPU/gfx8_vdata.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx10_vdata32_0.rst rename to llvm/docs/AMDGPU/gfx8_vdata.rst index e2ddcee736b7..713dc8670c12 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata32_0.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_vdata32_0: +.. _amdgpu_synid_gfx8_vdata: vdata -=========================== +===== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx8_vdata0.rst b/llvm/docs/AMDGPU/gfx8_vdata0.rst new file mode 100644 index 000000000000..2bf2274ac031 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_vdata0.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_vdata0: + +vdata0 +====== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdata0_1.rst b/llvm/docs/AMDGPU/gfx8_vdata0_1.rst new file mode 100644 index 000000000000..d0a04f22f5ec --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_vdata0_1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_vdata0_1: + +vdata0 +====== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdata1.rst b/llvm/docs/AMDGPU/gfx8_vdata1.rst new file mode 100644 index 000000000000..6009018b72af --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_vdata1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_vdata1: + +vdata1 +====== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdata1_1.rst b/llvm/docs/AMDGPU/gfx8_vdata1_1.rst new file mode 100644 index 000000000000..5b5ce86ff2aa --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_vdata1_1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_vdata1_1: + +vdata1 +====== + +Instruction input. + +*Size:* 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx10_vdata64_0.rst b/llvm/docs/AMDGPU/gfx8_vdata_1.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx10_vdata64_0.rst rename to llvm/docs/AMDGPU/gfx8_vdata_1.rst index 4552a3998fe9..d89b1f7fd174 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata64_0.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_vdata64_0: +.. _amdgpu_synid_gfx8_vdata_1: vdata -=========================== +===== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx8_data_buf_d16_96.rst b/llvm/docs/AMDGPU/gfx8_vdata_10.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx8_data_buf_d16_96.rst rename to llvm/docs/AMDGPU/gfx8_vdata_10.rst index b9e6915229fd..1c3a8728c943 100644 --- a/llvm/docs/AMDGPU/gfx8_data_buf_d16_96.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_10.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_data_buf_d16_96: +.. _amdgpu_synid_gfx8_vdata_10: vdata -=========================== +===== 16-bit data to store by a buffer instruction. diff --git a/llvm/docs/AMDGPU/gfx8_data_buf_d16_128.rst b/llvm/docs/AMDGPU/gfx8_vdata_11.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx8_data_buf_d16_128.rst rename to llvm/docs/AMDGPU/gfx8_vdata_11.rst index 3c98a360252e..4c79ea31e6d7 100644 --- a/llvm/docs/AMDGPU/gfx8_data_buf_d16_128.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_11.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_data_buf_d16_128: +.. _amdgpu_synid_gfx8_vdata_11: vdata -=========================== +===== 16-bit data to store by a buffer instruction. diff --git a/llvm/docs/AMDGPU/gfx10_data_buf_atomic32.rst b/llvm/docs/AMDGPU/gfx8_vdata_12.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx10_data_buf_atomic32.rst rename to llvm/docs/AMDGPU/gfx8_vdata_12.rst index a8e6d9fd61d8..d25ce77f0627 100644 --- a/llvm/docs/AMDGPU/gfx10_data_buf_atomic32.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_12.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_data_buf_atomic32: +.. _amdgpu_synid_gfx8_vdata_12: vdata -=========================== +===== Input data for an atomic instruction. diff --git a/llvm/docs/AMDGPU/gfx10_data_buf_atomic64.rst b/llvm/docs/AMDGPU/gfx8_vdata_13.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx10_data_buf_atomic64.rst rename to llvm/docs/AMDGPU/gfx8_vdata_13.rst index 3840cd5d92e9..6e439c1710a0 100644 --- a/llvm/docs/AMDGPU/gfx10_data_buf_atomic64.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_13.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_data_buf_atomic64: +.. _amdgpu_synid_gfx8_vdata_13: vdata -=========================== +===== Input data for an atomic instruction. diff --git a/llvm/docs/AMDGPU/gfx10_data_buf_atomic128.rst b/llvm/docs/AMDGPU/gfx8_vdata_14.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx10_data_buf_atomic128.rst rename to llvm/docs/AMDGPU/gfx8_vdata_14.rst index 3ca9fb9c3eaf..3fe0069e6da0 100644 --- a/llvm/docs/AMDGPU/gfx10_data_buf_atomic128.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_14.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_data_buf_atomic128: +.. _amdgpu_synid_gfx8_vdata_14: vdata -=========================== +===== Input data for an atomic instruction. diff --git a/llvm/docs/AMDGPU/gfx10_vdata128_0.rst b/llvm/docs/AMDGPU/gfx8_vdata_2.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx10_vdata128_0.rst rename to llvm/docs/AMDGPU/gfx8_vdata_2.rst index 0e25049065ee..5283001e7945 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata128_0.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_vdata128_0: +.. _amdgpu_synid_gfx8_vdata_2: vdata -=========================== +===== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_vdata96_0.rst b/llvm/docs/AMDGPU/gfx8_vdata_3.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx10_vdata96_0.rst rename to llvm/docs/AMDGPU/gfx8_vdata_3.rst index 084825a6331b..f7bc70fd1c97 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata96_0.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_vdata96_0: +.. _amdgpu_synid_gfx8_vdata_3: vdata -=========================== +===== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst b/llvm/docs/AMDGPU/gfx8_vdata_4.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst rename to llvm/docs/AMDGPU/gfx8_vdata_4.rst index 7b74290a5652..6feb94be08ce 100644 --- a/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_4.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_data_mimg_atomic_reg: +.. _amdgpu_synid_gfx8_vdata_4: vdata -=========================== +===== Input data for an atomic instruction. diff --git a/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst b/llvm/docs/AMDGPU/gfx8_vdata_5.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst rename to llvm/docs/AMDGPU/gfx8_vdata_5.rst index 6b5cd6814350..33ca105c3a62 100644 --- a/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_5.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_data_mimg_atomic_cmp: +.. _amdgpu_synid_gfx8_vdata_5: vdata -=========================== +===== Input data for an atomic instruction. @@ -23,5 +23,4 @@ Optionally may serve as an output data: Note: the surface data format is indicated in the image resource constant but not in the instruction. - *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_data_mimg_store_d16.rst b/llvm/docs/AMDGPU/gfx8_vdata_6.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx8_data_mimg_store_d16.rst rename to llvm/docs/AMDGPU/gfx8_vdata_6.rst index 7524c884e765..a6c7f230201e 100644 --- a/llvm/docs/AMDGPU/gfx8_data_mimg_store_d16.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_6.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_data_mimg_store_d16: +.. _amdgpu_synid_gfx8_vdata_6: vdata -=========================== +===== Image data to store by an *image_store* instruction. @@ -20,5 +20,4 @@ Image data to store by an *image_store* instruction. * For GFX8.0 this modifier does not affect size of data elements in registers. Data in registers are stored in low 16 bits, high 16 bits are unused. There is no packing. * Starting from GFX8.1 this modifier specifies that data elements in registers are packed; each value occupies 16 bits. - *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx10_data_mimg_store.rst b/llvm/docs/AMDGPU/gfx8_vdata_7.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_data_mimg_store.rst rename to llvm/docs/AMDGPU/gfx8_vdata_7.rst index 156c1b0180e5..be7ea7009643 100644 --- a/llvm/docs/AMDGPU/gfx10_data_mimg_store.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_7.rst @@ -5,14 +5,13 @@ * * ************************************************** -.. _amdgpu_synid10_data_mimg_store: +.. _amdgpu_synid_gfx8_vdata_7: vdata -=========================== +===== Image data to store by an *image_store* instruction. *Size:* depends on :ref:`dmask` which may specify from 1 to 4 data elements. Each data element occupies 1 dword. - *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_data_buf_d16_32.rst b/llvm/docs/AMDGPU/gfx8_vdata_8.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx8_data_buf_d16_32.rst rename to llvm/docs/AMDGPU/gfx8_vdata_8.rst index 64328756f84c..a52ff705977a 100644 --- a/llvm/docs/AMDGPU/gfx8_data_buf_d16_32.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_8.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_data_buf_d16_32: +.. _amdgpu_synid_gfx8_vdata_8: vdata -=========================== +===== 16-bit data to store by a buffer instruction. diff --git a/llvm/docs/AMDGPU/gfx8_data_buf_d16_64.rst b/llvm/docs/AMDGPU/gfx8_vdata_9.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx8_data_buf_d16_64.rst rename to llvm/docs/AMDGPU/gfx8_vdata_9.rst index 932ce6920fca..d00f40291b04 100644 --- a/llvm/docs/AMDGPU/gfx8_data_buf_d16_64.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_9.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_data_buf_d16_64: +.. _amdgpu_synid_gfx8_vdata_9: vdata -=========================== +===== 16-bit data to store by a buffer instruction. diff --git a/llvm/docs/AMDGPU/gfx900_vdst32_0.rst b/llvm/docs/AMDGPU/gfx8_vdst.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx900_vdst32_0.rst rename to llvm/docs/AMDGPU/gfx8_vdst.rst index 0ae76da5315f..227ee5376914 100644 --- a/llvm/docs/AMDGPU/gfx900_vdst32_0.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid900_vdst32_0: +.. _amdgpu_synid_gfx8_vdst: vdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx10_vdst64_0.rst b/llvm/docs/AMDGPU/gfx8_vdst_1.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx10_vdst64_0.rst rename to llvm/docs/AMDGPU/gfx8_vdst_1.rst index 6e44c28a07b3..566cb1d13b08 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst64_0.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_vdst64_0: +.. _amdgpu_synid_gfx8_vdst_1: vdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx8_dst_buf_d16_64.rst b/llvm/docs/AMDGPU/gfx8_vdst_10.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx8_dst_buf_d16_64.rst rename to llvm/docs/AMDGPU/gfx8_vdst_10.rst index b46310fd5241..eed24091f51d 100644 --- a/llvm/docs/AMDGPU/gfx8_dst_buf_d16_64.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_10.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_dst_buf_d16_64: +.. _amdgpu_synid_gfx8_vdst_10: vdst -=========================== +==== Instruction output: data read from a memory buffer and converted to a 16-bit format. diff --git a/llvm/docs/AMDGPU/gfx8_dst_buf_d16_96.rst b/llvm/docs/AMDGPU/gfx8_vdst_11.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx8_dst_buf_d16_96.rst rename to llvm/docs/AMDGPU/gfx8_vdst_11.rst index 15e7e8901970..37d160bbeb12 100644 --- a/llvm/docs/AMDGPU/gfx8_dst_buf_d16_96.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_11.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_dst_buf_d16_96: +.. _amdgpu_synid_gfx8_vdst_11: vdst -=========================== +==== Instruction output: data read from a memory buffer and converted to a 16-bit format. diff --git a/llvm/docs/AMDGPU/gfx8_dst_buf_d16_128.rst b/llvm/docs/AMDGPU/gfx8_vdst_12.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx8_dst_buf_d16_128.rst rename to llvm/docs/AMDGPU/gfx8_vdst_12.rst index 0f5318d8d8ce..a79d7924233a 100644 --- a/llvm/docs/AMDGPU/gfx8_dst_buf_d16_128.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_12.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_dst_buf_d16_128: +.. _amdgpu_synid_gfx8_vdst_12: vdst -=========================== +==== Instruction output: data read from a memory buffer and converted to a 16-bit format. diff --git a/llvm/docs/AMDGPU/gfx10_dst_buf_32.rst b/llvm/docs/AMDGPU/gfx8_vdst_13.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_dst_buf_32.rst rename to llvm/docs/AMDGPU/gfx8_vdst_13.rst index a1f1dc99ffb8..3af0bcb22c10 100644 --- a/llvm/docs/AMDGPU/gfx10_dst_buf_32.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_13.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_dst_buf_32: +.. _amdgpu_synid_gfx8_vdst_13: vdst -=========================== +==== Instruction output: data read from a memory buffer. diff --git a/llvm/docs/AMDGPU/gfx10_dst_buf_64.rst b/llvm/docs/AMDGPU/gfx8_vdst_14.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_dst_buf_64.rst rename to llvm/docs/AMDGPU/gfx8_vdst_14.rst index ebd3c7e3f173..5de619e78233 100644 --- a/llvm/docs/AMDGPU/gfx10_dst_buf_64.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_14.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_dst_buf_64: +.. _amdgpu_synid_gfx8_vdst_14: vdst -=========================== +==== Instruction output: data read from a memory buffer. diff --git a/llvm/docs/AMDGPU/gfx10_dst_buf_96.rst b/llvm/docs/AMDGPU/gfx8_vdst_15.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_dst_buf_96.rst rename to llvm/docs/AMDGPU/gfx8_vdst_15.rst index 13a7e2bfc966..20135ddefec9 100644 --- a/llvm/docs/AMDGPU/gfx10_dst_buf_96.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_15.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_dst_buf_96: +.. _amdgpu_synid_gfx8_vdst_15: vdst -=========================== +==== Instruction output: data read from a memory buffer. diff --git a/llvm/docs/AMDGPU/gfx10_dst_buf_128.rst b/llvm/docs/AMDGPU/gfx8_vdst_16.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_dst_buf_128.rst rename to llvm/docs/AMDGPU/gfx8_vdst_16.rst index 56cfc2f10180..d2410a72c6b6 100644 --- a/llvm/docs/AMDGPU/gfx10_dst_buf_128.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_16.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_dst_buf_128: +.. _amdgpu_synid_gfx8_vdst_16: vdst -=========================== +==== Instruction output: data read from a memory buffer. diff --git a/llvm/docs/AMDGPU/gfx10_dst_buf_lds.rst b/llvm/docs/AMDGPU/gfx8_vdst_17.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_dst_buf_lds.rst rename to llvm/docs/AMDGPU/gfx8_vdst_17.rst index ec83bf56931e..7d9929abcf53 100644 --- a/llvm/docs/AMDGPU/gfx10_dst_buf_lds.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_17.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_dst_buf_lds: +.. _amdgpu_synid_gfx8_vdst_17: vdst -=========================== +==== Instruction output: data read from a memory buffer. diff --git a/llvm/docs/AMDGPU/gfx10_vdst128_0.rst b/llvm/docs/AMDGPU/gfx8_vdst_2.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx10_vdst128_0.rst rename to llvm/docs/AMDGPU/gfx8_vdst_2.rst index a0a786c3b693..26daa85eb9b0 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst128_0.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_vdst128_0: +.. _amdgpu_synid_gfx8_vdst_2: vdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx10_vdst96_0.rst b/llvm/docs/AMDGPU/gfx8_vdst_3.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx10_vdst96_0.rst rename to llvm/docs/AMDGPU/gfx8_vdst_3.rst index a30e2ee8ae77..897d78ccf6f5 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst96_0.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_vdst96_0: +.. _amdgpu_synid_gfx8_vdst_3: vdst -=========================== +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx10_dst_flat_atomic32.rst b/llvm/docs/AMDGPU/gfx8_vdst_4.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_dst_flat_atomic32.rst rename to llvm/docs/AMDGPU/gfx8_vdst_4.rst index e8d94b855953..928ebda2de7f 100644 --- a/llvm/docs/AMDGPU/gfx10_dst_flat_atomic32.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_4.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_dst_flat_atomic32: +.. _amdgpu_synid_gfx8_vdst_4: vdst -=========================== +==== Data returned by a 32-bit atomic flat instruction. diff --git a/llvm/docs/AMDGPU/gfx10_dst_flat_atomic64.rst b/llvm/docs/AMDGPU/gfx8_vdst_5.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx10_dst_flat_atomic64.rst rename to llvm/docs/AMDGPU/gfx8_vdst_5.rst index 19d9b11ba8c9..be066c7e0c8e 100644 --- a/llvm/docs/AMDGPU/gfx10_dst_flat_atomic64.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_5.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_dst_flat_atomic64: +.. _amdgpu_synid_gfx8_vdst_5: vdst -=========================== +==== Data returned by a 64-bit atomic flat instruction. diff --git a/llvm/docs/AMDGPU/gfx8_dst_mimg_gather4.rst b/llvm/docs/AMDGPU/gfx8_vdst_6.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx8_dst_mimg_gather4.rst rename to llvm/docs/AMDGPU/gfx8_vdst_6.rst index 6fc01926ed17..1f38906417cf 100644 --- a/llvm/docs/AMDGPU/gfx8_dst_mimg_gather4.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_6.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_dst_mimg_gather4: +.. _amdgpu_synid_gfx8_vdst_6: vdst -=========================== +==== Image data to load by an *image_gather4* instruction. diff --git a/llvm/docs/AMDGPU/gfx10_dst_mimg_regular.rst b/llvm/docs/AMDGPU/gfx8_vdst_7.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_dst_mimg_regular.rst rename to llvm/docs/AMDGPU/gfx8_vdst_7.rst index d3379356ee72..f47e838e6a25 100644 --- a/llvm/docs/AMDGPU/gfx10_dst_mimg_regular.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_7.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_dst_mimg_regular: +.. _amdgpu_synid_gfx8_vdst_7: vdst -=========================== +==== Image data to load by an image instruction. diff --git a/llvm/docs/AMDGPU/gfx8_dst_mimg_regular_d16.rst b/llvm/docs/AMDGPU/gfx8_vdst_8.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx8_dst_mimg_regular_d16.rst rename to llvm/docs/AMDGPU/gfx8_vdst_8.rst index 4eb7037386f1..2288dd83a1fa 100644 --- a/llvm/docs/AMDGPU/gfx8_dst_mimg_regular_d16.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_8.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_dst_mimg_regular_d16: +.. _amdgpu_synid_gfx8_vdst_8: vdst -=========================== +==== Image data to load by an image instruction. @@ -22,5 +22,4 @@ Image data to load by an image instruction. * :ref:`tfe` adds 1 dword if specified. - *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_dst_buf_d16_32.rst b/llvm/docs/AMDGPU/gfx8_vdst_9.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx8_dst_buf_d16_32.rst rename to llvm/docs/AMDGPU/gfx8_vdst_9.rst index 6288c2def70a..2aefb8af3f13 100644 --- a/llvm/docs/AMDGPU/gfx8_dst_buf_d16_32.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_9.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_dst_buf_d16_32: +.. _amdgpu_synid_gfx8_vdst_9: vdst -=========================== +==== Instruction output: data read from a memory buffer and converted to a 16-bit format. diff --git a/llvm/docs/AMDGPU/gfx10_src_exp.rst b/llvm/docs/AMDGPU/gfx8_vsrc.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx10_src_exp.rst rename to llvm/docs/AMDGPU/gfx8_vsrc.rst index 4dd387a3aed4..ae1ccfbb2960 100644 --- a/llvm/docs/AMDGPU/gfx10_src_exp.rst +++ b/llvm/docs/AMDGPU/gfx8_vsrc.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_src_exp: +.. _amdgpu_synid_gfx8_vsrc: vsrc -=========================== +==== Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off` if not used. diff --git a/llvm/docs/AMDGPU/gfx906_vsrc32_0.rst b/llvm/docs/AMDGPU/gfx8_vsrc_1.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx906_vsrc32_0.rst rename to llvm/docs/AMDGPU/gfx8_vsrc_1.rst index ed350d997eb7..1f256412604d 100644 --- a/llvm/docs/AMDGPU/gfx906_vsrc32_0.rst +++ b/llvm/docs/AMDGPU/gfx8_vsrc_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid906_vsrc32_0: +.. _amdgpu_synid_gfx8_vsrc_1: vsrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_vsrc128_0.rst b/llvm/docs/AMDGPU/gfx8_vsrc_2.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx10_vsrc128_0.rst rename to llvm/docs/AMDGPU/gfx8_vsrc_2.rst index 1808061d5107..48ba2fdb4b7d 100644 --- a/llvm/docs/AMDGPU/gfx10_vsrc128_0.rst +++ b/llvm/docs/AMDGPU/gfx8_vsrc_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_vsrc128_0: +.. _amdgpu_synid_gfx8_vsrc_2: vsrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx10_vsrc64_0.rst b/llvm/docs/AMDGPU/gfx8_vsrc_3.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx10_vsrc64_0.rst rename to llvm/docs/AMDGPU/gfx8_vsrc_3.rst index 56c8fff09eb5..0e0d13007629 100644 --- a/llvm/docs/AMDGPU/gfx10_vsrc64_0.rst +++ b/llvm/docs/AMDGPU/gfx8_vsrc_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid10_vsrc64_0: +.. _amdgpu_synid_gfx8_vsrc_3: vsrc -=========================== +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx8_waitcnt.rst b/llvm/docs/AMDGPU/gfx8_waitcnt.rst index 70c49d4c5280..63dd2570bbf8 100644 --- a/llvm/docs/AMDGPU/gfx8_waitcnt.rst +++ b/llvm/docs/AMDGPU/gfx8_waitcnt.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid8_waitcnt: +.. _amdgpu_synid_gfx8_waitcnt: waitcnt -=========================== +======= Counts of outstanding instructions to wait for. diff --git a/llvm/docs/AMDGPU/gfx900_mad_type_dev.rst b/llvm/docs/AMDGPU/gfx900_fx_operand.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx900_mad_type_dev.rst rename to llvm/docs/AMDGPU/gfx900_fx_operand.rst index 45f5dab2159c..2901f9e055ca 100644 --- a/llvm/docs/AMDGPU/gfx900_mad_type_dev.rst +++ b/llvm/docs/AMDGPU/gfx900_fx_operand.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid900_mad_type_dev: +.. _amdgpu_synid_gfx900_fx_operand: -fx -=========================== +FX Operand +========== This is an *f32* or *f16* operand depending on instruction modifiers: diff --git a/llvm/docs/AMDGPU/gfx900_mod_vop3_abs_neg.rst b/llvm/docs/AMDGPU/gfx900_m.rst similarity index 86% rename from llvm/docs/AMDGPU/gfx900_mod_vop3_abs_neg.rst rename to llvm/docs/AMDGPU/gfx900_m.rst index b5ccdfbd8a63..dcbf9b27d968 100644 --- a/llvm/docs/AMDGPU/gfx900_mod_vop3_abs_neg.rst +++ b/llvm/docs/AMDGPU/gfx900_m.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid900_mod_vop3_abs_neg: +.. _amdgpu_synid_gfx900_m: m -=========================== += This operand may be used with floating point operand modifiers :ref:`abs` and :ref:`neg`. diff --git a/llvm/docs/AMDGPU/gfx900_src.rst b/llvm/docs/AMDGPU/gfx900_src.rst new file mode 100644 index 000000000000..a7fa0e43b4dc --- /dev/null +++ b/llvm/docs/AMDGPU/gfx900_src.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx900_src: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx900_src32_0.rst b/llvm/docs/AMDGPU/gfx900_src32_0.rst deleted file mode 100644 index 9d7c573e78eb..000000000000 --- a/llvm/docs/AMDGPU/gfx900_src32_0.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid900_src32_0: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx900_src32_1.rst b/llvm/docs/AMDGPU/gfx900_src32_1.rst deleted file mode 100644 index a5c23c635c4b..000000000000 --- a/llvm/docs/AMDGPU/gfx900_src32_1.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid900_src32_1: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx900_src_1.rst b/llvm/docs/AMDGPU/gfx900_src_1.rst new file mode 100644 index 000000000000..7bfe01628d76 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx900_src_1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx900_src_1: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx900_vdst.rst b/llvm/docs/AMDGPU/gfx900_vdst.rst new file mode 100644 index 000000000000..920090c4277a --- /dev/null +++ b/llvm/docs/AMDGPU/gfx900_vdst.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx900_vdst: + +vdst +==== + +Instruction output. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx904_mad_type_dev.rst b/llvm/docs/AMDGPU/gfx904_fx_operand.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx904_mad_type_dev.rst rename to llvm/docs/AMDGPU/gfx904_fx_operand.rst index 13cd62a29470..74a857824cd5 100644 --- a/llvm/docs/AMDGPU/gfx904_mad_type_dev.rst +++ b/llvm/docs/AMDGPU/gfx904_fx_operand.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid904_mad_type_dev: +.. _amdgpu_synid_gfx904_fx_operand: -fx -=========================== +FX Operand +========== This is an *f32* or *f16* operand depending on instruction modifiers: diff --git a/llvm/docs/AMDGPU/gfx904_m.rst b/llvm/docs/AMDGPU/gfx904_m.rst new file mode 100644 index 000000000000..feb0b47f8926 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx904_m.rst @@ -0,0 +1,13 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx904_m: + +m += + +This operand may be used with floating point operand modifiers :ref:`abs` and :ref:`neg`. diff --git a/llvm/docs/AMDGPU/gfx904_mod_vop3_abs_neg.rst b/llvm/docs/AMDGPU/gfx904_mod_vop3_abs_neg.rst deleted file mode 100644 index f95424960425..000000000000 --- a/llvm/docs/AMDGPU/gfx904_mod_vop3_abs_neg.rst +++ /dev/null @@ -1,13 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid904_mod_vop3_abs_neg: - -m -=========================== - -This operand may be used with floating point operand modifiers :ref:`abs` and :ref:`neg`. diff --git a/llvm/docs/AMDGPU/gfx904_src.rst b/llvm/docs/AMDGPU/gfx904_src.rst new file mode 100644 index 000000000000..99c3f8a62481 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx904_src.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx904_src: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx904_src32_0.rst b/llvm/docs/AMDGPU/gfx904_src32_0.rst deleted file mode 100644 index dbc5ee387393..000000000000 --- a/llvm/docs/AMDGPU/gfx904_src32_0.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid904_src32_0: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx904_src32_1.rst b/llvm/docs/AMDGPU/gfx904_src32_1.rst deleted file mode 100644 index 38dcc4fc1268..000000000000 --- a/llvm/docs/AMDGPU/gfx904_src32_1.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid904_src32_1: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx904_src_1.rst b/llvm/docs/AMDGPU/gfx904_src_1.rst new file mode 100644 index 000000000000..0d9a0e2d9a19 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx904_src_1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx904_src_1: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx904_vdst.rst b/llvm/docs/AMDGPU/gfx904_vdst.rst new file mode 100644 index 000000000000..2819cdbbd0d7 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx904_vdst.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx904_vdst: + +vdst +==== + +Instruction output. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx904_vdst32_0.rst b/llvm/docs/AMDGPU/gfx904_vdst32_0.rst deleted file mode 100644 index 6eb8bdf5b506..000000000000 --- a/llvm/docs/AMDGPU/gfx904_vdst32_0.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid904_vdst32_0: - -vdst -=========================== - -Instruction output. - -*Size:* 1 dword. - -*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx906_mad_type_dev.rst b/llvm/docs/AMDGPU/gfx906_fx_operand.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx906_mad_type_dev.rst rename to llvm/docs/AMDGPU/gfx906_fx_operand.rst index 5b5d4b7c2829..1f6924d7ddc2 100644 --- a/llvm/docs/AMDGPU/gfx906_mad_type_dev.rst +++ b/llvm/docs/AMDGPU/gfx906_fx_operand.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid906_mad_type_dev: +.. _amdgpu_synid_gfx906_fx_operand: -fx -=========================== +FX Operand +========== This is an *f32* or *f16* operand depending on instruction modifiers: diff --git a/llvm/docs/AMDGPU/gfx906_m.rst b/llvm/docs/AMDGPU/gfx906_m.rst new file mode 100644 index 000000000000..797149ed4ca9 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx906_m.rst @@ -0,0 +1,13 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx906_m: + +m += + +This operand may be used with floating point operand modifiers :ref:`abs` and :ref:`neg`. diff --git a/llvm/docs/AMDGPU/gfx906_mod_sdwa_sext.rst b/llvm/docs/AMDGPU/gfx906_m_1.rst similarity index 85% rename from llvm/docs/AMDGPU/gfx906_mod_sdwa_sext.rst rename to llvm/docs/AMDGPU/gfx906_m_1.rst index dbb95496c104..ca96836eb8d3 100644 --- a/llvm/docs/AMDGPU/gfx906_mod_sdwa_sext.rst +++ b/llvm/docs/AMDGPU/gfx906_m_1.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid906_mod_sdwa_sext: +.. _amdgpu_synid_gfx906_m_1: m -=========================== += This operand may be used with integer operand modifier :ref:`sext`. diff --git a/llvm/docs/AMDGPU/gfx906_mod_dpp_sdwa_abs_neg.rst b/llvm/docs/AMDGPU/gfx906_mod_dpp_sdwa_abs_neg.rst deleted file mode 100644 index 3ddc6fda098d..000000000000 --- a/llvm/docs/AMDGPU/gfx906_mod_dpp_sdwa_abs_neg.rst +++ /dev/null @@ -1,13 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid906_mod_dpp_sdwa_abs_neg: - -m -=========================== - -This operand may be used with floating point operand modifiers :ref:`abs` and :ref:`neg`. diff --git a/llvm/docs/AMDGPU/gfx906_mod_vop3_abs_neg.rst b/llvm/docs/AMDGPU/gfx906_mod_vop3_abs_neg.rst deleted file mode 100644 index 1c1e498eb806..000000000000 --- a/llvm/docs/AMDGPU/gfx906_mod_vop3_abs_neg.rst +++ /dev/null @@ -1,13 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid906_mod_vop3_abs_neg: - -m -=========================== - -This operand may be used with floating point operand modifiers :ref:`abs` and :ref:`neg`. diff --git a/llvm/docs/AMDGPU/gfx906_src.rst b/llvm/docs/AMDGPU/gfx906_src.rst new file mode 100644 index 000000000000..2271b258adc2 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx906_src.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx906_src: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx906_src32_0.rst b/llvm/docs/AMDGPU/gfx906_src32_0.rst deleted file mode 100644 index d755bd98e1a8..000000000000 --- a/llvm/docs/AMDGPU/gfx906_src32_0.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid906_src32_0: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx906_src32_1.rst b/llvm/docs/AMDGPU/gfx906_src32_1.rst deleted file mode 100644 index 8176522793eb..000000000000 --- a/llvm/docs/AMDGPU/gfx906_src32_1.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid906_src32_1: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx906_src32_2.rst b/llvm/docs/AMDGPU/gfx906_src32_2.rst deleted file mode 100644 index 92e91c5b5416..000000000000 --- a/llvm/docs/AMDGPU/gfx906_src32_2.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid906_src32_2: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx906_src32_3.rst b/llvm/docs/AMDGPU/gfx906_src32_3.rst deleted file mode 100644 index 98fa3dc575bc..000000000000 --- a/llvm/docs/AMDGPU/gfx906_src32_3.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid906_src32_3: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`iconst` diff --git a/llvm/docs/AMDGPU/gfx906_src32_4.rst b/llvm/docs/AMDGPU/gfx906_src32_4.rst deleted file mode 100644 index 624f9dff211a..000000000000 --- a/llvm/docs/AMDGPU/gfx906_src32_4.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid906_src32_4: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst` diff --git a/llvm/docs/AMDGPU/gfx906_src_1.rst b/llvm/docs/AMDGPU/gfx906_src_1.rst new file mode 100644 index 000000000000..a5115e3e4b4a --- /dev/null +++ b/llvm/docs/AMDGPU/gfx906_src_1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx906_src_1: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx906_src_2.rst b/llvm/docs/AMDGPU/gfx906_src_2.rst new file mode 100644 index 000000000000..b67c6f8043ff --- /dev/null +++ b/llvm/docs/AMDGPU/gfx906_src_2.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx906_src_2: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx906_src_3.rst b/llvm/docs/AMDGPU/gfx906_src_3.rst new file mode 100644 index 000000000000..4c8dff4c48c7 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx906_src_3.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx906_src_3: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`iconst`, :ref:`ival` diff --git a/llvm/docs/AMDGPU/gfx906_src_4.rst b/llvm/docs/AMDGPU/gfx906_src_4.rst new file mode 100644 index 000000000000..8144df591016 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx906_src_4.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx906_src_4: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst`, :ref:`ival` diff --git a/llvm/docs/AMDGPU/gfx906_type_deviation.rst b/llvm/docs/AMDGPU/gfx906_type_deviation.rst new file mode 100644 index 000000000000..457ac91fe6de --- /dev/null +++ b/llvm/docs/AMDGPU/gfx906_type_deviation.rst @@ -0,0 +1,13 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx906_type_deviation: + +Type Deviation +============== + +*Type* of this operand differs from *type* :ref:`implied by the opcode`. This tag specifies actual operand *type*. diff --git a/llvm/docs/AMDGPU/gfx906_vdst.rst b/llvm/docs/AMDGPU/gfx906_vdst.rst new file mode 100644 index 000000000000..823f1bd2dfda --- /dev/null +++ b/llvm/docs/AMDGPU/gfx906_vdst.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx906_vdst: + +vdst +==== + +Instruction output. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx906_vdst32_0.rst b/llvm/docs/AMDGPU/gfx906_vdst32_0.rst deleted file mode 100644 index faf0a2d2f9dd..000000000000 --- a/llvm/docs/AMDGPU/gfx906_vdst32_0.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid906_vdst32_0: - -vdst -=========================== - -Instruction output. - -*Size:* 1 dword. - -*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx906_vsrc.rst b/llvm/docs/AMDGPU/gfx906_vsrc.rst new file mode 100644 index 000000000000..815d1a029fd3 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx906_vsrc.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx906_vsrc: + +vsrc +==== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx908_ret.rst b/llvm/docs/AMDGPU/gfx908_dst.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx908_ret.rst rename to llvm/docs/AMDGPU/gfx908_dst.rst index 20907addb368..80d8a407c18c 100644 --- a/llvm/docs/AMDGPU/gfx908_ret.rst +++ b/llvm/docs/AMDGPU/gfx908_dst.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid908_ret: +.. _amdgpu_synid_gfx908_dst: dst -=========================== +=== This is an input operand. It may optionally serve as a destination if :ref:`glc` is specified. diff --git a/llvm/docs/AMDGPU/gfx908_fx_operand.rst b/llvm/docs/AMDGPU/gfx908_fx_operand.rst new file mode 100644 index 000000000000..4eb9a8f94387 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx908_fx_operand.rst @@ -0,0 +1,16 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx908_fx_operand: + +FX Operand +========== + +This is an *f32* or *f16* operand depending on instruction modifiers: + +* Operand size is controlled by :ref:`m_op_sel_hi`. +* Location of 16-bit operand is controlled by :ref:`m_op_sel`. diff --git a/llvm/docs/AMDGPU/gfx908_m.rst b/llvm/docs/AMDGPU/gfx908_m.rst new file mode 100644 index 000000000000..3f6c0d387434 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx908_m.rst @@ -0,0 +1,13 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx908_m: + +m += + +This operand may be used with floating point operand modifiers :ref:`abs` and :ref:`neg`. diff --git a/llvm/docs/AMDGPU/gfx908_mod_sdwa_sext.rst b/llvm/docs/AMDGPU/gfx908_m_1.rst similarity index 85% rename from llvm/docs/AMDGPU/gfx908_mod_sdwa_sext.rst rename to llvm/docs/AMDGPU/gfx908_m_1.rst index 844c7433ac12..0e697e59d464 100644 --- a/llvm/docs/AMDGPU/gfx908_mod_sdwa_sext.rst +++ b/llvm/docs/AMDGPU/gfx908_m_1.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid908_mod_sdwa_sext: +.. _amdgpu_synid_gfx908_m_1: m -=========================== += This operand may be used with integer operand modifier :ref:`sext`. diff --git a/llvm/docs/AMDGPU/gfx908_mad_type_dev.rst b/llvm/docs/AMDGPU/gfx908_mad_type_dev.rst deleted file mode 100644 index e86e6d058cb5..000000000000 --- a/llvm/docs/AMDGPU/gfx908_mad_type_dev.rst +++ /dev/null @@ -1,16 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid908_mad_type_dev: - -fx -=========================== - -This is an *f32* or *f16* operand depending on instruction modifiers: - -* Operand size is controlled by :ref:`m_op_sel_hi`. -* Location of 16-bit operand is controlled by :ref:`m_op_sel`. diff --git a/llvm/docs/AMDGPU/gfx908_mod_dpp_sdwa_abs_neg.rst b/llvm/docs/AMDGPU/gfx908_mod_dpp_sdwa_abs_neg.rst deleted file mode 100644 index d89f9832eee6..000000000000 --- a/llvm/docs/AMDGPU/gfx908_mod_dpp_sdwa_abs_neg.rst +++ /dev/null @@ -1,13 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid908_mod_dpp_sdwa_abs_neg: - -m -=========================== - -This operand may be used with floating point operand modifiers :ref:`abs` and :ref:`neg`. diff --git a/llvm/docs/AMDGPU/gfx908_mod_vop3_abs_neg.rst b/llvm/docs/AMDGPU/gfx908_mod_vop3_abs_neg.rst deleted file mode 100644 index 6bdd76bb6c3b..000000000000 --- a/llvm/docs/AMDGPU/gfx908_mod_vop3_abs_neg.rst +++ /dev/null @@ -1,13 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid908_mod_vop3_abs_neg: - -m -=========================== - -This operand may be used with floating point operand modifiers :ref:`abs` and :ref:`neg`. diff --git a/llvm/docs/AMDGPU/gfx908_opt.rst b/llvm/docs/AMDGPU/gfx908_opt.rst index 950d8c3ab318..343f0c19e9bc 100644 --- a/llvm/docs/AMDGPU/gfx908_opt.rst +++ b/llvm/docs/AMDGPU/gfx908_opt.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid908_opt: +.. _amdgpu_synid_gfx908_opt: opt -=========================== +=== This is an optional operand. It must be used if and only if :ref:`glc` is specified. diff --git a/llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst b/llvm/docs/AMDGPU/gfx908_saddr.rst similarity index 57% rename from llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst rename to llvm/docs/AMDGPU/gfx908_saddr.rst index 050d60f249ec..950d709ccfb2 100644 --- a/llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst +++ b/llvm/docs/AMDGPU/gfx908_saddr.rst @@ -5,15 +5,15 @@ * * ************************************************** -.. _amdgpu_synid908_saddr_flat_global: +.. _amdgpu_synid_gfx908_saddr: saddr -=========================== +===== An optional 64-bit flat global address. Must be specified as :ref:`off` if not used. -See :ref:`vaddr` for description of available addressing modes. +See :ref:`vaddr` for description of available addressing modes. *Size:* 2 dwords. -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`ttmp`, :ref:`exec`, :ref:`off` +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`off` diff --git a/llvm/docs/AMDGPU/gfx908_offset_buf.rst b/llvm/docs/AMDGPU/gfx908_soffset.rst similarity index 51% rename from llvm/docs/AMDGPU/gfx908_offset_buf.rst rename to llvm/docs/AMDGPU/gfx908_soffset.rst index 7e39ac3bbb91..ff6e7a265b06 100644 --- a/llvm/docs/AMDGPU/gfx908_offset_buf.rst +++ b/llvm/docs/AMDGPU/gfx908_soffset.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid908_offset_buf: +.. _amdgpu_synid_gfx908_soffset: soffset -=========================== +======= An unsigned byte offset. *Size:* 1 dword. -*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` +*Operands:* :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx908_src.rst b/llvm/docs/AMDGPU/gfx908_src.rst new file mode 100644 index 000000000000..c9463fd3924c --- /dev/null +++ b/llvm/docs/AMDGPU/gfx908_src.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx908_src: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx908_src32_0.rst b/llvm/docs/AMDGPU/gfx908_src32_0.rst deleted file mode 100644 index 9491a6490ca1..000000000000 --- a/llvm/docs/AMDGPU/gfx908_src32_0.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid908_src32_0: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`constant`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx908_src32_1.rst b/llvm/docs/AMDGPU/gfx908_src32_1.rst deleted file mode 100644 index db717a93ac17..000000000000 --- a/llvm/docs/AMDGPU/gfx908_src32_1.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid908_src32_1: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx908_src32_2.rst b/llvm/docs/AMDGPU/gfx908_src32_2.rst deleted file mode 100644 index f375c555a4df..000000000000 --- a/llvm/docs/AMDGPU/gfx908_src32_2.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid908_src32_2: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx908_src32_4.rst b/llvm/docs/AMDGPU/gfx908_src32_4.rst deleted file mode 100644 index aab1b9978ac3..000000000000 --- a/llvm/docs/AMDGPU/gfx908_src32_4.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid908_src32_4: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`iconst` diff --git a/llvm/docs/AMDGPU/gfx908_src32_5.rst b/llvm/docs/AMDGPU/gfx908_src32_5.rst deleted file mode 100644 index 220dc443e891..000000000000 --- a/llvm/docs/AMDGPU/gfx908_src32_5.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid908_src32_5: - -src -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst` diff --git a/llvm/docs/AMDGPU/gfx908_src_1.rst b/llvm/docs/AMDGPU/gfx908_src_1.rst new file mode 100644 index 000000000000..42d945135d17 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx908_src_1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx908_src_1: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx908_src_2.rst b/llvm/docs/AMDGPU/gfx908_src_2.rst new file mode 100644 index 000000000000..6de88062d883 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx908_src_2.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx908_src_2: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx908_src32_3.rst b/llvm/docs/AMDGPU/gfx908_src_3.rst similarity index 69% rename from llvm/docs/AMDGPU/gfx908_src32_3.rst rename to llvm/docs/AMDGPU/gfx908_src_3.rst index ca445e87ef10..588d535b0d7f 100644 --- a/llvm/docs/AMDGPU/gfx908_src32_3.rst +++ b/llvm/docs/AMDGPU/gfx908_src_3.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid908_src32_3: +.. _amdgpu_synid_gfx908_src_3: src -=========================== +=== Instruction input. *Size:* 1 dword. -*Operands:* :ref:`v`, :ref:`constant` +*Operands:* :ref:`v`, :ref:`iconst`, :ref:`fconst` diff --git a/llvm/docs/AMDGPU/gfx908_src_4.rst b/llvm/docs/AMDGPU/gfx908_src_4.rst new file mode 100644 index 000000000000..c098de8d7289 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx908_src_4.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx908_src_4: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`iconst`, :ref:`ival` diff --git a/llvm/docs/AMDGPU/gfx908_src_5.rst b/llvm/docs/AMDGPU/gfx908_src_5.rst new file mode 100644 index 000000000000..0b95e8773254 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx908_src_5.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx908_src_5: + +src +=== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst`, :ref:`ival` diff --git a/llvm/docs/AMDGPU/gfx908_rsrc_buf.rst b/llvm/docs/AMDGPU/gfx908_srsrc.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx908_rsrc_buf.rst rename to llvm/docs/AMDGPU/gfx908_srsrc.rst index 832adfe0763e..359b18e007fd 100644 --- a/llvm/docs/AMDGPU/gfx908_rsrc_buf.rst +++ b/llvm/docs/AMDGPU/gfx908_srsrc.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid908_rsrc_buf: +.. _amdgpu_synid_gfx908_srsrc: srsrc -=========================== +===== Buffer resource constant which defines the address and characteristics of the buffer in memory. diff --git a/llvm/docs/AMDGPU/gfx908_type_dev.rst b/llvm/docs/AMDGPU/gfx908_type_dev.rst deleted file mode 100644 index 1321aae8e260..000000000000 --- a/llvm/docs/AMDGPU/gfx908_type_dev.rst +++ /dev/null @@ -1,13 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid908_type_dev: - -Type deviation -=========================== - -*Type* of this operand differs from *type* :ref:`implied by the opcode`. This tag specifies actual operand *type*. diff --git a/llvm/docs/AMDGPU/gfx908_type_deviation.rst b/llvm/docs/AMDGPU/gfx908_type_deviation.rst new file mode 100644 index 000000000000..f285d08b3030 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx908_type_deviation.rst @@ -0,0 +1,13 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx908_type_deviation: + +Type Deviation +============== + +*Type* of this operand differs from *type* :ref:`implied by the opcode`. This tag specifies actual operand *type*. diff --git a/llvm/docs/AMDGPU/gfx908_vaddr.rst b/llvm/docs/AMDGPU/gfx908_vaddr.rst new file mode 100644 index 000000000000..3b785ff7bc8f --- /dev/null +++ b/llvm/docs/AMDGPU/gfx908_vaddr.rst @@ -0,0 +1,20 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx908_vaddr: + +vaddr +===== + +A 64-bit flat global address or a 32-bit offset depending on addressing mode: + +* Address = :ref:`vaddr` + :ref:`offset13s`. :ref:`vaddr` is a 64-bit address. This mode is indicated by :ref:`saddr` set to :ref:`off`. +* Address = :ref:`saddr` + :ref:`vaddr` + :ref:`offset13s`. :ref:`vaddr` is a 32-bit offset. This mode is used when :ref:`saddr` is not :ref:`off`. + +*Size:* 1 or 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx908_addr_buf.rst b/llvm/docs/AMDGPU/gfx908_vaddr_1.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx908_addr_buf.rst rename to llvm/docs/AMDGPU/gfx908_vaddr_1.rst index 9dc593be69eb..c749bd43943c 100644 --- a/llvm/docs/AMDGPU/gfx908_addr_buf.rst +++ b/llvm/docs/AMDGPU/gfx908_vaddr_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid908_addr_buf: +.. _amdgpu_synid_gfx908_vaddr_1: vaddr -=========================== +===== This is an optional operand which may specify offset and/or index. diff --git a/llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst b/llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst deleted file mode 100644 index d7da4774a94e..000000000000 --- a/llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst +++ /dev/null @@ -1,20 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid908_vaddr_flat_global: - -vaddr -=========================== - -A 64-bit flat global address or a 32-bit offset depending on addressing mode: - -* Address = :ref:`vaddr` + :ref:`offset13s`. :ref:`vaddr` is a 64-bit address. This mode is indicated by :ref:`saddr` set to :ref:`off`. -* Address = :ref:`saddr` + :ref:`vaddr` + :ref:`offset13s`. :ref:`vaddr` is a 32-bit offset. This mode is used when :ref:`saddr` is not :ref:`off`. - -*Size:* 1 or 2 dwords. - -*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx908_vdata32_0.rst b/llvm/docs/AMDGPU/gfx908_vdata.rst similarity index 85% rename from llvm/docs/AMDGPU/gfx908_vdata32_0.rst rename to llvm/docs/AMDGPU/gfx908_vdata.rst index 7571818881d8..6db6e5740be3 100644 --- a/llvm/docs/AMDGPU/gfx908_vdata32_0.rst +++ b/llvm/docs/AMDGPU/gfx908_vdata.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid908_vdata32_0: +.. _amdgpu_synid_gfx908_vdata: vdata -=========================== +===== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx908_data_buf_atomic32.rst b/llvm/docs/AMDGPU/gfx908_vdata_1.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx908_data_buf_atomic32.rst rename to llvm/docs/AMDGPU/gfx908_vdata_1.rst index 03163f55fe54..7d578111db97 100644 --- a/llvm/docs/AMDGPU/gfx908_data_buf_atomic32.rst +++ b/llvm/docs/AMDGPU/gfx908_vdata_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid908_data_buf_atomic32: +.. _amdgpu_synid_gfx908_vdata_1: vdata -=========================== +===== Input data for an atomic instruction. diff --git a/llvm/docs/AMDGPU/gfx908_dst_flat_atomic32.rst b/llvm/docs/AMDGPU/gfx908_vdst.rst similarity index 88% rename from llvm/docs/AMDGPU/gfx908_dst_flat_atomic32.rst rename to llvm/docs/AMDGPU/gfx908_vdst.rst index 045058314cbb..f3b952bc2bbe 100644 --- a/llvm/docs/AMDGPU/gfx908_dst_flat_atomic32.rst +++ b/llvm/docs/AMDGPU/gfx908_vdst.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid908_dst_flat_atomic32: +.. _amdgpu_synid_gfx908_vdst: vdst -=========================== +==== Data returned by a 32-bit atomic flat instruction. diff --git a/llvm/docs/AMDGPU/gfx908_vdst32_0.rst b/llvm/docs/AMDGPU/gfx908_vdst32_0.rst deleted file mode 100644 index ed2214a8fbed..000000000000 --- a/llvm/docs/AMDGPU/gfx908_vdst32_0.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid908_vdst32_0: - -vdst -=========================== - -Instruction output. - -*Size:* 1 dword. - -*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx908_vdst_1.rst b/llvm/docs/AMDGPU/gfx908_vdst_1.rst new file mode 100644 index 000000000000..985f754ce93a --- /dev/null +++ b/llvm/docs/AMDGPU/gfx908_vdst_1.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx908_vdst_1: + +vdst +==== + +Instruction output. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx908_adst32_0.rst b/llvm/docs/AMDGPU/gfx908_vdst_2.rst similarity index 85% rename from llvm/docs/AMDGPU/gfx908_adst32_0.rst rename to llvm/docs/AMDGPU/gfx908_vdst_2.rst index 80546fa1c832..4eb42310a67c 100644 --- a/llvm/docs/AMDGPU/gfx908_adst32_0.rst +++ b/llvm/docs/AMDGPU/gfx908_vdst_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid908_adst32_0: +.. _amdgpu_synid_gfx908_vdst_2: -adst -=========================== +vdst +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx908_adst128_0.rst b/llvm/docs/AMDGPU/gfx908_vdst_3.rst similarity index 84% rename from llvm/docs/AMDGPU/gfx908_adst128_0.rst rename to llvm/docs/AMDGPU/gfx908_vdst_3.rst index 23c7f9db057b..9661df57003e 100644 --- a/llvm/docs/AMDGPU/gfx908_adst128_0.rst +++ b/llvm/docs/AMDGPU/gfx908_vdst_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid908_adst128_0: +.. _amdgpu_synid_gfx908_vdst_3: -adst -=========================== +vdst +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx908_adst512_0.rst b/llvm/docs/AMDGPU/gfx908_vdst_4.rst similarity index 84% rename from llvm/docs/AMDGPU/gfx908_adst512_0.rst rename to llvm/docs/AMDGPU/gfx908_vdst_4.rst index 446eb02bf035..dab8c5b56fc5 100644 --- a/llvm/docs/AMDGPU/gfx908_adst512_0.rst +++ b/llvm/docs/AMDGPU/gfx908_vdst_4.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid908_adst512_0: +.. _amdgpu_synid_gfx908_vdst_4: -adst -=========================== +vdst +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx908_adst1024_0.rst b/llvm/docs/AMDGPU/gfx908_vdst_5.rst similarity index 84% rename from llvm/docs/AMDGPU/gfx908_adst1024_0.rst rename to llvm/docs/AMDGPU/gfx908_vdst_5.rst index 3dfe45ede469..1112a441cc6d 100644 --- a/llvm/docs/AMDGPU/gfx908_adst1024_0.rst +++ b/llvm/docs/AMDGPU/gfx908_vdst_5.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid908_adst1024_0: +.. _amdgpu_synid_gfx908_vdst_5: -adst -=========================== +vdst +==== Instruction output. diff --git a/llvm/docs/AMDGPU/gfx908_vsrc.rst b/llvm/docs/AMDGPU/gfx908_vsrc.rst new file mode 100644 index 000000000000..0c3ad8a0ae06 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx908_vsrc.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx908_vsrc: + +vsrc +==== + +Instruction input. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx908_vsrc32_0.rst b/llvm/docs/AMDGPU/gfx908_vsrc32_0.rst deleted file mode 100644 index c990b504515b..000000000000 --- a/llvm/docs/AMDGPU/gfx908_vsrc32_0.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid908_vsrc32_0: - -vsrc -=========================== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx908_asrc32_0.rst b/llvm/docs/AMDGPU/gfx908_vsrc_1.rst similarity index 84% rename from llvm/docs/AMDGPU/gfx908_asrc32_0.rst rename to llvm/docs/AMDGPU/gfx908_vsrc_1.rst index 8e46317254df..373cb2634d4a 100644 --- a/llvm/docs/AMDGPU/gfx908_asrc32_0.rst +++ b/llvm/docs/AMDGPU/gfx908_vsrc_1.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid908_asrc32_0: +.. _amdgpu_synid_gfx908_vsrc_1: -asrc -=========================== +vsrc +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx908_vasrc64_0.rst b/llvm/docs/AMDGPU/gfx908_vsrc_2.rst similarity index 85% rename from llvm/docs/AMDGPU/gfx908_vasrc64_0.rst rename to llvm/docs/AMDGPU/gfx908_vsrc_2.rst index bef80d9637a9..d70ed03718c7 100644 --- a/llvm/docs/AMDGPU/gfx908_vasrc64_0.rst +++ b/llvm/docs/AMDGPU/gfx908_vsrc_2.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid908_vasrc64_0: +.. _amdgpu_synid_gfx908_vsrc_2: -vasrc -=========================== +vsrc +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx908_asrc128_0.rst b/llvm/docs/AMDGPU/gfx908_vsrc_3.rst similarity index 84% rename from llvm/docs/AMDGPU/gfx908_asrc128_0.rst rename to llvm/docs/AMDGPU/gfx908_vsrc_3.rst index 91af6b7357bb..2456afbbf97c 100644 --- a/llvm/docs/AMDGPU/gfx908_asrc128_0.rst +++ b/llvm/docs/AMDGPU/gfx908_vsrc_3.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid908_asrc128_0: +.. _amdgpu_synid_gfx908_vsrc_3: -asrc -=========================== +vsrc +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx908_vasrc32_0.rst b/llvm/docs/AMDGPU/gfx908_vsrc_4.rst similarity index 85% rename from llvm/docs/AMDGPU/gfx908_vasrc32_0.rst rename to llvm/docs/AMDGPU/gfx908_vsrc_4.rst index 52aaaadc5808..e3c8c3fef7a0 100644 --- a/llvm/docs/AMDGPU/gfx908_vasrc32_0.rst +++ b/llvm/docs/AMDGPU/gfx908_vsrc_4.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid908_vasrc32_0: +.. _amdgpu_synid_gfx908_vsrc_4: -vasrc -=========================== +vsrc +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx908_asrc512_0.rst b/llvm/docs/AMDGPU/gfx908_vsrc_5.rst similarity index 84% rename from llvm/docs/AMDGPU/gfx908_asrc512_0.rst rename to llvm/docs/AMDGPU/gfx908_vsrc_5.rst index 59e22040c222..b51ca84b74c1 100644 --- a/llvm/docs/AMDGPU/gfx908_asrc512_0.rst +++ b/llvm/docs/AMDGPU/gfx908_vsrc_5.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid908_asrc512_0: +.. _amdgpu_synid_gfx908_vsrc_5: -asrc -=========================== +vsrc +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx908_asrc1024_0.rst b/llvm/docs/AMDGPU/gfx908_vsrc_6.rst similarity index 84% rename from llvm/docs/AMDGPU/gfx908_asrc1024_0.rst rename to llvm/docs/AMDGPU/gfx908_vsrc_6.rst index 00e1fc7f0f6e..f11d027f24d7 100644 --- a/llvm/docs/AMDGPU/gfx908_asrc1024_0.rst +++ b/llvm/docs/AMDGPU/gfx908_vsrc_6.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid908_asrc1024_0: +.. _amdgpu_synid_gfx908_vsrc_6: -asrc -=========================== +vsrc +==== Instruction input. diff --git a/llvm/docs/AMDGPU/gfx90a_src_10.rst b/llvm/docs/AMDGPU/gfx90a_src_10.rst index d53a92673af0..b71f38f2945e 100644 --- a/llvm/docs/AMDGPU/gfx90a_src_10.rst +++ b/llvm/docs/AMDGPU/gfx90a_src_10.rst @@ -14,4 +14,4 @@ Instruction input. *Size:* 8 dwords. -*Operands:* :ref:`v`, :ref:`a`, :ref:`constant` +*Operands:* :ref:`v`, :ref:`a`, :ref:`iconst`, :ref:`fconst` diff --git a/llvm/docs/AMDGPU/gfx90a_src_11.rst b/llvm/docs/AMDGPU/gfx90a_src_11.rst index bfcf55f08aa2..cb1ea4b97be5 100644 --- a/llvm/docs/AMDGPU/gfx90a_src_11.rst +++ b/llvm/docs/AMDGPU/gfx90a_src_11.rst @@ -14,4 +14,4 @@ Instruction input. *Size:* 2 dwords. -*Operands:* :ref:`v`, :ref:`a`, :ref:`constant` +*Operands:* :ref:`v`, :ref:`a`, :ref:`iconst`, :ref:`fconst` diff --git a/llvm/docs/AMDGPU/gfx90a_src_3.rst b/llvm/docs/AMDGPU/gfx90a_src_3.rst index 7646f4baa9d6..687f53ac20ce 100644 --- a/llvm/docs/AMDGPU/gfx90a_src_3.rst +++ b/llvm/docs/AMDGPU/gfx90a_src_3.rst @@ -14,4 +14,4 @@ Instruction input. *Size:* 1 dword. -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst`, :ref:`literal` +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst`, :ref:`ival`, :ref:`literal` diff --git a/llvm/docs/AMDGPU/gfx90a_src_4.rst b/llvm/docs/AMDGPU/gfx90a_src_4.rst index 691af89ef8a6..ec6580d90b73 100644 --- a/llvm/docs/AMDGPU/gfx90a_src_4.rst +++ b/llvm/docs/AMDGPU/gfx90a_src_4.rst @@ -14,4 +14,4 @@ Instruction input. *Size:* 1 dword. -*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst` +*Operands:* :ref:`v`, :ref:`s`, :ref:`flat_scratch`, :ref:`xnack_mask`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`iconst`, :ref:`ival` diff --git a/llvm/docs/AMDGPU/gfx90a_src_6.rst b/llvm/docs/AMDGPU/gfx90a_src_6.rst index 6c2579912816..75faedd0326f 100644 --- a/llvm/docs/AMDGPU/gfx90a_src_6.rst +++ b/llvm/docs/AMDGPU/gfx90a_src_6.rst @@ -14,4 +14,4 @@ Instruction input. *Size:* 1 dword. -*Operands:* :ref:`v`, :ref:`constant` +*Operands:* :ref:`v`, :ref:`iconst`, :ref:`fconst` diff --git a/llvm/docs/AMDGPU/gfx90a_src_7.rst b/llvm/docs/AMDGPU/gfx90a_src_7.rst index 968984b379e7..d63987f499ec 100644 --- a/llvm/docs/AMDGPU/gfx90a_src_7.rst +++ b/llvm/docs/AMDGPU/gfx90a_src_7.rst @@ -14,4 +14,4 @@ Instruction input. *Size:* 4 dwords. -*Operands:* :ref:`v`, :ref:`a`, :ref:`constant` +*Operands:* :ref:`v`, :ref:`a`, :ref:`iconst`, :ref:`fconst` diff --git a/llvm/docs/AMDGPU/gfx90a_src_8.rst b/llvm/docs/AMDGPU/gfx90a_src_8.rst index dfcd66e98d0c..8cfa04e04d91 100644 --- a/llvm/docs/AMDGPU/gfx90a_src_8.rst +++ b/llvm/docs/AMDGPU/gfx90a_src_8.rst @@ -14,4 +14,4 @@ Instruction input. *Size:* 16 dwords. -*Operands:* :ref:`v`, :ref:`a`, :ref:`constant` +*Operands:* :ref:`v`, :ref:`a`, :ref:`iconst`, :ref:`fconst` diff --git a/llvm/docs/AMDGPU/gfx90a_src_9.rst b/llvm/docs/AMDGPU/gfx90a_src_9.rst index fbf03083e0da..d0c9bfb29140 100644 --- a/llvm/docs/AMDGPU/gfx90a_src_9.rst +++ b/llvm/docs/AMDGPU/gfx90a_src_9.rst @@ -14,4 +14,4 @@ Instruction input. *Size:* 32 dwords. -*Operands:* :ref:`v`, :ref:`a`, :ref:`constant` +*Operands:* :ref:`v`, :ref:`a`, :ref:`iconst`, :ref:`fconst` diff --git a/llvm/docs/AMDGPU/gfx90a_type_deviation.rst b/llvm/docs/AMDGPU/gfx90a_type_deviation.rst index 8da1cd77cb3f..6490ae91ee0b 100644 --- a/llvm/docs/AMDGPU/gfx90a_type_deviation.rst +++ b/llvm/docs/AMDGPU/gfx90a_type_deviation.rst @@ -10,4 +10,4 @@ Type Deviation ============== -*Type* of this operand differs from *type* :ref:`implied by the opcode`. This tag specifies actual operand *type*. +*Type* of this operand differs from *type* :ref:`implied by the opcode`. This tag specifies actual operand *type*. diff --git a/llvm/docs/AMDGPU/gfx9_type_deviation.rst b/llvm/docs/AMDGPU/gfx9_type_deviation.rst index 47a5874a29c9..a72f10745f55 100644 --- a/llvm/docs/AMDGPU/gfx9_type_deviation.rst +++ b/llvm/docs/AMDGPU/gfx9_type_deviation.rst @@ -10,4 +10,4 @@ Type Deviation ============== -*Type* of this operand differs from *type* :ref:`implied by the opcode`. This tag specifies actual operand *type*. +*Type* of this operand differs from *type* :ref:`implied by the opcode`. This tag specifies actual operand *type*. diff --git a/llvm/docs/AMDGPUInstructionNotation.rst b/llvm/docs/AMDGPUInstructionNotation.rst index c03dd3d12e1d..21b4d3bea340 100644 --- a/llvm/docs/AMDGPUInstructionNotation.rst +++ b/llvm/docs/AMDGPUInstructionNotation.rst @@ -54,15 +54,40 @@ Notation An operand is described using the following notation: - *...* + *...* Where: +* *kind* is an optional prefix describing operand :ref:`kind`. * *name* is a link to a description of the operand. -* *tags* are optional. They are used to indicate special operand properties: +* *tags* are optional. They are used to indicate :ref:`special operand properties`. + +.. _amdgpu_syn_instruction_operand_kinds: + +Operand Kinds +^^^^^^^^^^^^^ + +Operand kind indicates which values are accepted by the operand. + +* Operands which only accept *vector* registers are labelled with 'v' prefix. +* Operands which only accept *scalar* values are labelled with 's' prefix. +* Operands which accept both *vector* registers and *scalar* values have no prefix. + +Examples: + +.. parsed-literal:: + + vdata // operand only accepts vector registers + sdst // operand only accepts scalar registers + src1 // operand accepts both scalar and vector registers .. _amdgpu_syn_instruction_operand_tags: +Operand Tags +^^^^^^^^^^^^ + +Operand tags indicate special operand properties. + ============== ================================================================================= Operand tag Meaning ============== ================================================================================= diff --git a/llvm/docs/AMDGPUInstructionSyntax.rst b/llvm/docs/AMDGPUInstructionSyntax.rst index 04c5180c6acc..e3fabe0df1e9 100644 --- a/llvm/docs/AMDGPUInstructionSyntax.rst +++ b/llvm/docs/AMDGPUInstructionSyntax.rst @@ -30,10 +30,29 @@ Opcode Mnemonic Opcode mnemonic describes opcode semantics and may include one or more suffices in this order: +* :ref:`Packing suffix`. * :ref:`Destination operand type suffix`. * :ref:`Source operand type suffix`. * :ref:`Encoding suffix`. +.. _amdgpu_syn_instruction_pk: + +Packing Suffix +~~~~~~~~~~~~~~ + +Most instructions which operate on packed data have a *_pk* suffix. +Unless otherwise :ref:`noted`, +these instructions operate on and produce packed data composed of +two values. The type of values is indicated by +:ref:`type suffices`. + +For example, the following instruction sums up two pairs of f16 values +and produces a pair of f16 values: + +.. parsed-literal:: + + v_pk_add_f16 v1, v2, v3 // Each operand has f16x2 type + .. _amdgpu_syn_instruction_type: Type and Size Suffices @@ -51,15 +70,15 @@ to other kinds of operands such as *addresses*, *offsets* and so on. The following table enumerates the most frequently used type suffices. - ============================================ ======================= ================= + ============================================ ======================= ============================ Type Suffices Packed instruction? Data Type - ============================================ ======================= ================= + ============================================ ======================= ============================ _b512, _b256, _b128, _b64, _b32, _b16, _b8 No Bits. _u64, _u32, _u16, _u8 No Unsigned integer. _i64, _i32, _i16, _i8 No Signed integer. _f64, _f32, _f16 No Floating-point. - _b16, _u16, _i16, _f16 Yes Packed. - ============================================ ======================= ================= + _b16, _u16, _i16, _f16 Yes Packed (b16x2, u16x2, etc). + ============================================ ======================= ============================ Instructions which have no type suffices are assumed to operate with typeless data. The size of data is specified by size suffices: @@ -131,14 +150,14 @@ To force specific encoding, one can add a suffix to the opcode of the instructio =================================================== ================= Encoding Encoding Suffix =================================================== ================= - Native 32-bit encoding (*VOP1*, *VOP2* or *VOPC*) _e32 + *VOP1*, *VOP2* and *VOPC* (32-bit) encoding _e32 *VOP3* (64-bit) encoding _e64 *DPP* encoding _dpp *SDWA* encoding _sdwa =================================================== ================= These suffices are used in this reference to indicate the assumed encoding. -When no suffix is specified, a native encoding is implied. +When no suffix is specified, native instruction encoding is implied. Operands ======== @@ -146,7 +165,7 @@ Operands Syntax ~~~~~~ -Syntax of most operands is described :doc:`in this document`. +Syntax of generic operands is described :doc:`in this document`. For detailed information about operands follow *operand links* in GPU-specific documents: diff --git a/llvm/docs/AMDGPUModifierSyntax.rst b/llvm/docs/AMDGPUModifierSyntax.rst index 6f8e37f2e7d6..a39f13051c9a 100644 --- a/llvm/docs/AMDGPUModifierSyntax.rst +++ b/llvm/docs/AMDGPUModifierSyntax.rst @@ -25,19 +25,19 @@ Modifiers DS Modifiers ------------ -.. _amdgpu_synid_ds_offset8: +.. _amdgpu_synid_ds_offset80: -offset8 +offset0 ~~~~~~~ -Specifies an immediate unsigned 8-bit offset, in bytes. The default value is 0. +Specifies first 8-bit offset, in bytes. The default value is 0. -Used with DS instructions which have 2 addresses. +Used with DS instructions that expect two addresses. =================== ==================================================================== Syntax Description =================== ==================================================================== - offset:{0..0xFF} Specifies an unsigned 8-bit offset as a positive + offset0:{0..0xFF} Specifies an unsigned 8-bit offset as a positive :ref:`integer number ` or an :ref:`absolute expression`. =================== ==================================================================== @@ -46,18 +46,43 @@ Examples: .. parsed-literal:: - offset:0xff - offset:2-x - offset:-x-y + offset0:0xff + offset0:2-x + offset0:-x-y + +.. _amdgpu_synid_ds_offset81: + +offset1 +~~~~~~~ + +Specifies second 8-bit offset, in bytes. The default value is 0. + +Used with DS instructions that expect two addresses. + + =================== ==================================================================== + Syntax Description + =================== ==================================================================== + offset1:{0..0xFF} Specifies an unsigned 8-bit offset as a positive + :ref:`integer number ` + or an :ref:`absolute expression`. + =================== ==================================================================== + +Examples: + +.. parsed-literal:: + + offset1:0xff + offset1:2-x + offset1:-x-y .. _amdgpu_synid_ds_offset16: -offset16 -~~~~~~~~ +offset +~~~~~~ -Specifies an immediate unsigned 16-bit offset, in bytes. The default value is 0. +Specifies a 16-bit offset, in bytes. The default value is 0. -Used with DS instructions which have 1 address. +Used with DS instructions that expect a single address. ==================== ==================================================================== Syntax Description @@ -1459,6 +1484,34 @@ Examples: op_sel:[0,0] op_sel:[0,1] +.. _amdgpu_synid_dpp_op_sel: + +dpp_op_sel +~~~~~~~~~~ + +Special version of *op_sel* used for *permlane* opcodes to specify +dpp-like mode bits - :ref:`fi` and +:ref:`bound_ctrl`. + +GFX10 only. + + ======================================== ============================================================ + Syntax Description + ======================================== ============================================================ + op_sel:[{0..1},{0..1}] First bit specifies :ref:`fi`, second + bit specifies :ref:`bound_ctrl`. + ======================================== ============================================================ + +Note: numeric values may be specified as either +:ref:`integer numbers` or +:ref:`absolute expressions`. + +Examples: + +.. parsed-literal:: + + op_sel:[0,0] + .. _amdgpu_synid_clamp: clamp