From 9a48438832a0216eff7ae92a8e2f8ad71e2bc2cc Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Thu, 31 Jan 2019 23:22:39 +0000 Subject: [PATCH] [WebAssembly] Fix a regression selecting negative build_vector lanes Summary: The custom lowering introduced in rL352592 creates build_vector nodes with negative i32 operands, but these operands did not meet the value range constraints necessary to match build_vector nodes. This CL fixes the issue by removing the unnecessary constraints. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish Differential Revision: https://reviews.llvm.org/D57481 llvm-svn: 352813 --- llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 2 +- llvm/test/CodeGen/WebAssembly/simd-build-vector.ll | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index b7ecd49c7937..ab0f48c9a1e1 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -30,7 +30,7 @@ defm "" : ARGUMENT; // Constrained immediate argument types foreach SIZE = [8, 16] in def ImmI#SIZE : ImmLeaf; foreach SIZE = [2, 4, 8, 16, 32] in def LaneIdx#SIZE : ImmLeaf; diff --git a/llvm/test/CodeGen/WebAssembly/simd-build-vector.ll b/llvm/test/CodeGen/WebAssembly/simd-build-vector.ll index ab08ef4be7db..41a320c92f70 100644 --- a/llvm/test/CodeGen/WebAssembly/simd-build-vector.ll +++ b/llvm/test/CodeGen/WebAssembly/simd-build-vector.ll @@ -23,12 +23,12 @@ define <8 x i16> @same_const_one_replaced_i8x16(i16 %x) { ; CHECK-LABEL: different_const_one_replaced_i8x16: ; CHECK-NEXT: .functype different_const_one_replaced_i8x16 (i32) -> (v128) -; CHECK-NEXT: v128.const $push[[L0:[0-9]+]]=, 1, 2, 3, 4, 5, 0, 7, 8 +; CHECK-NEXT: v128.const $push[[L0:[0-9]+]]=, 1, -2, 3, -4, 5, 0, 7, -8 ; CHECK-NEXT: i16x8.replace_lane $push[[L1:[0-9]+]]=, $pop[[L0]], 5, $0 ; CHECK-NEXT: return $pop[[L1]] define <8 x i16> @different_const_one_replaced_i8x16(i16 %x) { %v = insertelement - <8 x i16> , + <8 x i16> , i16 %x, i32 5 ret <8 x i16> %v