From c14602b318f2d439af254710095684c1f5a8a386 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 13 Nov 2023 22:37:50 -0800 Subject: [PATCH] [RISCV] Add PseudoCCADDIW/SLLW/SRLW/SRAW/SLLIW/SRLIW/SRAIW to RISCVOptWInstrs. These can be treated simlarly to PseudoCCADDW/SUBW. --- llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp index e73cab58d701..a2954b697252 100644 --- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp +++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp @@ -482,9 +482,16 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST, break; case RISCV::PseudoCCADDW: + case RISCV::PseudoCCADDIW: case RISCV::PseudoCCSUBW: - // Returns operand 4 or an ADDW/SUBW of operands 5 and 6. We only need to - // check if operand 4 is sign extended. + case RISCV::PseudoCCSLLW: + case RISCV::PseudoCCSRLW: + case RISCV::PseudoCCSRAW: + case RISCV::PseudoCCSLLIW: + case RISCV::PseudoCCSRLIW: + case RISCV::PseudoCCSRAIW: + // Returns operand 4 or an ADDW/SUBW/etc. of operands 5 and 6. We only + // need to check if operand 4 is sign extended. if (!AddRegDefToWorkList(MI->getOperand(4).getReg())) return false; break;