intel/llvm
1
0
Fork 0
mirror of https://github.com/intel/llvm.git synced 2026-01-29 04:16:38 +08:00
Code Issues Packages Projects Releases Wiki Activity

[mlir][sparse] fixed naming consistency (#73053)

Browse Source 
All DLT related methods have DLT at end, removed stale TODO
This commit is contained in:
Aart Bik
2023-11-21 16:26:09 -08:00
committed by GitHub
parent a756a6b97e
commit d213220a9a
4 changed files with 10 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
View File

@@ -1341,7 +1341,7 @@ struct SparseAssembleOpConverter : public OpConversionPattern<AssembleOp> {
continue;
}
if (isDLTWithPos(dlt)) {
if (isWithPosDLT(dlt)) {
assert(isCompressedDLT(dlt) || isLooseCompressedDLT(dlt));
if (isLooseCompressedDLT(dlt)) {
memSize = rewriter.create<arith::MulIOp>(loc, memSize, c2);
@@ -1356,7 +1356,7 @@ struct SparseAssembleOpConverter : public OpConversionPattern<AssembleOp> {
memSize = genIndexLoad(rewriter, loc, desc.getPosMemRef(lvl), posBack);
posBack = rewriter.create<arith::SubIOp>(loc, posBack, c1);
}
assert(isDLTWithCrd(dlt) && lvl <= trailCOOStart);
assert(isWithCrdDLT(dlt) && lvl <= trailCOOStart);
// FIXME: This seems to be unnecessarily complex, can we simplify it?
if (lvl == trailCOOStart) {
Value cooSz = rewriter.create<arith::MulIOp>(