From f67158422c3bf37ce3884f4579a93f65e083e7fa Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Thu, 9 Nov 2023 14:43:45 +0100 Subject: [PATCH] [CFIInstrInserter] Use number of supported registers (NFC) (#71797) This makes use of the more accurate register number introduced in PR #70222 to avoid CFI calculations for unsupported registers. This has basically no impact right now, but results in a 0.2% compile-time improvement at O0 when applied on top of #70958. The reason is that the extra registers that PR adds push the `BitVector` out of the `SmallVector` space, which results in an outsized impact. (This does make me wonder whether `BitVector` should accept an `N` template parameter to allow using a larger `SmallVector`...) --- llvm/lib/CodeGen/CFIInstrInserter.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/CodeGen/CFIInstrInserter.cpp b/llvm/lib/CodeGen/CFIInstrInserter.cpp index 6a024287f002..87b062a16df1 100644 --- a/llvm/lib/CodeGen/CFIInstrInserter.cpp +++ b/llvm/lib/CodeGen/CFIInstrInserter.cpp @@ -151,7 +151,7 @@ void CFIInstrInserter::calculateCFAInfo(MachineFunction &MF) { Register InitialRegister = MF.getSubtarget().getFrameLowering()->getInitialCFARegister(MF); InitialRegister = TRI.getDwarfRegNum(InitialRegister, true); - unsigned NumRegs = TRI.getNumRegs(); + unsigned NumRegs = TRI.getNumSupportedRegs(MF); // Initialize MBBMap. for (MachineBasicBlock &MBB : MF) { @@ -181,7 +181,7 @@ void CFIInstrInserter::calculateOutgoingCFAInfo(MBBCFAInfo &MBBInfo) { MachineFunction *MF = MBBInfo.MBB->getParent(); const std::vector &Instrs = MF->getFrameInstructions(); const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo(); - unsigned NumRegs = TRI.getNumRegs(); + unsigned NumRegs = TRI.getNumSupportedRegs(*MF); BitVector CSRSaved(NumRegs), CSRRestored(NumRegs); // Determine cfa offset and register set by the block.